?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
inet: frag: enforce memory limits earlier
[linux/fpc-iii.git] / drivers / net / phy / marvell.c
blobc60c147708c45db519123dd8155ef82a301592e0
1 /*
2 * drivers/net/phy/marvell.c
3 *
4 * Driver for Marvell PHYs
5 *
6 * Author: Andy Fleming
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
9 *
10 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 */
18 #include <linux/kernel.h>
19 #include <linux/string.h>
20 #include <linux/errno.h>
21 #include <linux/unistd.h>
22 #include <linux/interrupt.h>
23 #include <linux/init.h>
24 #include <linux/delay.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/spinlock.h>
29 #include <linux/mm.h>
30 #include <linux/module.h>
31 #include <linux/mii.h>
32 #include <linux/ethtool.h>
33 #include <linux/phy.h>
34 #include <linux/marvell_phy.h>
35 #include <linux/of.h>
36
37 #include <linux/io.h>
38 #include <asm/irq.h>
39 #include <linux/uaccess.h>
40
41 #define MII_MARVELL_PHY_PAGE 22
42
43 #define MII_M1011_IEVENT 0x13
44 #define MII_M1011_IEVENT_CLEAR 0x0000
45
46 #define MII_M1011_IMASK 0x12
47 #define MII_M1011_IMASK_INIT 0x6400
48 #define MII_M1011_IMASK_CLEAR 0x0000
49
50 #define MII_M1011_PHY_SCR 0x10
51 #define MII_M1011_PHY_SCR_MDI 0x0000
52 #define MII_M1011_PHY_SCR_MDI_X 0x0020
53 #define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
54
55 #define MII_M1145_PHY_EXT_ADDR_PAGE 0x16
56 #define MII_M1145_PHY_EXT_SR 0x1b
57 #define MII_M1145_PHY_EXT_CR 0x14
58 #define MII_M1145_RGMII_RX_DELAY 0x0080
59 #define MII_M1145_RGMII_TX_DELAY 0x0002
60 #define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
61 #define MII_M1145_HWCFG_MODE_MASK 0xf
62 #define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
63
64 #define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
65 #define MII_M1145_HWCFG_MODE_MASK 0xf
66 #define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
67
68 #define MII_M1111_PHY_LED_CONTROL 0x18
69 #define MII_M1111_PHY_LED_DIRECT 0x4100
70 #define MII_M1111_PHY_LED_COMBINE 0x411c
71 #define MII_M1111_PHY_EXT_CR 0x14
72 #define MII_M1111_RX_DELAY 0x80
73 #define MII_M1111_TX_DELAY 0x2
74 #define MII_M1111_PHY_EXT_SR 0x1b
75
76 #define MII_M1111_HWCFG_MODE_MASK 0xf
77 #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
78 #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
79 #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
80 #define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
81 #define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
82 #define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
83
84 #define MII_M1111_COPPER 0
85 #define MII_M1111_FIBER 1
86
87 #define MII_88E1121_PHY_MSCR_PAGE 2
88 #define MII_88E1121_PHY_MSCR_REG 21
89 #define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
90 #define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
91 #define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
92
93 #define MII_88E1318S_PHY_MSCR1_REG 16
94 #define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
95
96 /* Copper Specific Interrupt Enable Register */
97 #define MII_88E1318S_PHY_CSIER 0x12
98 /* WOL Event Interrupt Enable */
99 #define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
100
101 /* LED Timer Control Register */
102 #define MII_88E1318S_PHY_LED_PAGE 0x03
103 #define MII_88E1318S_PHY_LED_TCR 0x12
104 #define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
105 #define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
106 #define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
107
108 /* Magic Packet MAC address registers */
109 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
110 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
111 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
112
113 #define MII_88E1318S_PHY_WOL_PAGE 0x11
114 #define MII_88E1318S_PHY_WOL_CTRL 0x10
115 #define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
116 #define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
117
118 #define MII_88E1121_PHY_LED_CTRL 16
119 #define MII_88E1121_PHY_LED_PAGE 3
120 #define MII_88E1121_PHY_LED_DEF 0x0030
121
122 #define MII_M1011_PHY_STATUS 0x11
123 #define MII_M1011_PHY_STATUS_1000 0x8000
124 #define MII_M1011_PHY_STATUS_100 0x4000
125 #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
126 #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
127 #define MII_M1011_PHY_STATUS_RESOLVED 0x0800
128 #define MII_M1011_PHY_STATUS_LINK 0x0400
129
130 #define MII_M1116R_CONTROL_REG_MAC 21
131
132 #define MII_88E3016_PHY_SPEC_CTRL 0x10
133 #define MII_88E3016_DISABLE_SCRAMBLER 0x0200
134 #define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
135
136 #define MII_88E1510_GEN_CTRL_REG_1 0x14
137 #define MII_88E1510_GEN_CTRL_REG_1_MODE_MASK 0x7
138 #define MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII 0x1 /* SGMII to copper */
139 #define MII_88E1510_GEN_CTRL_REG_1_RESET 0x8000 /* Soft reset */
140
141 #define LPA_FIBER_1000HALF 0x40
142 #define LPA_FIBER_1000FULL 0x20
143
144 #define LPA_PAUSE_FIBER 0x180
145 #define LPA_PAUSE_ASYM_FIBER 0x100
146
147 #define ADVERTISE_FIBER_1000HALF 0x40
148 #define ADVERTISE_FIBER_1000FULL 0x20
149
150 #define ADVERTISE_PAUSE_FIBER 0x180
151 #define ADVERTISE_PAUSE_ASYM_FIBER 0x100
152
153 #define REGISTER_LINK_STATUS 0x400
154 #define NB_FIBER_STATS 1
155
156 MODULE_DESCRIPTION("Marvell PHY driver");
157 MODULE_AUTHOR("Andy Fleming");
158 MODULE_LICENSE("GPL");
159
160 struct marvell_hw_stat {
161 const char *string;
162 u8 page;
163 u8 reg;
164 u8 bits;
165 };
166
167 static struct marvell_hw_stat marvell_hw_stats[] = {
168 { "phy_receive_errors_copper", 0, 21, 16},
169 { "phy_idle_errors", 0, 10, 8 },
170 { "phy_receive_errors_fiber", 1, 21, 16},
171 };
172
173 struct marvell_priv {
174 u64 stats[ARRAY_SIZE(marvell_hw_stats)];
175 };
176
177 static int marvell_ack_interrupt(struct phy_device *phydev)
178 {
179 int err;
180
181 /* Clear the interrupts by reading the reg */
182 err = phy_read(phydev, MII_M1011_IEVENT);
183
184 if (err < 0)
185 return err;
186
187 return 0;
188 }
189
190 static int marvell_config_intr(struct phy_device *phydev)
191 {
192 int err;
193
194 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
195 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
196 else
197 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
198
199 return err;
200 }
201
202 static int marvell_set_polarity(struct phy_device *phydev, int polarity)
203 {
204 int reg;
205 int err;
206 int val;
207
208 /* get the current settings */
209 reg = phy_read(phydev, MII_M1011_PHY_SCR);
210 if (reg < 0)
211 return reg;
212
213 val = reg;
214 val &= ~MII_M1011_PHY_SCR_AUTO_CROSS;
215 switch (polarity) {
216 case ETH_TP_MDI:
217 val |= MII_M1011_PHY_SCR_MDI;
218 break;
219 case ETH_TP_MDI_X:
220 val |= MII_M1011_PHY_SCR_MDI_X;
221 break;
222 case ETH_TP_MDI_AUTO:
223 case ETH_TP_MDI_INVALID:
224 default:
225 val |= MII_M1011_PHY_SCR_AUTO_CROSS;
226 break;
227 }
228
229 if (val != reg) {
230 /* Set the new polarity value in the register */
231 err = phy_write(phydev, MII_M1011_PHY_SCR, val);
232 if (err)
233 return err;
234 }
235
236 return 0;
237 }
238
239 static int marvell_config_aneg(struct phy_device *phydev)
240 {
241 int err;
242
243 err = marvell_set_polarity(phydev, phydev->mdix);
244 if (err < 0)
245 return err;
246
247 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
248 MII_M1111_PHY_LED_DIRECT);
249 if (err < 0)
250 return err;
251
252 err = genphy_config_aneg(phydev);
253 if (err < 0)
254 return err;
255
256 if (phydev->autoneg != AUTONEG_ENABLE) {
257 int bmcr;
258
259 /*
260 * A write to speed/duplex bits (that is performed by
261 * genphy_config_aneg() call above) must be followed by
262 * a software reset. Otherwise, the write has no effect.
263 */
264 bmcr = phy_read(phydev, MII_BMCR);
265 if (bmcr < 0)
266 return bmcr;
267
268 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
269 if (err < 0)
270 return err;
271 }
272
273 return 0;
274 }
275
276 static int m88e1101_config_aneg(struct phy_device *phydev)
277 {
278 int err;
279
280 /* This Marvell PHY has an errata which requires
281 * that certain registers get written in order
282 * to restart autonegotiation
283 */
284 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
285
286 if (err < 0)
287 return err;
288
289 err = phy_write(phydev, 0x1d, 0x1f);
290 if (err < 0)
291 return err;
292
293 err = phy_write(phydev, 0x1e, 0x200c);
294 if (err < 0)
295 return err;
296
297 err = phy_write(phydev, 0x1d, 0x5);
298 if (err < 0)
299 return err;
300
301 err = phy_write(phydev, 0x1e, 0);
302 if (err < 0)
303 return err;
304
305 err = phy_write(phydev, 0x1e, 0x100);
306 if (err < 0)
307 return err;
308
309 return marvell_config_aneg(phydev);
310 }
311
312 static int m88e1111_config_aneg(struct phy_device *phydev)
313 {
314 int err;
315
316 /* The Marvell PHY has an errata which requires
317 * that certain registers get written in order
318 * to restart autonegotiation
319 */
320 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
321
322 err = marvell_set_polarity(phydev, phydev->mdix);
323 if (err < 0)
324 return err;
325
326 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
327 MII_M1111_PHY_LED_DIRECT);
328 if (err < 0)
329 return err;
330
331 err = genphy_config_aneg(phydev);
332 if (err < 0)
333 return err;
334
335 if (phydev->autoneg != AUTONEG_ENABLE) {
336 int bmcr;
337
338 /* A write to speed/duplex bits (that is performed by
339 * genphy_config_aneg() call above) must be followed by
340 * a software reset. Otherwise, the write has no effect.
341 */
342 bmcr = phy_read(phydev, MII_BMCR);
343 if (bmcr < 0)
344 return bmcr;
345
346 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
347 if (err < 0)
348 return err;
349 }
350
351 return 0;
352 }
353
354 #ifdef CONFIG_OF_MDIO
355 /*
356 * Set and/or override some configuration registers based on the
357 * marvell,reg-init property stored in the of_node for the phydev.
358 *
359 * marvell,reg-init = <reg-page reg mask value>,...;
360 *
361 * There may be one or more sets of <reg-page reg mask value>:
362 *
363 * reg-page: which register bank to use.
364 * reg: the register.
365 * mask: if non-zero, ANDed with existing register value.
366 * value: ORed with the masked value and written to the regiser.
367 *
368 */
369 static int marvell_of_reg_init(struct phy_device *phydev)
370 {
371 const __be32 *paddr;
372 int len, i, saved_page, current_page, page_changed, ret;
373
374 if (!phydev->mdio.dev.of_node)
375 return 0;
376
377 paddr = of_get_property(phydev->mdio.dev.of_node,
378 "marvell,reg-init", &len);
379 if (!paddr || len < (4 * sizeof(*paddr)))
380 return 0;
381
382 saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE);
383 if (saved_page < 0)
384 return saved_page;
385 page_changed = 0;
386 current_page = saved_page;
387
388 ret = 0;
389 len /= sizeof(*paddr);
390 for (i = 0; i < len - 3; i += 4) {
391 u16 reg_page = be32_to_cpup(paddr + i);
392 u16 reg = be32_to_cpup(paddr + i + 1);
393 u16 mask = be32_to_cpup(paddr + i + 2);
394 u16 val_bits = be32_to_cpup(paddr + i + 3);
395 int val;
396
397 if (reg_page != current_page) {
398 current_page = reg_page;
399 page_changed = 1;
400 ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page);
401 if (ret < 0)
402 goto err;
403 }
404
405 val = 0;
406 if (mask) {
407 val = phy_read(phydev, reg);
408 if (val < 0) {
409 ret = val;
410 goto err;
411 }
412 val &= mask;
413 }
414 val |= val_bits;
415
416 ret = phy_write(phydev, reg, val);
417 if (ret < 0)
418 goto err;
419
420 }
421 err:
422 if (page_changed) {
423 i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page);
424 if (ret == 0)
425 ret = i;
426 }
427 return ret;
428 }
429 #else
430 static int marvell_of_reg_init(struct phy_device *phydev)
431 {
432 return 0;
433 }
434 #endif /* CONFIG_OF_MDIO */
435
436 static int m88e1121_config_aneg(struct phy_device *phydev)
437 {
438 int err, oldpage, mscr;
439
440 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
441
442 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
443 MII_88E1121_PHY_MSCR_PAGE);
444 if (err < 0)
445 return err;
446
447 if (phy_interface_is_rgmii(phydev)) {
448
449 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
450 MII_88E1121_PHY_MSCR_DELAY_MASK;
451
452 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
453 mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
454 MII_88E1121_PHY_MSCR_TX_DELAY);
455 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
456 mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
457 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
458 mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
459
460 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
461 if (err < 0)
462 return err;
463 }
464
465 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
466
467 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
468 if (err < 0)
469 return err;
470
471 err = phy_write(phydev, MII_M1011_PHY_SCR,
472 MII_M1011_PHY_SCR_AUTO_CROSS);
473 if (err < 0)
474 return err;
475
476 return genphy_config_aneg(phydev);
477 }
478
479 static int m88e1318_config_aneg(struct phy_device *phydev)
480 {
481 int err, oldpage, mscr;
482
483 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
484
485 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
486 MII_88E1121_PHY_MSCR_PAGE);
487 if (err < 0)
488 return err;
489
490 mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
491 mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
492
493 err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr);
494 if (err < 0)
495 return err;
496
497 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
498 if (err < 0)
499 return err;
500
501 return m88e1121_config_aneg(phydev);
502 }
503
504 /**
505 * ethtool_adv_to_fiber_adv_t
506 * @ethadv: the ethtool advertisement settings
507 *
508 * A small helper function that translates ethtool advertisement
509 * settings to phy autonegotiation advertisements for the
510 * MII_ADV register for fiber link.
511 */
512 static inline u32 ethtool_adv_to_fiber_adv_t(u32 ethadv)
513 {
514 u32 result = 0;
515
516 if (ethadv & ADVERTISED_1000baseT_Half)
517 result |= ADVERTISE_FIBER_1000HALF;
518 if (ethadv & ADVERTISED_1000baseT_Full)
519 result |= ADVERTISE_FIBER_1000FULL;
520
521 if ((ethadv & ADVERTISE_PAUSE_ASYM) && (ethadv & ADVERTISE_PAUSE_CAP))
522 result |= LPA_PAUSE_ASYM_FIBER;
523 else if (ethadv & ADVERTISE_PAUSE_CAP)
524 result |= (ADVERTISE_PAUSE_FIBER
525 & (~ADVERTISE_PAUSE_ASYM_FIBER));
526
527 return result;
528 }
529
530 /**
531 * marvell_config_aneg_fiber - restart auto-negotiation or write BMCR
532 * @phydev: target phy_device struct
533 *
534 * Description: If auto-negotiation is enabled, we configure the
535 * advertising, and then restart auto-negotiation. If it is not
536 * enabled, then we write the BMCR. Adapted for fiber link in
537 * some Marvell's devices.
538 */
539 static int marvell_config_aneg_fiber(struct phy_device *phydev)
540 {
541 int changed = 0;
542 int err;
543 int adv, oldadv;
544 u32 advertise;
545
546 if (phydev->autoneg != AUTONEG_ENABLE)
547 return genphy_setup_forced(phydev);
548
549 /* Only allow advertising what this PHY supports */
550 phydev->advertising &= phydev->supported;
551 advertise = phydev->advertising;
552
553 /* Setup fiber advertisement */
554 adv = phy_read(phydev, MII_ADVERTISE);
555 if (adv < 0)
556 return adv;
557
558 oldadv = adv;
559 adv &= ~(ADVERTISE_FIBER_1000HALF | ADVERTISE_FIBER_1000FULL
560 | LPA_PAUSE_FIBER);
561 adv |= ethtool_adv_to_fiber_adv_t(advertise);
562
563 if (adv != oldadv) {
564 err = phy_write(phydev, MII_ADVERTISE, adv);
565 if (err < 0)
566 return err;
567
568 changed = 1;
569 }
570
571 if (changed == 0) {
572 /* Advertisement hasn't changed, but maybe aneg was never on to
573 * begin with? Or maybe phy was isolated?
574 */
575 int ctl = phy_read(phydev, MII_BMCR);
576
577 if (ctl < 0)
578 return ctl;
579
580 if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE))
581 changed = 1; /* do restart aneg */
582 }
583
584 /* Only restart aneg if we are advertising something different
585 * than we were before.
586 */
587 if (changed > 0)
588 changed = genphy_restart_aneg(phydev);
589
590 return changed;
591 }
592
593 static int m88e1510_config_aneg(struct phy_device *phydev)
594 {
595 int err;
596
597 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
598 if (err < 0)
599 goto error;
600
601 /* Configure the copper link first */
602 err = m88e1318_config_aneg(phydev);
603 if (err < 0)
604 goto error;
605
606 /* Then the fiber link */
607 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER);
608 if (err < 0)
609 goto error;
610
611 err = marvell_config_aneg_fiber(phydev);
612 if (err < 0)
613 goto error;
614
615 return phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
616
617 error:
618 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
619 return err;
620 }
621
622 static int marvell_config_init(struct phy_device *phydev)
623 {
624 /* Set registers from marvell,reg-init DT property */
625 return marvell_of_reg_init(phydev);
626 }
627
628 static int m88e1116r_config_init(struct phy_device *phydev)
629 {
630 int temp;
631 int err;
632
633 temp = phy_read(phydev, MII_BMCR);
634 temp |= BMCR_RESET;
635 err = phy_write(phydev, MII_BMCR, temp);
636 if (err < 0)
637 return err;
638
639 mdelay(500);
640
641 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
642 if (err < 0)
643 return err;
644
645 temp = phy_read(phydev, MII_M1011_PHY_SCR);
646 temp |= (7 << 12); /* max number of gigabit attempts */
647 temp |= (1 << 11); /* enable downshift */
648 temp |= MII_M1011_PHY_SCR_AUTO_CROSS;
649 err = phy_write(phydev, MII_M1011_PHY_SCR, temp);
650 if (err < 0)
651 return err;
652
653 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 2);
654 if (err < 0)
655 return err;
656 temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC);
657 temp |= (1 << 5);
658 temp |= (1 << 4);
659 err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp);
660 if (err < 0)
661 return err;
662 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
663 if (err < 0)
664 return err;
665
666 temp = phy_read(phydev, MII_BMCR);
667 temp |= BMCR_RESET;
668 err = phy_write(phydev, MII_BMCR, temp);
669 if (err < 0)
670 return err;
671
672 mdelay(500);
673
674 return marvell_config_init(phydev);
675 }
676
677 static int m88e3016_config_init(struct phy_device *phydev)
678 {
679 int reg;
680
681 /* Enable Scrambler and Auto-Crossover */
682 reg = phy_read(phydev, MII_88E3016_PHY_SPEC_CTRL);
683 if (reg < 0)
684 return reg;
685
686 reg &= ~MII_88E3016_DISABLE_SCRAMBLER;
687 reg |= MII_88E3016_AUTO_MDIX_CROSSOVER;
688
689 reg = phy_write(phydev, MII_88E3016_PHY_SPEC_CTRL, reg);
690 if (reg < 0)
691 return reg;
692
693 return marvell_config_init(phydev);
694 }
695
696 static int m88e1111_config_init(struct phy_device *phydev)
697 {
698 int err;
699 int temp;
700
701 if (phy_interface_is_rgmii(phydev)) {
702
703 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
704 if (temp < 0)
705 return temp;
706
707 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
708 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
709 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
710 temp &= ~MII_M1111_TX_DELAY;
711 temp |= MII_M1111_RX_DELAY;
712 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
713 temp &= ~MII_M1111_RX_DELAY;
714 temp |= MII_M1111_TX_DELAY;
715 }
716
717 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
718 if (err < 0)
719 return err;
720
721 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
722 if (temp < 0)
723 return temp;
724
725 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
726
727 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
728 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
729 else
730 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
731
732 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
733 if (err < 0)
734 return err;
735 }
736
737 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
738 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
739 if (temp < 0)
740 return temp;
741
742 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
743 temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
744 temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
745
746 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
747 if (err < 0)
748 return err;
749
750 /* make sure copper is selected */
751 err = phy_read(phydev, MII_M1145_PHY_EXT_ADDR_PAGE);
752 if (err < 0)
753 return err;
754
755 err = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE,
756 err & (~0xff));
757 if (err < 0)
758 return err;
759 }
760
761 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
762 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
763 if (temp < 0)
764 return temp;
765 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
766 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
767 if (err < 0)
768 return err;
769
770 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
771 if (temp < 0)
772 return temp;
773 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
774 temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
775 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
776 if (err < 0)
777 return err;
778
779 /* soft reset */
780 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
781 if (err < 0)
782 return err;
783 do
784 temp = phy_read(phydev, MII_BMCR);
785 while (temp & BMCR_RESET);
786
787 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
788 if (temp < 0)
789 return temp;
790 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
791 temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
792 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
793 if (err < 0)
794 return err;
795 }
796
797 err = marvell_of_reg_init(phydev);
798 if (err < 0)
799 return err;
800
801 return phy_write(phydev, MII_BMCR, BMCR_RESET);
802 }
803
804 static int m88e1121_config_init(struct phy_device *phydev)
805 {
806 int err, oldpage;
807
808 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
809
810 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
811 if (err < 0)
812 return err;
813
814 /* Default PHY LED config: LED[0] .. Link, LED[1] .. Activity */
815 err = phy_write(phydev, MII_88E1121_PHY_LED_CTRL,
816 MII_88E1121_PHY_LED_DEF);
817 if (err < 0)
818 return err;
819
820 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
821
822 /* Set marvell,reg-init configuration from device tree */
823 return marvell_config_init(phydev);
824 }
825
826 static int m88e1510_config_init(struct phy_device *phydev)
827 {
828 int err;
829 int temp;
830
831 /* SGMII-to-Copper mode initialization */
832 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
833 /* Select page 18 */
834 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 18);
835 if (err < 0)
836 return err;
837
838 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
839 temp = phy_read(phydev, MII_88E1510_GEN_CTRL_REG_1);
840 temp &= ~MII_88E1510_GEN_CTRL_REG_1_MODE_MASK;
841 temp |= MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII;
842 err = phy_write(phydev, MII_88E1510_GEN_CTRL_REG_1, temp);
843 if (err < 0)
844 return err;
845
846 /* PHY reset is necessary after changing MODE[2:0] */
847 temp |= MII_88E1510_GEN_CTRL_REG_1_RESET;
848 err = phy_write(phydev, MII_88E1510_GEN_CTRL_REG_1, temp);
849 if (err < 0)
850 return err;
851
852 /* Reset page selection */
853 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
854 if (err < 0)
855 return err;
856 }
857
858 return m88e1121_config_init(phydev);
859 }
860
861 static int m88e1118_config_aneg(struct phy_device *phydev)
862 {
863 int err;
864
865 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
866 if (err < 0)
867 return err;
868
869 err = phy_write(phydev, MII_M1011_PHY_SCR,
870 MII_M1011_PHY_SCR_AUTO_CROSS);
871 if (err < 0)
872 return err;
873
874 err = genphy_config_aneg(phydev);
875 return 0;
876 }
877
878 static int m88e1118_config_init(struct phy_device *phydev)
879 {
880 int err;
881
882 /* Change address */
883 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
884 if (err < 0)
885 return err;
886
887 /* Enable 1000 Mbit */
888 err = phy_write(phydev, 0x15, 0x1070);
889 if (err < 0)
890 return err;
891
892 /* Change address */
893 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003);
894 if (err < 0)
895 return err;
896
897 /* Adjust LED Control */
898 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
899 err = phy_write(phydev, 0x10, 0x1100);
900 else
901 err = phy_write(phydev, 0x10, 0x021e);
902 if (err < 0)
903 return err;
904
905 err = marvell_of_reg_init(phydev);
906 if (err < 0)
907 return err;
908
909 /* Reset address */
910 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
911 if (err < 0)
912 return err;
913
914 return phy_write(phydev, MII_BMCR, BMCR_RESET);
915 }
916
917 static int m88e1149_config_init(struct phy_device *phydev)
918 {
919 int err;
920
921 /* Change address */
922 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
923 if (err < 0)
924 return err;
925
926 /* Enable 1000 Mbit */
927 err = phy_write(phydev, 0x15, 0x1048);
928 if (err < 0)
929 return err;
930
931 err = marvell_of_reg_init(phydev);
932 if (err < 0)
933 return err;
934
935 /* Reset address */
936 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
937 if (err < 0)
938 return err;
939
940 return phy_write(phydev, MII_BMCR, BMCR_RESET);
941 }
942
943 static int m88e1145_config_init(struct phy_device *phydev)
944 {
945 int err;
946 int temp;
947
948 /* Take care of errata E0 & E1 */
949 err = phy_write(phydev, 0x1d, 0x001b);
950 if (err < 0)
951 return err;
952
953 err = phy_write(phydev, 0x1e, 0x418f);
954 if (err < 0)
955 return err;
956
957 err = phy_write(phydev, 0x1d, 0x0016);
958 if (err < 0)
959 return err;
960
961 err = phy_write(phydev, 0x1e, 0xa2da);
962 if (err < 0)
963 return err;
964
965 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
966 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
967 if (temp < 0)
968 return temp;
969
970 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
971
972 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
973 if (err < 0)
974 return err;
975
976 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
977 err = phy_write(phydev, 0x1d, 0x0012);
978 if (err < 0)
979 return err;
980
981 temp = phy_read(phydev, 0x1e);
982 if (temp < 0)
983 return temp;
984
985 temp &= 0xf03f;
986 temp |= 2 << 9; /* 36 ohm */
987 temp |= 2 << 6; /* 39 ohm */
988
989 err = phy_write(phydev, 0x1e, temp);
990 if (err < 0)
991 return err;
992
993 err = phy_write(phydev, 0x1d, 0x3);
994 if (err < 0)
995 return err;
996
997 err = phy_write(phydev, 0x1e, 0x8000);
998 if (err < 0)
999 return err;
1000 }
1001 }
1002
1003 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1004 temp = phy_read(phydev, MII_M1145_PHY_EXT_SR);
1005 if (temp < 0)
1006 return temp;
1007
1008 temp &= ~MII_M1145_HWCFG_MODE_MASK;
1009 temp |= MII_M1145_HWCFG_MODE_SGMII_NO_CLK;
1010 temp |= MII_M1145_HWCFG_FIBER_COPPER_AUTO;
1011
1012 err = phy_write(phydev, MII_M1145_PHY_EXT_SR, temp);
1013 if (err < 0)
1014 return err;
1015 }
1016
1017 err = marvell_of_reg_init(phydev);
1018 if (err < 0)
1019 return err;
1020
1021 return 0;
1022 }
1023
1024 /**
1025 * fiber_lpa_to_ethtool_lpa_t
1026 * @lpa: value of the MII_LPA register for fiber link
1027 *
1028 * A small helper function that translates MII_LPA
1029 * bits to ethtool LP advertisement settings.
1030 */
1031 static u32 fiber_lpa_to_ethtool_lpa_t(u32 lpa)
1032 {
1033 u32 result = 0;
1034
1035 if (lpa & LPA_FIBER_1000HALF)
1036 result |= ADVERTISED_1000baseT_Half;
1037 if (lpa & LPA_FIBER_1000FULL)
1038 result |= ADVERTISED_1000baseT_Full;
1039
1040 return result;
1041 }
1042
1043 /**
1044 * marvell_update_link - update link status in real time in @phydev
1045 * @phydev: target phy_device struct
1046 *
1047 * Description: Update the value in phydev->link to reflect the
1048 * current link value.
1049 */
1050 static int marvell_update_link(struct phy_device *phydev, int fiber)
1051 {
1052 int status;
1053
1054 /* Use the generic register for copper link, or specific
1055 * register for fiber case */
1056 if (fiber) {
1057 status = phy_read(phydev, MII_M1011_PHY_STATUS);
1058 if (status < 0)
1059 return status;
1060
1061 if ((status & REGISTER_LINK_STATUS) == 0)
1062 phydev->link = 0;
1063 else
1064 phydev->link = 1;
1065 } else {
1066 return genphy_update_link(phydev);
1067 }
1068
1069 return 0;
1070 }
1071
1072 /* marvell_read_status_page
1073 *
1074 * Description:
1075 * Check the link, then figure out the current state
1076 * by comparing what we advertise with what the link partner
1077 * advertises. Start by checking the gigabit possibilities,
1078 * then move on to 10/100.
1079 */
1080 static int marvell_read_status_page(struct phy_device *phydev, int page)
1081 {
1082 int adv;
1083 int err;
1084 int lpa;
1085 int lpagb;
1086 int status = 0;
1087 int fiber;
1088
1089 /* Detect and update the link, but return if there
1090 * was an error */
1091 if (page == MII_M1111_FIBER)
1092 fiber = 1;
1093 else
1094 fiber = 0;
1095
1096 err = marvell_update_link(phydev, fiber);
1097 if (err)
1098 return err;
1099
1100 if (AUTONEG_ENABLE == phydev->autoneg) {
1101 status = phy_read(phydev, MII_M1011_PHY_STATUS);
1102 if (status < 0)
1103 return status;
1104
1105 lpa = phy_read(phydev, MII_LPA);
1106 if (lpa < 0)
1107 return lpa;
1108
1109 lpagb = phy_read(phydev, MII_STAT1000);
1110 if (lpagb < 0)
1111 return lpagb;
1112
1113 adv = phy_read(phydev, MII_ADVERTISE);
1114 if (adv < 0)
1115 return adv;
1116
1117 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
1118 phydev->duplex = DUPLEX_FULL;
1119 else
1120 phydev->duplex = DUPLEX_HALF;
1121
1122 status = status & MII_M1011_PHY_STATUS_SPD_MASK;
1123 phydev->pause = phydev->asym_pause = 0;
1124
1125 switch (status) {
1126 case MII_M1011_PHY_STATUS_1000:
1127 phydev->speed = SPEED_1000;
1128 break;
1129
1130 case MII_M1011_PHY_STATUS_100:
1131 phydev->speed = SPEED_100;
1132 break;
1133
1134 default:
1135 phydev->speed = SPEED_10;
1136 break;
1137 }
1138
1139 if (!fiber) {
1140 phydev->lp_advertising = mii_stat1000_to_ethtool_lpa_t(lpagb) |
1141 mii_lpa_to_ethtool_lpa_t(lpa);
1142
1143 if (phydev->duplex == DUPLEX_FULL) {
1144 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
1145 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
1146 }
1147 } else {
1148 /* The fiber link is only 1000M capable */
1149 phydev->lp_advertising = fiber_lpa_to_ethtool_lpa_t(lpa);
1150
1151 if (phydev->duplex == DUPLEX_FULL) {
1152 if (!(lpa & LPA_PAUSE_FIBER)) {
1153 phydev->pause = 0;
1154 phydev->asym_pause = 0;
1155 } else if ((lpa & LPA_PAUSE_ASYM_FIBER)) {
1156 phydev->pause = 1;
1157 phydev->asym_pause = 1;
1158 } else {
1159 phydev->pause = 1;
1160 phydev->asym_pause = 0;
1161 }
1162 }
1163 }
1164 } else {
1165 int bmcr = phy_read(phydev, MII_BMCR);
1166
1167 if (bmcr < 0)
1168 return bmcr;
1169
1170 if (bmcr & BMCR_FULLDPLX)
1171 phydev->duplex = DUPLEX_FULL;
1172 else
1173 phydev->duplex = DUPLEX_HALF;
1174
1175 if (bmcr & BMCR_SPEED1000)
1176 phydev->speed = SPEED_1000;
1177 else if (bmcr & BMCR_SPEED100)
1178 phydev->speed = SPEED_100;
1179 else
1180 phydev->speed = SPEED_10;
1181
1182 phydev->pause = phydev->asym_pause = 0;
1183 phydev->lp_advertising = 0;
1184 }
1185
1186 return 0;
1187 }
1188
1189 /* marvell_read_status
1190 *
1191 * Some Marvell's phys have two modes: fiber and copper.
1192 * Both need status checked.
1193 * Description:
1194 * First, check the fiber link and status.
1195 * If the fiber link is down, check the copper link and status which
1196 * will be the default value if both link are down.
1197 */
1198 static int marvell_read_status(struct phy_device *phydev)
1199 {
1200 int err;
1201
1202 /* Check the fiber mode first */
1203 if (phydev->supported & SUPPORTED_FIBRE &&
1204 phydev->interface != PHY_INTERFACE_MODE_SGMII) {
1205 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER);
1206 if (err < 0)
1207 goto error;
1208
1209 err = marvell_read_status_page(phydev, MII_M1111_FIBER);
1210 if (err < 0)
1211 goto error;
1212
1213 /* If the fiber link is up, it is the selected and used link.
1214 * In this case, we need to stay in the fiber page.
1215 * Please to be careful about that, avoid to restore Copper page
1216 * in other functions which could break the behaviour
1217 * for some fiber phy like 88E1512.
1218 * */
1219 if (phydev->link)
1220 return 0;
1221
1222 /* If fiber link is down, check and save copper mode state */
1223 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1224 if (err < 0)
1225 goto error;
1226 }
1227
1228 return marvell_read_status_page(phydev, MII_M1111_COPPER);
1229
1230 error:
1231 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1232 return err;
1233 }
1234
1235 /* marvell_suspend
1236 *
1237 * Some Marvell's phys have two modes: fiber and copper.
1238 * Both need to be suspended
1239 */
1240 static int marvell_suspend(struct phy_device *phydev)
1241 {
1242 int err;
1243
1244 /* Suspend the fiber mode first */
1245 if (!(phydev->supported & SUPPORTED_FIBRE)) {
1246 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER);
1247 if (err < 0)
1248 goto error;
1249
1250 /* With the page set, use the generic suspend */
1251 err = genphy_suspend(phydev);
1252 if (err < 0)
1253 goto error;
1254
1255 /* Then, the copper link */
1256 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1257 if (err < 0)
1258 goto error;
1259 }
1260
1261 /* With the page set, use the generic suspend */
1262 return genphy_suspend(phydev);
1263
1264 error:
1265 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1266 return err;
1267 }
1268
1269 /* marvell_resume
1270 *
1271 * Some Marvell's phys have two modes: fiber and copper.
1272 * Both need to be resumed
1273 */
1274 static int marvell_resume(struct phy_device *phydev)
1275 {
1276 int err;
1277
1278 /* Resume the fiber mode first */
1279 if (!(phydev->supported & SUPPORTED_FIBRE)) {
1280 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER);
1281 if (err < 0)
1282 goto error;
1283
1284 /* With the page set, use the generic resume */
1285 err = genphy_resume(phydev);
1286 if (err < 0)
1287 goto error;
1288
1289 /* Then, the copper link */
1290 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1291 if (err < 0)
1292 goto error;
1293 }
1294
1295 /* With the page set, use the generic resume */
1296 return genphy_resume(phydev);
1297
1298 error:
1299 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1300 return err;
1301 }
1302
1303 static int marvell_aneg_done(struct phy_device *phydev)
1304 {
1305 int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
1306 return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
1307 }
1308
1309 static int m88e1121_did_interrupt(struct phy_device *phydev)
1310 {
1311 int imask;
1312
1313 imask = phy_read(phydev, MII_M1011_IEVENT);
1314
1315 if (imask & MII_M1011_IMASK_INIT)
1316 return 1;
1317
1318 return 0;
1319 }
1320
1321 static void m88e1318_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
1322 {
1323 wol->supported = WAKE_MAGIC;
1324 wol->wolopts = 0;
1325
1326 if (phy_write(phydev, MII_MARVELL_PHY_PAGE,
1327 MII_88E1318S_PHY_WOL_PAGE) < 0)
1328 return;
1329
1330 if (phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL) &
1331 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
1332 wol->wolopts |= WAKE_MAGIC;
1333
1334 if (phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00) < 0)
1335 return;
1336 }
1337
1338 static int m88e1318_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
1339 {
1340 int err, oldpage, temp;
1341
1342 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
1343
1344 if (wol->wolopts & WAKE_MAGIC) {
1345 /* Explicitly switch to page 0x00, just to be sure */
1346 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00);
1347 if (err < 0)
1348 return err;
1349
1350 /* Enable the WOL interrupt */
1351 temp = phy_read(phydev, MII_88E1318S_PHY_CSIER);
1352 temp |= MII_88E1318S_PHY_CSIER_WOL_EIE;
1353 err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp);
1354 if (err < 0)
1355 return err;
1356
1357 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1358 MII_88E1318S_PHY_LED_PAGE);
1359 if (err < 0)
1360 return err;
1361
1362 /* Setup LED[2] as interrupt pin (active low) */
1363 temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR);
1364 temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT;
1365 temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE;
1366 temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW;
1367 err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp);
1368 if (err < 0)
1369 return err;
1370
1371 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1372 MII_88E1318S_PHY_WOL_PAGE);
1373 if (err < 0)
1374 return err;
1375
1376 /* Store the device address for the magic packet */
1377 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
1378 ((phydev->attached_dev->dev_addr[5] << 8) |
1379 phydev->attached_dev->dev_addr[4]));
1380 if (err < 0)
1381 return err;
1382 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
1383 ((phydev->attached_dev->dev_addr[3] << 8) |
1384 phydev->attached_dev->dev_addr[2]));
1385 if (err < 0)
1386 return err;
1387 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
1388 ((phydev->attached_dev->dev_addr[1] << 8) |
1389 phydev->attached_dev->dev_addr[0]));
1390 if (err < 0)
1391 return err;
1392
1393 /* Clear WOL status and enable magic packet matching */
1394 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
1395 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
1396 temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
1397 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
1398 if (err < 0)
1399 return err;
1400 } else {
1401 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1402 MII_88E1318S_PHY_WOL_PAGE);
1403 if (err < 0)
1404 return err;
1405
1406 /* Clear WOL status and disable magic packet matching */
1407 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
1408 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
1409 temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
1410 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
1411 if (err < 0)
1412 return err;
1413 }
1414
1415 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
1416 if (err < 0)
1417 return err;
1418
1419 return 0;
1420 }
1421
1422 static int marvell_get_sset_count(struct phy_device *phydev)
1423 {
1424 if (phydev->supported & SUPPORTED_FIBRE)
1425 return ARRAY_SIZE(marvell_hw_stats);
1426 else
1427 return ARRAY_SIZE(marvell_hw_stats) - NB_FIBER_STATS;
1428 }
1429
1430 static void marvell_get_strings(struct phy_device *phydev, u8 *data)
1431 {
1432 int i;
1433
1434 for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++) {
1435 memcpy(data + i * ETH_GSTRING_LEN,
1436 marvell_hw_stats[i].string, ETH_GSTRING_LEN);
1437 }
1438 }
1439
1440 #ifndef UINT64_MAX
1441 #define UINT64_MAX (u64)(~((u64)0))
1442 #endif
1443 static u64 marvell_get_stat(struct phy_device *phydev, int i)
1444 {
1445 struct marvell_hw_stat stat = marvell_hw_stats[i];
1446 struct marvell_priv *priv = phydev->priv;
1447 int err, oldpage, val;
1448 u64 ret;
1449
1450 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
1451 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1452 stat.page);
1453 if (err < 0)
1454 return UINT64_MAX;
1455
1456 val = phy_read(phydev, stat.reg);
1457 if (val < 0) {
1458 ret = UINT64_MAX;
1459 } else {
1460 val = val & ((1 << stat.bits) - 1);
1461 priv->stats[i] += val;
1462 ret = priv->stats[i];
1463 }
1464
1465 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
1466
1467 return ret;
1468 }
1469
1470 static void marvell_get_stats(struct phy_device *phydev,
1471 struct ethtool_stats *stats, u64 *data)
1472 {
1473 int i;
1474
1475 for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++)
1476 data[i] = marvell_get_stat(phydev, i);
1477 }
1478
1479 static int marvell_probe(struct phy_device *phydev)
1480 {
1481 struct marvell_priv *priv;
1482
1483 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
1484 if (!priv)
1485 return -ENOMEM;
1486
1487 phydev->priv = priv;
1488
1489 return 0;
1490 }
1491
1492 static struct phy_driver marvell_drivers[] = {
1493 {
1494 .phy_id = MARVELL_PHY_ID_88E1101,
1495 .phy_id_mask = MARVELL_PHY_ID_MASK,
1496 .name = "Marvell 88E1101",
1497 .features = PHY_GBIT_FEATURES,
1498 .probe = marvell_probe,
1499 .flags = PHY_HAS_INTERRUPT,
1500 .config_init = &marvell_config_init,
1501 .config_aneg = &m88e1101_config_aneg,
1502 .read_status = &genphy_read_status,
1503 .ack_interrupt = &marvell_ack_interrupt,
1504 .config_intr = &marvell_config_intr,
1505 .resume = &genphy_resume,
1506 .suspend = &genphy_suspend,
1507 .get_sset_count = marvell_get_sset_count,
1508 .get_strings = marvell_get_strings,
1509 .get_stats = marvell_get_stats,
1510 },
1511 {
1512 .phy_id = MARVELL_PHY_ID_88E1112,
1513 .phy_id_mask = MARVELL_PHY_ID_MASK,
1514 .name = "Marvell 88E1112",
1515 .features = PHY_GBIT_FEATURES,
1516 .flags = PHY_HAS_INTERRUPT,
1517 .probe = marvell_probe,
1518 .config_init = &m88e1111_config_init,
1519 .config_aneg = &marvell_config_aneg,
1520 .read_status = &genphy_read_status,
1521 .ack_interrupt = &marvell_ack_interrupt,
1522 .config_intr = &marvell_config_intr,
1523 .resume = &genphy_resume,
1524 .suspend = &genphy_suspend,
1525 .get_sset_count = marvell_get_sset_count,
1526 .get_strings = marvell_get_strings,
1527 .get_stats = marvell_get_stats,
1528 },
1529 {
1530 .phy_id = MARVELL_PHY_ID_88E1111,
1531 .phy_id_mask = MARVELL_PHY_ID_MASK,
1532 .name = "Marvell 88E1111",
1533 .features = PHY_GBIT_FEATURES,
1534 .flags = PHY_HAS_INTERRUPT,
1535 .probe = marvell_probe,
1536 .config_init = &m88e1111_config_init,
1537 .config_aneg = &m88e1111_config_aneg,
1538 .read_status = &marvell_read_status,
1539 .ack_interrupt = &marvell_ack_interrupt,
1540 .config_intr = &marvell_config_intr,
1541 .resume = &genphy_resume,
1542 .suspend = &genphy_suspend,
1543 .get_sset_count = marvell_get_sset_count,
1544 .get_strings = marvell_get_strings,
1545 .get_stats = marvell_get_stats,
1546 },
1547 {
1548 .phy_id = MARVELL_PHY_ID_88E1118,
1549 .phy_id_mask = MARVELL_PHY_ID_MASK,
1550 .name = "Marvell 88E1118",
1551 .features = PHY_GBIT_FEATURES,
1552 .flags = PHY_HAS_INTERRUPT,
1553 .probe = marvell_probe,
1554 .config_init = &m88e1118_config_init,
1555 .config_aneg = &m88e1118_config_aneg,
1556 .read_status = &genphy_read_status,
1557 .ack_interrupt = &marvell_ack_interrupt,
1558 .config_intr = &marvell_config_intr,
1559 .resume = &genphy_resume,
1560 .suspend = &genphy_suspend,
1561 .get_sset_count = marvell_get_sset_count,
1562 .get_strings = marvell_get_strings,
1563 .get_stats = marvell_get_stats,
1564 },
1565 {
1566 .phy_id = MARVELL_PHY_ID_88E1121R,
1567 .phy_id_mask = MARVELL_PHY_ID_MASK,
1568 .name = "Marvell 88E1121R",
1569 .features = PHY_GBIT_FEATURES,
1570 .flags = PHY_HAS_INTERRUPT,
1571 .probe = marvell_probe,
1572 .config_init = &m88e1121_config_init,
1573 .config_aneg = &m88e1121_config_aneg,
1574 .read_status = &marvell_read_status,
1575 .ack_interrupt = &marvell_ack_interrupt,
1576 .config_intr = &marvell_config_intr,
1577 .did_interrupt = &m88e1121_did_interrupt,
1578 .resume = &genphy_resume,
1579 .suspend = &genphy_suspend,
1580 .get_sset_count = marvell_get_sset_count,
1581 .get_strings = marvell_get_strings,
1582 .get_stats = marvell_get_stats,
1583 },
1584 {
1585 .phy_id = MARVELL_PHY_ID_88E1318S,
1586 .phy_id_mask = MARVELL_PHY_ID_MASK,
1587 .name = "Marvell 88E1318S",
1588 .features = PHY_GBIT_FEATURES,
1589 .flags = PHY_HAS_INTERRUPT,
1590 .probe = marvell_probe,
1591 .config_init = &m88e1121_config_init,
1592 .config_aneg = &m88e1318_config_aneg,
1593 .read_status = &marvell_read_status,
1594 .ack_interrupt = &marvell_ack_interrupt,
1595 .config_intr = &marvell_config_intr,
1596 .did_interrupt = &m88e1121_did_interrupt,
1597 .get_wol = &m88e1318_get_wol,
1598 .set_wol = &m88e1318_set_wol,
1599 .resume = &genphy_resume,
1600 .suspend = &genphy_suspend,
1601 .get_sset_count = marvell_get_sset_count,
1602 .get_strings = marvell_get_strings,
1603 .get_stats = marvell_get_stats,
1604 },
1605 {
1606 .phy_id = MARVELL_PHY_ID_88E1145,
1607 .phy_id_mask = MARVELL_PHY_ID_MASK,
1608 .name = "Marvell 88E1145",
1609 .features = PHY_GBIT_FEATURES,
1610 .flags = PHY_HAS_INTERRUPT,
1611 .probe = marvell_probe,
1612 .config_init = &m88e1145_config_init,
1613 .config_aneg = &marvell_config_aneg,
1614 .read_status = &genphy_read_status,
1615 .ack_interrupt = &marvell_ack_interrupt,
1616 .config_intr = &marvell_config_intr,
1617 .resume = &genphy_resume,
1618 .suspend = &genphy_suspend,
1619 .get_sset_count = marvell_get_sset_count,
1620 .get_strings = marvell_get_strings,
1621 .get_stats = marvell_get_stats,
1622 },
1623 {
1624 .phy_id = MARVELL_PHY_ID_88E1149R,
1625 .phy_id_mask = MARVELL_PHY_ID_MASK,
1626 .name = "Marvell 88E1149R",
1627 .features = PHY_GBIT_FEATURES,
1628 .flags = PHY_HAS_INTERRUPT,
1629 .probe = marvell_probe,
1630 .config_init = &m88e1149_config_init,
1631 .config_aneg = &m88e1118_config_aneg,
1632 .read_status = &genphy_read_status,
1633 .ack_interrupt = &marvell_ack_interrupt,
1634 .config_intr = &marvell_config_intr,
1635 .resume = &genphy_resume,
1636 .suspend = &genphy_suspend,
1637 .get_sset_count = marvell_get_sset_count,
1638 .get_strings = marvell_get_strings,
1639 .get_stats = marvell_get_stats,
1640 },
1641 {
1642 .phy_id = MARVELL_PHY_ID_88E1240,
1643 .phy_id_mask = MARVELL_PHY_ID_MASK,
1644 .name = "Marvell 88E1240",
1645 .features = PHY_GBIT_FEATURES,
1646 .flags = PHY_HAS_INTERRUPT,
1647 .probe = marvell_probe,
1648 .config_init = &m88e1111_config_init,
1649 .config_aneg = &marvell_config_aneg,
1650 .read_status = &genphy_read_status,
1651 .ack_interrupt = &marvell_ack_interrupt,
1652 .config_intr = &marvell_config_intr,
1653 .resume = &genphy_resume,
1654 .suspend = &genphy_suspend,
1655 .get_sset_count = marvell_get_sset_count,
1656 .get_strings = marvell_get_strings,
1657 .get_stats = marvell_get_stats,
1658 },
1659 {
1660 .phy_id = MARVELL_PHY_ID_88E1116R,
1661 .phy_id_mask = MARVELL_PHY_ID_MASK,
1662 .name = "Marvell 88E1116R",
1663 .features = PHY_GBIT_FEATURES,
1664 .flags = PHY_HAS_INTERRUPT,
1665 .probe = marvell_probe,
1666 .config_init = &m88e1116r_config_init,
1667 .config_aneg = &genphy_config_aneg,
1668 .read_status = &genphy_read_status,
1669 .ack_interrupt = &marvell_ack_interrupt,
1670 .config_intr = &marvell_config_intr,
1671 .resume = &genphy_resume,
1672 .suspend = &genphy_suspend,
1673 .get_sset_count = marvell_get_sset_count,
1674 .get_strings = marvell_get_strings,
1675 .get_stats = marvell_get_stats,
1676 },
1677 {
1678 .phy_id = MARVELL_PHY_ID_88E1510,
1679 .phy_id_mask = MARVELL_PHY_ID_MASK,
1680 .name = "Marvell 88E1510",
1681 .features = PHY_GBIT_FEATURES | SUPPORTED_FIBRE,
1682 .flags = PHY_HAS_INTERRUPT,
1683 .probe = marvell_probe,
1684 .config_init = &m88e1510_config_init,
1685 .config_aneg = &m88e1510_config_aneg,
1686 .read_status = &marvell_read_status,
1687 .ack_interrupt = &marvell_ack_interrupt,
1688 .config_intr = &marvell_config_intr,
1689 .did_interrupt = &m88e1121_did_interrupt,
1690 .resume = &marvell_resume,
1691 .suspend = &marvell_suspend,
1692 .get_sset_count = marvell_get_sset_count,
1693 .get_strings = marvell_get_strings,
1694 .get_stats = marvell_get_stats,
1695 },
1696 {
1697 .phy_id = MARVELL_PHY_ID_88E1540,
1698 .phy_id_mask = MARVELL_PHY_ID_MASK,
1699 .name = "Marvell 88E1540",
1700 .features = PHY_GBIT_FEATURES,
1701 .flags = PHY_HAS_INTERRUPT,
1702 .probe = marvell_probe,
1703 .config_init = &marvell_config_init,
1704 .config_aneg = &m88e1510_config_aneg,
1705 .read_status = &marvell_read_status,
1706 .ack_interrupt = &marvell_ack_interrupt,
1707 .config_intr = &marvell_config_intr,
1708 .did_interrupt = &m88e1121_did_interrupt,
1709 .resume = &genphy_resume,
1710 .suspend = &genphy_suspend,
1711 .get_sset_count = marvell_get_sset_count,
1712 .get_strings = marvell_get_strings,
1713 .get_stats = marvell_get_stats,
1714 },
1715 {
1716 .phy_id = MARVELL_PHY_ID_88E3016,
1717 .phy_id_mask = MARVELL_PHY_ID_MASK,
1718 .name = "Marvell 88E3016",
1719 .features = PHY_BASIC_FEATURES,
1720 .flags = PHY_HAS_INTERRUPT,
1721 .probe = marvell_probe,
1722 .config_aneg = &genphy_config_aneg,
1723 .config_init = &m88e3016_config_init,
1724 .aneg_done = &marvell_aneg_done,
1725 .read_status = &marvell_read_status,
1726 .ack_interrupt = &marvell_ack_interrupt,
1727 .config_intr = &marvell_config_intr,
1728 .did_interrupt = &m88e1121_did_interrupt,
1729 .resume = &genphy_resume,
1730 .suspend = &genphy_suspend,
1731 .get_sset_count = marvell_get_sset_count,
1732 .get_strings = marvell_get_strings,
1733 .get_stats = marvell_get_stats,
1734 },
1735 };
1736
1737 module_phy_driver(marvell_drivers);
1738
1739 static struct mdio_device_id __maybe_unused marvell_tbl[] = {
1740 { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
1741 { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
1742 { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
1743 { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
1744 { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
1745 { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
1746 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
1747 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
1748 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
1749 { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
1750 { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
1751 { MARVELL_PHY_ID_88E1540, MARVELL_PHY_ID_MASK },
1752 { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
1753 { }
1754 };
1755
1756 MODULE_DEVICE_TABLE(mdio, marvell_tbl);
Linux with added FPC-III support