drivers/pwm/pwm-tegra.c

   1 /*
   2  * drivers/pwm/pwm-tegra.c
   3  *
   4  * Tegra pulse-width-modulation controller driver
   5  *
   6  * Copyright (c) 2010, NVIDIA Corporation.
   7  * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along
  20  * with this program; if not, write to the Free Software Foundation, Inc.,
  21  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  22  */
  23
  24 #include <linux/clk.h>
  25 #include <linux/err.h>
  26 #include <linux/io.h>
  27 #include <linux/module.h>
  28 #include <linux/of.h>
  29 #include <linux/of_device.h>
  30 #include <linux/pwm.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/slab.h>
  33 #include <linux/reset.h>
  34
  35 #define PWM_ENABLE      (1 << 31)
  36 #define PWM_DUTY_WIDTH  8
  37 #define PWM_DUTY_SHIFT  16
  38 #define PWM_SCALE_WIDTH 13
  39 #define PWM_SCALE_SHIFT 0
  40
  41 struct tegra_pwm_soc {
  42         unsigned int num_channels;
  43 };
  44
  45 struct tegra_pwm_chip {
  46         struct pwm_chip chip;
  47         struct device *dev;
  48
  49         struct clk *clk;
  50         struct reset_control*rst;
  51
  52         void __iomem *regs;
  53
  54         const struct tegra_pwm_soc *soc;
  55 };
  56
  57 static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip)
  58 {
  59         return container_of(chip, struct tegra_pwm_chip, chip);
  60 }
  61
  62 static inline u32 pwm_readl(struct tegra_pwm_chip *chip, unsigned int num)
  63 {
  64         return readl(chip->regs + (num << 4));
  65 }
  66
  67 static inline void pwm_writel(struct tegra_pwm_chip *chip, unsigned int num,
  68                              unsigned long val)
  69 {
  70         writel(val, chip->regs + (num << 4));
  71 }
  72
  73 static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  74                             int duty_ns, int period_ns)
  75 {
  76         struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
  77         unsigned long long c = duty_ns;
  78         unsigned long rate, hz;
  79         unsigned long long ns100 = NSEC_PER_SEC;
  80         u32 val = 0;
  81         int err;
  82
  83         /*
  84          * Convert from duty_ns / period_ns to a fixed number of duty ticks
  85          * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
  86          * nearest integer during division.
  87          */
  88         c *= (1 << PWM_DUTY_WIDTH);
  89         c += period_ns / 2;
  90         do_div(c, period_ns);
  91
  92         val = (u32)c << PWM_DUTY_SHIFT;
  93
  94         /*
  95          * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH)
  96          * cycles at the PWM clock rate will take period_ns nanoseconds.
  97          */
  98         rate = clk_get_rate(pc->clk) >> PWM_DUTY_WIDTH;
  99
 100         /* Consider precision in PWM_SCALE_WIDTH rate calculation */
 101         ns100 *= 100;
 102         hz = DIV_ROUND_CLOSEST_ULL(ns100, period_ns);
 103         rate = DIV_ROUND_CLOSEST(rate * 100, hz);
 104
 105         /*
 106          * Since the actual PWM divider is the register's frequency divider
 107          * field minus 1, we need to decrement to get the correct value to
 108          * write to the register.
 109          */
 110         if (rate > 0)
 111                 rate--;
 112
 113         /*
 114          * Make sure that the rate will fit in the register's frequency
 115          * divider field.
 116          */
 117         if (rate >> PWM_SCALE_WIDTH)
 118                 return -EINVAL;
 119
 120         val |= rate << PWM_SCALE_SHIFT;
 121
 122         /*
 123          * If the PWM channel is disabled, make sure to turn on the clock
 124          * before writing the register. Otherwise, keep it enabled.
 125          */
 126         if (!pwm_is_enabled(pwm)) {
 127                 err = clk_prepare_enable(pc->clk);
 128                 if (err < 0)
 129                         return err;
 130         } else
 131                 val |= PWM_ENABLE;
 132
 133         pwm_writel(pc, pwm->hwpwm, val);
 134
 135         /*
 136          * If the PWM is not enabled, turn the clock off again to save power.
 137          */
 138         if (!pwm_is_enabled(pwm))
 139                 clk_disable_unprepare(pc->clk);
 140
 141         return 0;
 142 }
 143
 144 static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 145 {
 146         struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
 147         int rc = 0;
 148         u32 val;
 149
 150         rc = clk_prepare_enable(pc->clk);
 151         if (rc < 0)
 152                 return rc;
 153
 154         val = pwm_readl(pc, pwm->hwpwm);
 155         val |= PWM_ENABLE;
 156         pwm_writel(pc, pwm->hwpwm, val);
 157
 158         return 0;
 159 }
 160
 161 static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 162 {
 163         struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
 164         u32 val;
 165
 166         val = pwm_readl(pc, pwm->hwpwm);
 167         val &= ~PWM_ENABLE;
 168         pwm_writel(pc, pwm->hwpwm, val);
 169
 170         clk_disable_unprepare(pc->clk);
 171 }
 172
 173 static const struct pwm_ops tegra_pwm_ops = {
 174         .config = tegra_pwm_config,
 175         .enable = tegra_pwm_enable,
 176         .disable = tegra_pwm_disable,
 177         .owner = THIS_MODULE,
 178 };
 179
 180 static int tegra_pwm_probe(struct platform_device *pdev)
 181 {
 182         struct tegra_pwm_chip *pwm;
 183         struct resource *r;
 184         int ret;
 185
 186         pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
 187         if (!pwm)
 188                 return -ENOMEM;
 189
 190         pwm->soc = of_device_get_match_data(&pdev->dev);
 191         pwm->dev = &pdev->dev;
 192
 193         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 194         pwm->regs = devm_ioremap_resource(&pdev->dev, r);
 195         if (IS_ERR(pwm->regs))
 196                 return PTR_ERR(pwm->regs);
 197
 198         platform_set_drvdata(pdev, pwm);
 199
 200         pwm->clk = devm_clk_get(&pdev->dev, NULL);
 201         if (IS_ERR(pwm->clk))
 202                 return PTR_ERR(pwm->clk);
 203
 204         pwm->rst = devm_reset_control_get(&pdev->dev, "pwm");
 205         if (IS_ERR(pwm->rst)) {
 206                 ret = PTR_ERR(pwm->rst);
 207                 dev_err(&pdev->dev, "Reset control is not found: %d\n", ret);
 208                 return ret;
 209         }
 210
 211         reset_control_deassert(pwm->rst);
 212
 213         pwm->chip.dev = &pdev->dev;
 214         pwm->chip.ops = &tegra_pwm_ops;
 215         pwm->chip.base = -1;
 216         pwm->chip.npwm = pwm->soc->num_channels;
 217
 218         ret = pwmchip_add(&pwm->chip);
 219         if (ret < 0) {
 220                 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
 221                 reset_control_assert(pwm->rst);
 222                 return ret;
 223         }
 224
 225         return 0;
 226 }
 227
 228 static int tegra_pwm_remove(struct platform_device *pdev)
 229 {
 230         struct tegra_pwm_chip *pc = platform_get_drvdata(pdev);
 231         unsigned int i;
 232         int err;
 233
 234         if (WARN_ON(!pc))
 235                 return -ENODEV;
 236
 237         err = clk_prepare_enable(pc->clk);
 238         if (err < 0)
 239                 return err;
 240
 241         for (i = 0; i < pc->chip.npwm; i++) {
 242                 struct pwm_device *pwm = &pc->chip.pwms[i];
 243
 244                 if (!pwm_is_enabled(pwm))
 245                         if (clk_prepare_enable(pc->clk) < 0)
 246                                 continue;
 247
 248                 pwm_writel(pc, i, 0);
 249
 250                 clk_disable_unprepare(pc->clk);
 251         }
 252
 253         reset_control_assert(pc->rst);
 254         clk_disable_unprepare(pc->clk);
 255
 256         return pwmchip_remove(&pc->chip);
 257 }
 258
 259 static const struct tegra_pwm_soc tegra20_pwm_soc = {
 260         .num_channels = 4,
 261 };
 262
 263 static const struct tegra_pwm_soc tegra186_pwm_soc = {
 264         .num_channels = 1,
 265 };
 266
 267 static const struct of_device_id tegra_pwm_of_match[] = {
 268         { .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
 269         { .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
 270         { }
 271 };
 272
 273 MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);
 274
 275 static struct platform_driver tegra_pwm_driver = {
 276         .driver = {
 277                 .name = "tegra-pwm",
 278                 .of_match_table = tegra_pwm_of_match,
 279         },
 280         .probe = tegra_pwm_probe,
 281         .remove = tegra_pwm_remove,
 282 };
 283
 284 module_platform_driver(tegra_pwm_driver);
 285
 286 MODULE_LICENSE("GPL");
 287 MODULE_AUTHOR("NVIDIA Corporation");
 288 MODULE_ALIAS("platform:tegra-pwm");