drivers/usb/chipidea/bits.h

   1 /*
   2  * bits.h - register bits of the ChipIdea USB IP core
   3  *
   4  * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
   5  *
   6  * Author: David Lopo
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __DRIVERS_USB_CHIPIDEA_BITS_H
  14 #define __DRIVERS_USB_CHIPIDEA_BITS_H
  15
  16 #include <linux/usb/ehci_def.h>
  17
  18 /*
  19  * ID
  20  * For 1.x revision, bit24 - bit31 are reserved
  21  * For 2.x revision, bit25 - bit28 are 0x2
  22  */
  23 #define TAG                   (0x1F << 16)
  24 #define REVISION              (0xF << 21)
  25 #define VERSION               (0xF << 25)
  26 #define CIVERSION             (0x7 << 29)
  27
  28 /* SBUSCFG */
  29 #define AHBBRST_MASK            0x7
  30
  31 /* HCCPARAMS */
  32 #define HCCPARAMS_LEN         BIT(17)
  33
  34 /* DCCPARAMS */
  35 #define DCCPARAMS_DEN         (0x1F << 0)
  36 #define DCCPARAMS_DC          BIT(7)
  37 #define DCCPARAMS_HC          BIT(8)
  38
  39 /* TESTMODE */
  40 #define TESTMODE_FORCE        BIT(0)
  41
  42 /* USBCMD */
  43 #define USBCMD_RS             BIT(0)
  44 #define USBCMD_RST            BIT(1)
  45 #define USBCMD_SUTW           BIT(13)
  46 #define USBCMD_ATDTW          BIT(14)
  47
  48 /* USBSTS & USBINTR */
  49 #define USBi_UI               BIT(0)
  50 #define USBi_UEI              BIT(1)
  51 #define USBi_PCI              BIT(2)
  52 #define USBi_URI              BIT(6)
  53 #define USBi_SLI              BIT(8)
  54
  55 /* DEVICEADDR */
  56 #define DEVICEADDR_USBADRA    BIT(24)
  57 #define DEVICEADDR_USBADR     (0x7FUL << 25)
  58
  59 /* TTCTRL */
  60 #define TTCTRL_TTHA_MASK        (0x7fUL << 24)
  61 /* Set non-zero value for internal TT Hub address representation */
  62 #define TTCTRL_TTHA             (0x7fUL << 24)
  63
  64 /* BURSTSIZE */
  65 #define RX_BURST_MASK           0xff
  66 #define TX_BURST_MASK           0xff00
  67
  68 /* PORTSC */
  69 #define PORTSC_CCS            BIT(0)
  70 #define PORTSC_CSC            BIT(1)
  71 #define PORTSC_PEC            BIT(3)
  72 #define PORTSC_OCC            BIT(5)
  73 #define PORTSC_FPR            BIT(6)
  74 #define PORTSC_SUSP           BIT(7)
  75 #define PORTSC_HSP            BIT(9)
  76 #define PORTSC_PP             BIT(12)
  77 #define PORTSC_PTC            (0x0FUL << 16)
  78 #define PORTSC_WKCN           BIT(20)
  79 #define PORTSC_PHCD(d)        ((d) ? BIT(22) : BIT(23))
  80 /* PTS and PTW for non lpm version only */
  81 #define PORTSC_PFSC           BIT(24)
  82 #define PORTSC_PTS(d)                                           \
  83         (u32)((((d) & 0x3) << 30) | (((d) & 0x4) ? BIT(25) : 0))
  84 #define PORTSC_PTW            BIT(28)
  85 #define PORTSC_STS            BIT(29)
  86
  87 #define PORTSC_W1C_BITS                                         \
  88         (PORTSC_CSC | PORTSC_PEC | PORTSC_OCC)
  89
  90 /* DEVLC */
  91 #define DEVLC_PFSC            BIT(23)
  92 #define DEVLC_PSPD            (0x03UL << 25)
  93 #define DEVLC_PSPD_HS         (0x02UL << 25)
  94 #define DEVLC_PTW             BIT(27)
  95 #define DEVLC_STS             BIT(28)
  96 #define DEVLC_PTS(d)          (u32)(((d) & 0x7) << 29)
  97
  98 /* Encoding for DEVLC_PTS and PORTSC_PTS */
  99 #define PTS_UTMI              0
 100 #define PTS_ULPI              2
 101 #define PTS_SERIAL            3
 102 #define PTS_HSIC              4
 103
 104 /* OTGSC */
 105 #define OTGSC_IDPU            BIT(5)
 106 #define OTGSC_HADP            BIT(6)
 107 #define OTGSC_HABA            BIT(7)
 108 #define OTGSC_ID              BIT(8)
 109 #define OTGSC_AVV             BIT(9)
 110 #define OTGSC_ASV             BIT(10)
 111 #define OTGSC_BSV             BIT(11)
 112 #define OTGSC_BSE             BIT(12)
 113 #define OTGSC_IDIS            BIT(16)
 114 #define OTGSC_AVVIS           BIT(17)
 115 #define OTGSC_ASVIS           BIT(18)
 116 #define OTGSC_BSVIS           BIT(19)
 117 #define OTGSC_BSEIS           BIT(20)
 118 #define OTGSC_1MSIS           BIT(21)
 119 #define OTGSC_DPIS            BIT(22)
 120 #define OTGSC_IDIE            BIT(24)
 121 #define OTGSC_AVVIE           BIT(25)
 122 #define OTGSC_ASVIE           BIT(26)
 123 #define OTGSC_BSVIE           BIT(27)
 124 #define OTGSC_BSEIE           BIT(28)
 125 #define OTGSC_1MSIE           BIT(29)
 126 #define OTGSC_DPIE            BIT(30)
 127 #define OTGSC_INT_EN_BITS       (OTGSC_IDIE | OTGSC_AVVIE | OTGSC_ASVIE \
 128                                 | OTGSC_BSVIE | OTGSC_BSEIE | OTGSC_1MSIE \
 129                                 | OTGSC_DPIE)
 130 #define OTGSC_INT_STATUS_BITS   (OTGSC_IDIS | OTGSC_AVVIS | OTGSC_ASVIS \
 131                                 | OTGSC_BSVIS | OTGSC_BSEIS | OTGSC_1MSIS \
 132                                 | OTGSC_DPIS)
 133
 134 /* USBMODE */
 135 #define USBMODE_CM            (0x03UL <<  0)
 136 #define USBMODE_CM_DC         (0x02UL <<  0)
 137 #define USBMODE_SLOM          BIT(3)
 138 #define USBMODE_CI_SDIS       BIT(4)
 139
 140 /* ENDPTCTRL */
 141 #define ENDPTCTRL_RXS         BIT(0)
 142 #define ENDPTCTRL_RXT         (0x03UL <<  2)
 143 #define ENDPTCTRL_RXR         BIT(6)         /* reserved for port 0 */
 144 #define ENDPTCTRL_RXE         BIT(7)
 145 #define ENDPTCTRL_TXS         BIT(16)
 146 #define ENDPTCTRL_TXT         (0x03UL << 18)
 147 #define ENDPTCTRL_TXR         BIT(22)        /* reserved for port 0 */
 148 #define ENDPTCTRL_TXE         BIT(23)
 149
 150 #endif /* __DRIVERS_USB_CHIPIDEA_BITS_H */