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inet: frag: enforce memory limits earlier
[linux/fpc-iii.git] / drivers / usb / host / ohci-pxa27x.c
bloba667cf2d57883689538e2a0d9a471b494e831b0c
1 /*
2 * OHCI HCD (Host Controller Driver) for USB.
3 *
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
6 * (C) Copyright 2002 Hewlett-Packard Company
7 *
8 * Bus Glue for pxa27x
9 *
10 * Written by Christopher Hoover <ch@hpl.hp.com>
11 * Based on fragments of previous driver by Russell King et al.
12 *
13 * Modified for LH7A404 from ohci-sa1111.c
14 * by Durgesh Pattamatta <pattamattad@sharpsec.com>
15 *
16 * Modified for pxa27x from ohci-lh7a404.c
17 * by Nick Bane <nick@cecomputing.co.uk> 26-8-2004
18 *
19 * This file is licenced under the GPL.
20 */
21
22 #include <linux/clk.h>
23 #include <linux/device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/io.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/of_platform.h>
29 #include <linux/of_gpio.h>
30 #include <linux/platform_data/usb-ohci-pxa27x.h>
31 #include <linux/platform_data/usb-pxa3xx-ulpi.h>
32 #include <linux/platform_device.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/signal.h>
35 #include <linux/usb.h>
36 #include <linux/usb/hcd.h>
37 #include <linux/usb/otg.h>
38
39 #include <mach/hardware.h>
40
41 #include "ohci.h"
42
43 #define DRIVER_DESC "OHCI PXA27x/PXA3x driver"
44
45 /*
46 * UHC: USB Host Controller (OHCI-like) register definitions
47 */
48 #define UHCREV (0x0000) /* UHC HCI Spec Revision */
49 #define UHCHCON (0x0004) /* UHC Host Control Register */
50 #define UHCCOMS (0x0008) /* UHC Command Status Register */
51 #define UHCINTS (0x000C) /* UHC Interrupt Status Register */
52 #define UHCINTE (0x0010) /* UHC Interrupt Enable */
53 #define UHCINTD (0x0014) /* UHC Interrupt Disable */
54 #define UHCHCCA (0x0018) /* UHC Host Controller Comm. Area */
55 #define UHCPCED (0x001C) /* UHC Period Current Endpt Descr */
56 #define UHCCHED (0x0020) /* UHC Control Head Endpt Descr */
57 #define UHCCCED (0x0024) /* UHC Control Current Endpt Descr */
58 #define UHCBHED (0x0028) /* UHC Bulk Head Endpt Descr */
59 #define UHCBCED (0x002C) /* UHC Bulk Current Endpt Descr */
60 #define UHCDHEAD (0x0030) /* UHC Done Head */
61 #define UHCFMI (0x0034) /* UHC Frame Interval */
62 #define UHCFMR (0x0038) /* UHC Frame Remaining */
63 #define UHCFMN (0x003C) /* UHC Frame Number */
64 #define UHCPERS (0x0040) /* UHC Periodic Start */
65 #define UHCLS (0x0044) /* UHC Low Speed Threshold */
66
67 #define UHCRHDA (0x0048) /* UHC Root Hub Descriptor A */
68 #define UHCRHDA_NOCP (1 << 12) /* No over current protection */
69 #define UHCRHDA_OCPM (1 << 11) /* Over Current Protection Mode */
70 #define UHCRHDA_POTPGT(x) \
71 (((x) & 0xff) << 24) /* Power On To Power Good Time */
72
73 #define UHCRHDB (0x004C) /* UHC Root Hub Descriptor B */
74 #define UHCRHS (0x0050) /* UHC Root Hub Status */
75 #define UHCRHPS1 (0x0054) /* UHC Root Hub Port 1 Status */
76 #define UHCRHPS2 (0x0058) /* UHC Root Hub Port 2 Status */
77 #define UHCRHPS3 (0x005C) /* UHC Root Hub Port 3 Status */
78
79 #define UHCSTAT (0x0060) /* UHC Status Register */
80 #define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
81 #define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
82 #define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
83 #define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
84 #define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
85 #define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
86 #define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
87 #define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
88 #define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
89
90 #define UHCHR (0x0064) /* UHC Reset Register */
91 #define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
92 #define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
93 #define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
94 #define UHCHR_PCPL (1 << 7) /* Power control polarity low */
95 #define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
96 #define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
97 #define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
98 #define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
99 #define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
100 #define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
101 #define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
102
103 #define UHCHIE (0x0068) /* UHC Interrupt Enable Register*/
104 #define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
105 #define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
106 #define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
107 #define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
108 #define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
109 Interrupt Enable*/
110 #define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
111 #define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
112
113 #define UHCHIT (0x006C) /* UHC Interrupt Test register */
114
115 #define PXA_UHC_MAX_PORTNUM 3
116
117 static const char hcd_name[] = "ohci-pxa27x";
118
119 static struct hc_driver __read_mostly ohci_pxa27x_hc_driver;
120
121 struct pxa27x_ohci {
122 struct clk *clk;
123 void __iomem *mmio_base;
124 struct regulator *vbus[3];
125 bool vbus_enabled[3];
126 };
127
128 #define to_pxa27x_ohci(hcd) (struct pxa27x_ohci *)(hcd_to_ohci(hcd)->priv)
129
130 /*
131 PMM_NPS_MODE -- PMM Non-power switching mode
132 Ports are powered continuously.
133
134 PMM_GLOBAL_MODE -- PMM global switching mode
135 All ports are powered at the same time.
136
137 PMM_PERPORT_MODE -- PMM per port switching mode
138 Ports are powered individually.
139 */
140 static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *pxa_ohci, int mode)
141 {
142 uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA);
143 uint32_t uhcrhdb = __raw_readl(pxa_ohci->mmio_base + UHCRHDB);
144
145 switch (mode) {
146 case PMM_NPS_MODE:
147 uhcrhda |= RH_A_NPS;
148 break;
149 case PMM_GLOBAL_MODE:
150 uhcrhda &= ~(RH_A_NPS & RH_A_PSM);
151 break;
152 case PMM_PERPORT_MODE:
153 uhcrhda &= ~(RH_A_NPS);
154 uhcrhda |= RH_A_PSM;
155
156 /* Set port power control mask bits, only 3 ports. */
157 uhcrhdb |= (0x7<<17);
158 break;
159 default:
160 printk( KERN_ERR
161 "Invalid mode %d, set to non-power switch mode.\n",
162 mode );
163
164 uhcrhda |= RH_A_NPS;
165 }
166
167 __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA);
168 __raw_writel(uhcrhdb, pxa_ohci->mmio_base + UHCRHDB);
169 return 0;
170 }
171
172 static int pxa27x_ohci_set_vbus_power(struct pxa27x_ohci *pxa_ohci,
173 unsigned int port, bool enable)
174 {
175 struct regulator *vbus = pxa_ohci->vbus[port];
176 int ret = 0;
177
178 if (IS_ERR_OR_NULL(vbus))
179 return 0;
180
181 if (enable && !pxa_ohci->vbus_enabled[port])
182 ret = regulator_enable(vbus);
183 else if (!enable && pxa_ohci->vbus_enabled[port])
184 ret = regulator_disable(vbus);
185
186 if (ret < 0)
187 return ret;
188
189 pxa_ohci->vbus_enabled[port] = enable;
190
191 return 0;
192 }
193
194 static int pxa27x_ohci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
195 u16 wIndex, char *buf, u16 wLength)
196 {
197 struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
198 int ret;
199
200 switch (typeReq) {
201 case SetPortFeature:
202 case ClearPortFeature:
203 if (!wIndex || wIndex > 3)
204 return -EPIPE;
205
206 if (wValue != USB_PORT_FEAT_POWER)
207 break;
208
209 ret = pxa27x_ohci_set_vbus_power(pxa_ohci, wIndex - 1,
210 typeReq == SetPortFeature);
211 if (ret)
212 return ret;
213 break;
214 }
215
216 return ohci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
217 }
218 /*-------------------------------------------------------------------------*/
219
220 static inline void pxa27x_setup_hc(struct pxa27x_ohci *pxa_ohci,
221 struct pxaohci_platform_data *inf)
222 {
223 uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR);
224 uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA);
225
226 if (inf->flags & ENABLE_PORT1)
227 uhchr &= ~UHCHR_SSEP1;
228
229 if (inf->flags & ENABLE_PORT2)
230 uhchr &= ~UHCHR_SSEP2;
231
232 if (inf->flags & ENABLE_PORT3)
233 uhchr &= ~UHCHR_SSEP3;
234
235 if (inf->flags & POWER_CONTROL_LOW)
236 uhchr |= UHCHR_PCPL;
237
238 if (inf->flags & POWER_SENSE_LOW)
239 uhchr |= UHCHR_PSPL;
240
241 if (inf->flags & NO_OC_PROTECTION)
242 uhcrhda |= UHCRHDA_NOCP;
243 else
244 uhcrhda &= ~UHCRHDA_NOCP;
245
246 if (inf->flags & OC_MODE_PERPORT)
247 uhcrhda |= UHCRHDA_OCPM;
248 else
249 uhcrhda &= ~UHCRHDA_OCPM;
250
251 if (inf->power_on_delay) {
252 uhcrhda &= ~UHCRHDA_POTPGT(0xff);
253 uhcrhda |= UHCRHDA_POTPGT(inf->power_on_delay / 2);
254 }
255
256 __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
257 __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA);
258 }
259
260 static inline void pxa27x_reset_hc(struct pxa27x_ohci *pxa_ohci)
261 {
262 uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR);
263
264 __raw_writel(uhchr | UHCHR_FHR, pxa_ohci->mmio_base + UHCHR);
265 udelay(11);
266 __raw_writel(uhchr & ~UHCHR_FHR, pxa_ohci->mmio_base + UHCHR);
267 }
268
269 #ifdef CONFIG_PXA27x
270 extern void pxa27x_clear_otgph(void);
271 #else
272 #define pxa27x_clear_otgph() do {} while (0)
273 #endif
274
275 static int pxa27x_start_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev)
276 {
277 int retval = 0;
278 struct pxaohci_platform_data *inf;
279 uint32_t uhchr;
280 struct usb_hcd *hcd = dev_get_drvdata(dev);
281
282 inf = dev_get_platdata(dev);
283
284 clk_prepare_enable(pxa_ohci->clk);
285
286 pxa27x_reset_hc(pxa_ohci);
287
288 uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) | UHCHR_FSBIR;
289 __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
290
291 while (__raw_readl(pxa_ohci->mmio_base + UHCHR) & UHCHR_FSBIR)
292 cpu_relax();
293
294 pxa27x_setup_hc(pxa_ohci, inf);
295
296 if (inf->init)
297 retval = inf->init(dev);
298
299 if (retval < 0)
300 return retval;
301
302 if (cpu_is_pxa3xx())
303 pxa3xx_u2d_start_hc(&hcd->self);
304
305 uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) & ~UHCHR_SSE;
306 __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
307 __raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, pxa_ohci->mmio_base + UHCHIE);
308
309 /* Clear any OTG Pin Hold */
310 pxa27x_clear_otgph();
311 return 0;
312 }
313
314 static void pxa27x_stop_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev)
315 {
316 struct pxaohci_platform_data *inf;
317 struct usb_hcd *hcd = dev_get_drvdata(dev);
318 uint32_t uhccoms;
319
320 inf = dev_get_platdata(dev);
321
322 if (cpu_is_pxa3xx())
323 pxa3xx_u2d_stop_hc(&hcd->self);
324
325 if (inf->exit)
326 inf->exit(dev);
327
328 pxa27x_reset_hc(pxa_ohci);
329
330 /* Host Controller Reset */
331 uhccoms = __raw_readl(pxa_ohci->mmio_base + UHCCOMS) | 0x01;
332 __raw_writel(uhccoms, pxa_ohci->mmio_base + UHCCOMS);
333 udelay(10);
334
335 clk_disable_unprepare(pxa_ohci->clk);
336 }
337
338 #ifdef CONFIG_OF
339 static const struct of_device_id pxa_ohci_dt_ids[] = {
340 { .compatible = "marvell,pxa-ohci" },
341 { }
342 };
343
344 MODULE_DEVICE_TABLE(of, pxa_ohci_dt_ids);
345
346 static int ohci_pxa_of_init(struct platform_device *pdev)
347 {
348 struct device_node *np = pdev->dev.of_node;
349 struct pxaohci_platform_data *pdata;
350 u32 tmp;
351 int ret;
352
353 if (!np)
354 return 0;
355
356 /* Right now device-tree probed devices don't get dma_mask set.
357 * Since shared usb code relies on it, set it here for now.
358 * Once we have dma capability bindings this can go away.
359 */
360 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
361 if (ret)
362 return ret;
363
364 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
365 if (!pdata)
366 return -ENOMEM;
367
368 if (of_property_read_bool(np, "marvell,enable-port1"))
369 pdata->flags |= ENABLE_PORT1;
370 if (of_property_read_bool(np, "marvell,enable-port2"))
371 pdata->flags |= ENABLE_PORT2;
372 if (of_property_read_bool(np, "marvell,enable-port3"))
373 pdata->flags |= ENABLE_PORT3;
374 if (of_property_read_bool(np, "marvell,port-sense-low"))
375 pdata->flags |= POWER_SENSE_LOW;
376 if (of_property_read_bool(np, "marvell,power-control-low"))
377 pdata->flags |= POWER_CONTROL_LOW;
378 if (of_property_read_bool(np, "marvell,no-oc-protection"))
379 pdata->flags |= NO_OC_PROTECTION;
380 if (of_property_read_bool(np, "marvell,oc-mode-perport"))
381 pdata->flags |= OC_MODE_PERPORT;
382 if (!of_property_read_u32(np, "marvell,power-on-delay", &tmp))
383 pdata->power_on_delay = tmp;
384 if (!of_property_read_u32(np, "marvell,port-mode", &tmp))
385 pdata->port_mode = tmp;
386 if (!of_property_read_u32(np, "marvell,power-budget", &tmp))
387 pdata->power_budget = tmp;
388
389 pdev->dev.platform_data = pdata;
390
391 return 0;
392 }
393 #else
394 static int ohci_pxa_of_init(struct platform_device *pdev)
395 {
396 return 0;
397 }
398 #endif
399
400 /*-------------------------------------------------------------------------*/
401
402 /* configure so an HC device and id are always provided */
403 /* always called with process context; sleeping is OK */
404
405
406 /**
407 * usb_hcd_pxa27x_probe - initialize pxa27x-based HCDs
408 * Context: !in_interrupt()
409 *
410 * Allocates basic resources for this USB host controller, and
411 * then invokes the start() method for the HCD associated with it
412 * through the hotplug entry's driver_data.
413 *
414 */
415 int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device *pdev)
416 {
417 int retval, irq;
418 struct usb_hcd *hcd;
419 struct pxaohci_platform_data *inf;
420 struct pxa27x_ohci *pxa_ohci;
421 struct ohci_hcd *ohci;
422 struct resource *r;
423 struct clk *usb_clk;
424 unsigned int i;
425
426 retval = ohci_pxa_of_init(pdev);
427 if (retval)
428 return retval;
429
430 inf = dev_get_platdata(&pdev->dev);
431
432 if (!inf)
433 return -ENODEV;
434
435 irq = platform_get_irq(pdev, 0);
436 if (irq < 0) {
437 pr_err("no resource of IORESOURCE_IRQ");
438 return irq;
439 }
440
441 usb_clk = devm_clk_get(&pdev->dev, NULL);
442 if (IS_ERR(usb_clk))
443 return PTR_ERR(usb_clk);
444
445 hcd = usb_create_hcd (driver, &pdev->dev, "pxa27x");
446 if (!hcd)
447 return -ENOMEM;
448
449 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
450 hcd->regs = devm_ioremap_resource(&pdev->dev, r);
451 if (IS_ERR(hcd->regs)) {
452 retval = PTR_ERR(hcd->regs);
453 goto err;
454 }
455 hcd->rsrc_start = r->start;
456 hcd->rsrc_len = resource_size(r);
457
458 /* initialize "struct pxa27x_ohci" */
459 pxa_ohci = to_pxa27x_ohci(hcd);
460 pxa_ohci->clk = usb_clk;
461 pxa_ohci->mmio_base = (void __iomem *)hcd->regs;
462
463 for (i = 0; i < 3; ++i) {
464 char name[6];
465
466 if (!(inf->flags & (ENABLE_PORT1 << i)))
467 continue;
468
469 sprintf(name, "vbus%u", i + 1);
470 pxa_ohci->vbus[i] = devm_regulator_get(&pdev->dev, name);
471 }
472
473 retval = pxa27x_start_hc(pxa_ohci, &pdev->dev);
474 if (retval < 0) {
475 pr_debug("pxa27x_start_hc failed");
476 goto err;
477 }
478
479 /* Select Power Management Mode */
480 pxa27x_ohci_select_pmm(pxa_ohci, inf->port_mode);
481
482 if (inf->power_budget)
483 hcd->power_budget = inf->power_budget;
484
485 /* The value of NDP in roothub_a is incorrect on this hardware */
486 ohci = hcd_to_ohci(hcd);
487 ohci->num_ports = 3;
488
489 retval = usb_add_hcd(hcd, irq, 0);
490 if (retval == 0) {
491 device_wakeup_enable(hcd->self.controller);
492 return retval;
493 }
494
495 pxa27x_stop_hc(pxa_ohci, &pdev->dev);
496 err:
497 usb_put_hcd(hcd);
498 return retval;
499 }
500
501
502 /* may be called without controller electrically present */
503 /* may be called with controller, bus, and devices active */
504
505 /**
506 * usb_hcd_pxa27x_remove - shutdown processing for pxa27x-based HCDs
507 * @dev: USB Host Controller being removed
508 * Context: !in_interrupt()
509 *
510 * Reverses the effect of usb_hcd_pxa27x_probe(), first invoking
511 * the HCD's stop() method. It is always called from a thread
512 * context, normally "rmmod", "apmd", or something similar.
513 *
514 */
515 void usb_hcd_pxa27x_remove (struct usb_hcd *hcd, struct platform_device *pdev)
516 {
517 struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
518 unsigned int i;
519
520 usb_remove_hcd(hcd);
521 pxa27x_stop_hc(pxa_ohci, &pdev->dev);
522
523 for (i = 0; i < 3; ++i)
524 pxa27x_ohci_set_vbus_power(pxa_ohci, i, false);
525
526 usb_put_hcd(hcd);
527 }
528
529 /*-------------------------------------------------------------------------*/
530
531 static int ohci_hcd_pxa27x_drv_probe(struct platform_device *pdev)
532 {
533 pr_debug ("In ohci_hcd_pxa27x_drv_probe");
534
535 if (usb_disabled())
536 return -ENODEV;
537
538 return usb_hcd_pxa27x_probe(&ohci_pxa27x_hc_driver, pdev);
539 }
540
541 static int ohci_hcd_pxa27x_drv_remove(struct platform_device *pdev)
542 {
543 struct usb_hcd *hcd = platform_get_drvdata(pdev);
544
545 usb_hcd_pxa27x_remove(hcd, pdev);
546 return 0;
547 }
548
549 #ifdef CONFIG_PM
550 static int ohci_hcd_pxa27x_drv_suspend(struct device *dev)
551 {
552 struct usb_hcd *hcd = dev_get_drvdata(dev);
553 struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
554 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
555 bool do_wakeup = device_may_wakeup(dev);
556 int ret;
557
558
559 if (time_before(jiffies, ohci->next_statechange))
560 msleep(5);
561 ohci->next_statechange = jiffies;
562
563 ret = ohci_suspend(hcd, do_wakeup);
564 if (ret)
565 return ret;
566
567 pxa27x_stop_hc(pxa_ohci, dev);
568 return ret;
569 }
570
571 static int ohci_hcd_pxa27x_drv_resume(struct device *dev)
572 {
573 struct usb_hcd *hcd = dev_get_drvdata(dev);
574 struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
575 struct pxaohci_platform_data *inf = dev_get_platdata(dev);
576 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
577 int status;
578
579 if (time_before(jiffies, ohci->next_statechange))
580 msleep(5);
581 ohci->next_statechange = jiffies;
582
583 status = pxa27x_start_hc(pxa_ohci, dev);
584 if (status < 0)
585 return status;
586
587 /* Select Power Management Mode */
588 pxa27x_ohci_select_pmm(pxa_ohci, inf->port_mode);
589
590 ohci_resume(hcd, false);
591 return 0;
592 }
593
594 static const struct dev_pm_ops ohci_hcd_pxa27x_pm_ops = {
595 .suspend = ohci_hcd_pxa27x_drv_suspend,
596 .resume = ohci_hcd_pxa27x_drv_resume,
597 };
598 #endif
599
600 static struct platform_driver ohci_hcd_pxa27x_driver = {
601 .probe = ohci_hcd_pxa27x_drv_probe,
602 .remove = ohci_hcd_pxa27x_drv_remove,
603 .shutdown = usb_hcd_platform_shutdown,
604 .driver = {
605 .name = "pxa27x-ohci",
606 .of_match_table = of_match_ptr(pxa_ohci_dt_ids),
607 #ifdef CONFIG_PM
608 .pm = &ohci_hcd_pxa27x_pm_ops,
609 #endif
610 },
611 };
612
613 static const struct ohci_driver_overrides pxa27x_overrides __initconst = {
614 .extra_priv_size = sizeof(struct pxa27x_ohci),
615 };
616
617 static int __init ohci_pxa27x_init(void)
618 {
619 if (usb_disabled())
620 return -ENODEV;
621
622 pr_info("%s: " DRIVER_DESC "\n", hcd_name);
623
624 ohci_init_driver(&ohci_pxa27x_hc_driver, &pxa27x_overrides);
625 ohci_pxa27x_hc_driver.hub_control = pxa27x_ohci_hub_control;
626
627 return platform_driver_register(&ohci_hcd_pxa27x_driver);
628 }
629 module_init(ohci_pxa27x_init);
630
631 static void __exit ohci_pxa27x_cleanup(void)
632 {
633 platform_driver_unregister(&ohci_hcd_pxa27x_driver);
634 }
635 module_exit(ohci_pxa27x_cleanup);
636
637 MODULE_DESCRIPTION(DRIVER_DESC);
638 MODULE_LICENSE("GPL");
639 MODULE_ALIAS("platform:pxa27x-ohci");
Linux with added FPC-III support