drivers/usb/host/ohci.h

   1 /*
   2  * OHCI HCD (Host Controller Driver) for USB.
   3  *
   4  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   5  * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
   6  *
   7  * This file is licenced under the GPL.
   8  */
   9
  10 /*
  11  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
  12  * __leXX (normally) or __beXX (given OHCI_BIG_ENDIAN), depending on the
  13  * host controller implementation.
  14  */
  15 typedef __u32 __bitwise __hc32;
  16 typedef __u16 __bitwise __hc16;
  17
  18 /*
  19  * OHCI Endpoint Descriptor (ED) ... holds TD queue
  20  * See OHCI spec, section 4.2
  21  *
  22  * This is a "Queue Head" for those transfers, which is why
  23  * both EHCI and UHCI call similar structures a "QH".
  24  */
  25 struct ed {
  26         /* first fields are hardware-specified */
  27         __hc32                  hwINFO;      /* endpoint config bitmap */
  28         /* info bits defined by hcd */
  29 #define ED_DEQUEUE      (1 << 27)
  30         /* info bits defined by the hardware */
  31 #define ED_ISO          (1 << 15)
  32 #define ED_SKIP         (1 << 14)
  33 #define ED_LOWSPEED     (1 << 13)
  34 #define ED_OUT          (0x01 << 11)
  35 #define ED_IN           (0x02 << 11)
  36         __hc32                  hwTailP;        /* tail of TD list */
  37         __hc32                  hwHeadP;        /* head of TD list (hc r/w) */
  38 #define ED_C            (0x02)                  /* toggle carry */
  39 #define ED_H            (0x01)                  /* halted */
  40         __hc32                  hwNextED;       /* next ED in list */
  41
  42         /* rest are purely for the driver's use */
  43         dma_addr_t              dma;            /* addr of ED */
  44         struct td               *dummy;         /* next TD to activate */
  45
  46         /* host's view of schedule */
  47         struct ed               *ed_next;       /* on schedule or rm_list */
  48         struct ed               *ed_prev;       /* for non-interrupt EDs */
  49         struct list_head        td_list;        /* "shadow list" of our TDs */
  50         struct list_head        in_use_list;
  51
  52         /* create --> IDLE --> OPER --> ... --> IDLE --> destroy
  53          * usually:  OPER --> UNLINK --> (IDLE | OPER) --> ...
  54          */
  55         u8                      state;          /* ED_{IDLE,UNLINK,OPER} */
  56 #define ED_IDLE         0x00            /* NOT linked to HC */
  57 #define ED_UNLINK       0x01            /* being unlinked from hc */
  58 #define ED_OPER         0x02            /* IS linked to hc */
  59
  60         u8                      type;           /* PIPE_{BULK,...} */
  61
  62         /* periodic scheduling params (for intr and iso) */
  63         u8                      branch;
  64         u16                     interval;
  65         u16                     load;
  66         u16                     last_iso;       /* iso only */
  67
  68         /* HC may see EDs on rm_list until next frame (frame_no == tick) */
  69         u16                     tick;
  70
  71         /* Detect TDs not added to the done queue */
  72         unsigned                takeback_wdh_cnt;
  73         struct td               *pending_td;
  74 #define OKAY_TO_TAKEBACK(ohci, ed)                      \
  75                 ((int) (ohci->wdh_cnt - ed->takeback_wdh_cnt) >= 0)
  76
  77 } __attribute__ ((aligned(16)));
  78
  79 #define ED_MASK ((u32)~0x0f)            /* strip hw status in low addr bits */
  80
  81
  82 /*
  83  * OHCI Transfer Descriptor (TD) ... one per transfer segment
  84  * See OHCI spec, sections 4.3.1 (general = control/bulk/interrupt)
  85  * and 4.3.2 (iso)
  86  */
  87 struct td {
  88         /* first fields are hardware-specified */
  89         __hc32          hwINFO;         /* transfer info bitmask */
  90
  91         /* hwINFO bits for both general and iso tds: */
  92 #define TD_CC       0xf0000000                  /* condition code */
  93 #define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
  94 //#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
  95 #define TD_DI       0x00E00000                  /* frames before interrupt */
  96 #define TD_DI_SET(X) (((X) & 0x07)<< 21)
  97         /* these two bits are available for definition/use by HCDs in both
  98          * general and iso tds ... others are available for only one type
  99          */
 100 #define TD_DONE     0x00020000                  /* retired to donelist */
 101 #define TD_ISO      0x00010000                  /* copy of ED_ISO */
 102
 103         /* hwINFO bits for general tds: */
 104 #define TD_EC       0x0C000000                  /* error count */
 105 #define TD_T        0x03000000                  /* data toggle state */
 106 #define TD_T_DATA0  0x02000000                          /* DATA0 */
 107 #define TD_T_DATA1  0x03000000                          /* DATA1 */
 108 #define TD_T_TOGGLE 0x00000000                          /* uses ED_C */
 109 #define TD_DP       0x00180000                  /* direction/pid */
 110 #define TD_DP_SETUP 0x00000000                  /* SETUP pid */
 111 #define TD_DP_IN    0x00100000                          /* IN pid */
 112 #define TD_DP_OUT   0x00080000                          /* OUT pid */
 113                                                         /* 0x00180000 rsvd */
 114 #define TD_R        0x00040000                  /* round: short packets OK? */
 115
 116         /* (no hwINFO #defines yet for iso tds) */
 117
 118         __hc32          hwCBP;          /* Current Buffer Pointer (or 0) */
 119         __hc32          hwNextTD;       /* Next TD Pointer */
 120         __hc32          hwBE;           /* Memory Buffer End Pointer */
 121
 122         /* PSW is only for ISO.  Only 1 PSW entry is used, but on
 123          * big-endian PPC hardware that's the second entry.
 124          */
 125 #define MAXPSW  2
 126         __hc16          hwPSW [MAXPSW];
 127
 128         /* rest are purely for the driver's use */
 129         __u8            index;
 130         struct ed       *ed;
 131         struct td       *td_hash;       /* dma-->td hashtable */
 132         struct td       *next_dl_td;
 133         struct urb      *urb;
 134
 135         dma_addr_t      td_dma;         /* addr of this TD */
 136         dma_addr_t      data_dma;       /* addr of data it points to */
 137
 138         struct list_head td_list;       /* "shadow list", TDs on same ED */
 139 } __attribute__ ((aligned(32)));        /* c/b/i need 16; only iso needs 32 */
 140
 141 #define TD_MASK ((u32)~0x1f)            /* strip hw status in low addr bits */
 142
 143 /*
 144  * Hardware transfer status codes -- CC from td->hwINFO or td->hwPSW
 145  */
 146 #define TD_CC_NOERROR      0x00
 147 #define TD_CC_CRC          0x01
 148 #define TD_CC_BITSTUFFING  0x02
 149 #define TD_CC_DATATOGGLEM  0x03
 150 #define TD_CC_STALL        0x04
 151 #define TD_DEVNOTRESP      0x05
 152 #define TD_PIDCHECKFAIL    0x06
 153 #define TD_UNEXPECTEDPID   0x07
 154 #define TD_DATAOVERRUN     0x08
 155 #define TD_DATAUNDERRUN    0x09
 156     /* 0x0A, 0x0B reserved for hardware */
 157 #define TD_BUFFEROVERRUN   0x0C
 158 #define TD_BUFFERUNDERRUN  0x0D
 159     /* 0x0E, 0x0F reserved for HCD */
 160 #define TD_NOTACCESSED     0x0F
 161
 162
 163 /* map OHCI TD status codes (CC) to errno values */
 164 static const int cc_to_error [16] = {
 165         /* No  Error  */               0,
 166         /* CRC Error  */               -EILSEQ,
 167         /* Bit Stuff  */               -EPROTO,
 168         /* Data Togg  */               -EILSEQ,
 169         /* Stall      */               -EPIPE,
 170         /* DevNotResp */               -ETIME,
 171         /* PIDCheck   */               -EPROTO,
 172         /* UnExpPID   */               -EPROTO,
 173         /* DataOver   */               -EOVERFLOW,
 174         /* DataUnder  */               -EREMOTEIO,
 175         /* (for hw)   */               -EIO,
 176         /* (for hw)   */               -EIO,
 177         /* BufferOver */               -ECOMM,
 178         /* BuffUnder  */               -ENOSR,
 179         /* (for HCD)  */               -EALREADY,
 180         /* (for HCD)  */               -EALREADY
 181 };
 182
 183
 184 /*
 185  * The HCCA (Host Controller Communications Area) is a 256 byte
 186  * structure defined section 4.4.1 of the OHCI spec. The HC is
 187  * told the base address of it.  It must be 256-byte aligned.
 188  */
 189 struct ohci_hcca {
 190 #define NUM_INTS 32
 191         __hc32  int_table [NUM_INTS];   /* periodic schedule */
 192
 193         /*
 194          * OHCI defines u16 frame_no, followed by u16 zero pad.
 195          * Since some processors can't do 16 bit bus accesses,
 196          * portable access must be a 32 bits wide.
 197          */
 198         __hc32  frame_no;               /* current frame number */
 199         __hc32  done_head;              /* info returned for an interrupt */
 200         u8      reserved_for_hc [116];
 201         u8      what [4];               /* spec only identifies 252 bytes :) */
 202 } __attribute__ ((aligned(256)));
 203
 204 /*
 205  * This is the structure of the OHCI controller's memory mapped I/O region.
 206  * You must use readl() and writel() (in <asm/io.h>) to access these fields!!
 207  * Layout is in section 7 (and appendix B) of the spec.
 208  */
 209 struct ohci_regs {
 210         /* control and status registers (section 7.1) */
 211         __hc32  revision;
 212         __hc32  control;
 213         __hc32  cmdstatus;
 214         __hc32  intrstatus;
 215         __hc32  intrenable;
 216         __hc32  intrdisable;
 217
 218         /* memory pointers (section 7.2) */
 219         __hc32  hcca;
 220         __hc32  ed_periodcurrent;
 221         __hc32  ed_controlhead;
 222         __hc32  ed_controlcurrent;
 223         __hc32  ed_bulkhead;
 224         __hc32  ed_bulkcurrent;
 225         __hc32  donehead;
 226
 227         /* frame counters (section 7.3) */
 228         __hc32  fminterval;
 229         __hc32  fmremaining;
 230         __hc32  fmnumber;
 231         __hc32  periodicstart;
 232         __hc32  lsthresh;
 233
 234         /* Root hub ports (section 7.4) */
 235         struct  ohci_roothub_regs {
 236                 __hc32  a;
 237                 __hc32  b;
 238                 __hc32  status;
 239 #define MAX_ROOT_PORTS  15      /* maximum OHCI root hub ports (RH_A_NDP) */
 240                 __hc32  portstatus [MAX_ROOT_PORTS];
 241         } roothub;
 242
 243         /* and optional "legacy support" registers (appendix B) at 0x0100 */
 244
 245 } __attribute__ ((aligned(32)));
 246
 247
 248 /* OHCI CONTROL AND STATUS REGISTER MASKS */
 249
 250 /*
 251  * HcControl (control) register masks
 252  */
 253 #define OHCI_CTRL_CBSR  (3 << 0)        /* control/bulk service ratio */
 254 #define OHCI_CTRL_PLE   (1 << 2)        /* periodic list enable */
 255 #define OHCI_CTRL_IE    (1 << 3)        /* isochronous enable */
 256 #define OHCI_CTRL_CLE   (1 << 4)        /* control list enable */
 257 #define OHCI_CTRL_BLE   (1 << 5)        /* bulk list enable */
 258 #define OHCI_CTRL_HCFS  (3 << 6)        /* host controller functional state */
 259 #define OHCI_CTRL_IR    (1 << 8)        /* interrupt routing */
 260 #define OHCI_CTRL_RWC   (1 << 9)        /* remote wakeup connected */
 261 #define OHCI_CTRL_RWE   (1 << 10)       /* remote wakeup enable */
 262
 263 /* pre-shifted values for HCFS */
 264 #       define OHCI_USB_RESET   (0 << 6)
 265 #       define OHCI_USB_RESUME  (1 << 6)
 266 #       define OHCI_USB_OPER    (2 << 6)
 267 #       define OHCI_USB_SUSPEND (3 << 6)
 268
 269 /*
 270  * HcCommandStatus (cmdstatus) register masks
 271  */
 272 #define OHCI_HCR        (1 << 0)        /* host controller reset */
 273 #define OHCI_CLF        (1 << 1)        /* control list filled */
 274 #define OHCI_BLF        (1 << 2)        /* bulk list filled */
 275 #define OHCI_OCR        (1 << 3)        /* ownership change request */
 276 #define OHCI_SOC        (3 << 16)       /* scheduling overrun count */
 277
 278 /*
 279  * masks used with interrupt registers:
 280  * HcInterruptStatus (intrstatus)
 281  * HcInterruptEnable (intrenable)
 282  * HcInterruptDisable (intrdisable)
 283  */
 284 #define OHCI_INTR_SO    (1 << 0)        /* scheduling overrun */
 285 #define OHCI_INTR_WDH   (1 << 1)        /* writeback of done_head */
 286 #define OHCI_INTR_SF    (1 << 2)        /* start frame */
 287 #define OHCI_INTR_RD    (1 << 3)        /* resume detect */
 288 #define OHCI_INTR_UE    (1 << 4)        /* unrecoverable error */
 289 #define OHCI_INTR_FNO   (1 << 5)        /* frame number overflow */
 290 #define OHCI_INTR_RHSC  (1 << 6)        /* root hub status change */
 291 #define OHCI_INTR_OC    (1 << 30)       /* ownership change */
 292 #define OHCI_INTR_MIE   (1 << 31)       /* master interrupt enable */
 293
 294
 295 /* OHCI ROOT HUB REGISTER MASKS */
 296
 297 /* roothub.portstatus [i] bits */
 298 #define RH_PS_CCS            0x00000001         /* current connect status */
 299 #define RH_PS_PES            0x00000002         /* port enable status*/
 300 #define RH_PS_PSS            0x00000004         /* port suspend status */
 301 #define RH_PS_POCI           0x00000008         /* port over current indicator */
 302 #define RH_PS_PRS            0x00000010         /* port reset status */
 303 #define RH_PS_PPS            0x00000100         /* port power status */
 304 #define RH_PS_LSDA           0x00000200         /* low speed device attached */
 305 #define RH_PS_CSC            0x00010000         /* connect status change */
 306 #define RH_PS_PESC           0x00020000         /* port enable status change */
 307 #define RH_PS_PSSC           0x00040000         /* port suspend status change */
 308 #define RH_PS_OCIC           0x00080000         /* over current indicator change */
 309 #define RH_PS_PRSC           0x00100000         /* port reset status change */
 310
 311 /* roothub.status bits */
 312 #define RH_HS_LPS            0x00000001         /* local power status */
 313 #define RH_HS_OCI            0x00000002         /* over current indicator */
 314 #define RH_HS_DRWE           0x00008000         /* device remote wakeup enable */
 315 #define RH_HS_LPSC           0x00010000         /* local power status change */
 316 #define RH_HS_OCIC           0x00020000         /* over current indicator change */
 317 #define RH_HS_CRWE           0x80000000         /* clear remote wakeup enable */
 318
 319 /* roothub.b masks */
 320 #define RH_B_DR         0x0000ffff              /* device removable flags */
 321 #define RH_B_PPCM       0xffff0000              /* port power control mask */
 322
 323 /* roothub.a masks */
 324 #define RH_A_NDP        (0xff << 0)             /* number of downstream ports */
 325 #define RH_A_PSM        (1 << 8)                /* power switching mode */
 326 #define RH_A_NPS        (1 << 9)                /* no power switching */
 327 #define RH_A_DT         (1 << 10)               /* device type (mbz) */
 328 #define RH_A_OCPM       (1 << 11)               /* over current protection mode */
 329 #define RH_A_NOCP       (1 << 12)               /* no over current protection */
 330 #define RH_A_POTPGT     (0xff << 24)            /* power on to power good time */
 331
 332
 333 /* hcd-private per-urb state */
 334 typedef struct urb_priv {
 335         struct ed               *ed;
 336         u16                     length;         // # tds in this request
 337         u16                     td_cnt;         // tds already serviced
 338         struct list_head        pending;
 339         struct td               *td [0];        // all TDs in this request
 340
 341 } urb_priv_t;
 342
 343 #define TD_HASH_SIZE    64    /* power'o'two */
 344 // sizeof (struct td) ~= 64 == 2^6 ...
 345 #define TD_HASH_FUNC(td_dma) ((td_dma ^ (td_dma >> 6)) % TD_HASH_SIZE)
 346
 347
 348 /*
 349  * This is the full ohci controller description
 350  *
 351  * Note how the "proper" USB information is just
 352  * a subset of what the full implementation needs. (Linus)
 353  */
 354
 355 enum ohci_rh_state {
 356         OHCI_RH_HALTED,
 357         OHCI_RH_SUSPENDED,
 358         OHCI_RH_RUNNING
 359 };
 360
 361 struct ohci_hcd {
 362         spinlock_t              lock;
 363
 364         /*
 365          * I/O memory used to communicate with the HC (dma-consistent)
 366          */
 367         struct ohci_regs __iomem *regs;
 368
 369         /*
 370          * main memory used to communicate with the HC (dma-consistent).
 371          * hcd adds to schedule for a live hc any time, but removals finish
 372          * only at the start of the next frame.
 373          */
 374         struct ohci_hcca        *hcca;
 375         dma_addr_t              hcca_dma;
 376
 377         struct ed               *ed_rm_list;            /* to be removed */
 378
 379         struct ed               *ed_bulktail;           /* last in bulk list */
 380         struct ed               *ed_controltail;        /* last in ctrl list */
 381         struct ed               *periodic [NUM_INTS];   /* shadow int_table */
 382
 383         void (*start_hnp)(struct ohci_hcd *ohci);
 384
 385         /*
 386          * memory management for queue data structures
 387          */
 388         struct dma_pool         *td_cache;
 389         struct dma_pool         *ed_cache;
 390         struct td               *td_hash [TD_HASH_SIZE];
 391         struct td               *dl_start, *dl_end;     /* the done list */
 392         struct list_head        pending;
 393         struct list_head        eds_in_use;     /* all EDs with at least 1 TD */
 394
 395         /*
 396          * driver state
 397          */
 398         enum ohci_rh_state      rh_state;
 399         int                     num_ports;
 400         int                     load [NUM_INTS];
 401         u32                     hc_control;     /* copy of hc control reg */
 402         unsigned long           next_statechange;       /* suspend/resume */
 403         u32                     fminterval;             /* saved register */
 404         unsigned                autostop:1;     /* rh auto stopping/stopped */
 405         unsigned                working:1;
 406         unsigned                restart_work:1;
 407
 408         unsigned long           flags;          /* for HC bugs */
 409 #define OHCI_QUIRK_AMD756       0x01                    /* erratum #4 */
 410 #define OHCI_QUIRK_SUPERIO      0x02                    /* natsemi */
 411 #define OHCI_QUIRK_INITRESET    0x04                    /* SiS, OPTi, ... */
 412 #define OHCI_QUIRK_BE_DESC      0x08                    /* BE descriptors */
 413 #define OHCI_QUIRK_BE_MMIO      0x10                    /* BE registers */
 414 #define OHCI_QUIRK_ZFMICRO      0x20                    /* Compaq ZFMicro chipset*/
 415 #define OHCI_QUIRK_NEC          0x40                    /* lost interrupts */
 416 #define OHCI_QUIRK_FRAME_NO     0x80                    /* no big endian frame_no shift */
 417 #define OHCI_QUIRK_HUB_POWER    0x100                   /* distrust firmware power/oc setup */
 418 #define OHCI_QUIRK_AMD_PLL      0x200                   /* AMD PLL quirk*/
 419 #define OHCI_QUIRK_AMD_PREFETCH 0x400                   /* pre-fetch for ISO transfer */
 420 #define OHCI_QUIRK_GLOBAL_SUSPEND       0x800           /* must suspend ports */
 421 #define OHCI_QUIRK_QEMU         0x1000                  /* relax timing expectations */
 422
 423         // there are also chip quirks/bugs in init logic
 424
 425         unsigned                prev_frame_no;
 426         unsigned                wdh_cnt, prev_wdh_cnt;
 427         u32                     prev_donehead;
 428         struct timer_list       io_watchdog;
 429
 430         struct work_struct      nec_work;       /* Worker for NEC quirk */
 431
 432         struct dentry           *debug_dir;
 433         struct dentry           *debug_async;
 434         struct dentry           *debug_periodic;
 435         struct dentry           *debug_registers;
 436
 437         /* platform-specific data -- must come last */
 438         unsigned long           priv[0] __aligned(sizeof(s64));
 439
 440 };
 441
 442 #ifdef CONFIG_PCI
 443 static inline int quirk_nec(struct ohci_hcd *ohci)
 444 {
 445         return ohci->flags & OHCI_QUIRK_NEC;
 446 }
 447 static inline int quirk_zfmicro(struct ohci_hcd *ohci)
 448 {
 449         return ohci->flags & OHCI_QUIRK_ZFMICRO;
 450 }
 451 static inline int quirk_amdiso(struct ohci_hcd *ohci)
 452 {
 453         return ohci->flags & OHCI_QUIRK_AMD_PLL;
 454 }
 455 static inline int quirk_amdprefetch(struct ohci_hcd *ohci)
 456 {
 457         return ohci->flags & OHCI_QUIRK_AMD_PREFETCH;
 458 }
 459 #else
 460 static inline int quirk_nec(struct ohci_hcd *ohci)
 461 {
 462         return 0;
 463 }
 464 static inline int quirk_zfmicro(struct ohci_hcd *ohci)
 465 {
 466         return 0;
 467 }
 468 static inline int quirk_amdiso(struct ohci_hcd *ohci)
 469 {
 470         return 0;
 471 }
 472 static inline int quirk_amdprefetch(struct ohci_hcd *ohci)
 473 {
 474         return 0;
 475 }
 476 #endif
 477
 478 /* convert between an hcd pointer and the corresponding ohci_hcd */
 479 static inline struct ohci_hcd *hcd_to_ohci (struct usb_hcd *hcd)
 480 {
 481         return (struct ohci_hcd *) (hcd->hcd_priv);
 482 }
 483 static inline struct usb_hcd *ohci_to_hcd (const struct ohci_hcd *ohci)
 484 {
 485         return container_of ((void *) ohci, struct usb_hcd, hcd_priv);
 486 }
 487
 488 /*-------------------------------------------------------------------------*/
 489
 490 #define ohci_dbg(ohci, fmt, args...) \
 491         dev_dbg (ohci_to_hcd(ohci)->self.controller , fmt , ## args )
 492 #define ohci_err(ohci, fmt, args...) \
 493         dev_err (ohci_to_hcd(ohci)->self.controller , fmt , ## args )
 494 #define ohci_info(ohci, fmt, args...) \
 495         dev_info (ohci_to_hcd(ohci)->self.controller , fmt , ## args )
 496 #define ohci_warn(ohci, fmt, args...) \
 497         dev_warn (ohci_to_hcd(ohci)->self.controller , fmt , ## args )
 498
 499 /*-------------------------------------------------------------------------*/
 500
 501 /*
 502  * While most USB host controllers implement their registers and
 503  * in-memory communication descriptors in little-endian format,
 504  * a minority (notably the IBM STB04XXX and the Motorola MPC5200
 505  * processors) implement them in big endian format.
 506  *
 507  * In addition some more exotic implementations like the Toshiba
 508  * Spider (aka SCC) cell southbridge are "mixed" endian, that is,
 509  * they have a different endianness for registers vs. in-memory
 510  * descriptors.
 511  *
 512  * This attempts to support either format at compile time without a
 513  * runtime penalty, or both formats with the additional overhead
 514  * of checking a flag bit.
 515  *
 516  * That leads to some tricky Kconfig rules howevber. There are
 517  * different defaults based on some arch/ppc platforms, though
 518  * the basic rules are:
 519  *
 520  * Controller type              Kconfig options needed
 521  * ---------------              ----------------------
 522  * little endian                CONFIG_USB_OHCI_LITTLE_ENDIAN
 523  *
 524  * fully big endian             CONFIG_USB_OHCI_BIG_ENDIAN_DESC _and_
 525  *                              CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
 526  *
 527  * mixed endian                 CONFIG_USB_OHCI_LITTLE_ENDIAN _and_
 528  *                              CONFIG_USB_OHCI_BIG_ENDIAN_{MMIO,DESC}
 529  *
 530  * (If you have a mixed endian controller, you -must- also define
 531  * CONFIG_USB_OHCI_LITTLE_ENDIAN or things will not work when building
 532  * both your mixed endian and a fully big endian controller support in
 533  * the same kernel image).
 534  */
 535
 536 #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_DESC
 537 #ifdef CONFIG_USB_OHCI_LITTLE_ENDIAN
 538 #define big_endian_desc(ohci)   (ohci->flags & OHCI_QUIRK_BE_DESC)
 539 #else
 540 #define big_endian_desc(ohci)   1               /* only big endian */
 541 #endif
 542 #else
 543 #define big_endian_desc(ohci)   0               /* only little endian */
 544 #endif
 545
 546 #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
 547 #ifdef CONFIG_USB_OHCI_LITTLE_ENDIAN
 548 #define big_endian_mmio(ohci)   (ohci->flags & OHCI_QUIRK_BE_MMIO)
 549 #else
 550 #define big_endian_mmio(ohci)   1               /* only big endian */
 551 #endif
 552 #else
 553 #define big_endian_mmio(ohci)   0               /* only little endian */
 554 #endif
 555
 556 /*
 557  * Big-endian read/write functions are arch-specific.
 558  * Other arches can be added if/when they're needed.
 559  *
 560  */
 561 static inline unsigned int _ohci_readl (const struct ohci_hcd *ohci,
 562                                         __hc32 __iomem * regs)
 563 {
 564 #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
 565         return big_endian_mmio(ohci) ?
 566                 readl_be (regs) :
 567                 readl (regs);
 568 #else
 569         return readl (regs);
 570 #endif
 571 }
 572
 573 static inline void _ohci_writel (const struct ohci_hcd *ohci,
 574                                  const unsigned int val, __hc32 __iomem *regs)
 575 {
 576 #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
 577         big_endian_mmio(ohci) ?
 578                 writel_be (val, regs) :
 579                 writel (val, regs);
 580 #else
 581                 writel (val, regs);
 582 #endif
 583 }
 584
 585 #define ohci_readl(o,r)         _ohci_readl(o,r)
 586 #define ohci_writel(o,v,r)      _ohci_writel(o,v,r)
 587
 588
 589 /*-------------------------------------------------------------------------*/
 590
 591 /* cpu to ohci */
 592 static inline __hc16 cpu_to_hc16 (const struct ohci_hcd *ohci, const u16 x)
 593 {
 594         return big_endian_desc(ohci) ?
 595                 (__force __hc16)cpu_to_be16(x) :
 596                 (__force __hc16)cpu_to_le16(x);
 597 }
 598
 599 static inline __hc16 cpu_to_hc16p (const struct ohci_hcd *ohci, const u16 *x)
 600 {
 601         return big_endian_desc(ohci) ?
 602                 cpu_to_be16p(x) :
 603                 cpu_to_le16p(x);
 604 }
 605
 606 static inline __hc32 cpu_to_hc32 (const struct ohci_hcd *ohci, const u32 x)
 607 {
 608         return big_endian_desc(ohci) ?
 609                 (__force __hc32)cpu_to_be32(x) :
 610                 (__force __hc32)cpu_to_le32(x);
 611 }
 612
 613 static inline __hc32 cpu_to_hc32p (const struct ohci_hcd *ohci, const u32 *x)
 614 {
 615         return big_endian_desc(ohci) ?
 616                 cpu_to_be32p(x) :
 617                 cpu_to_le32p(x);
 618 }
 619
 620 /* ohci to cpu */
 621 static inline u16 hc16_to_cpu (const struct ohci_hcd *ohci, const __hc16 x)
 622 {
 623         return big_endian_desc(ohci) ?
 624                 be16_to_cpu((__force __be16)x) :
 625                 le16_to_cpu((__force __le16)x);
 626 }
 627
 628 static inline u16 hc16_to_cpup (const struct ohci_hcd *ohci, const __hc16 *x)
 629 {
 630         return big_endian_desc(ohci) ?
 631                 be16_to_cpup((__force __be16 *)x) :
 632                 le16_to_cpup((__force __le16 *)x);
 633 }
 634
 635 static inline u32 hc32_to_cpu (const struct ohci_hcd *ohci, const __hc32 x)
 636 {
 637         return big_endian_desc(ohci) ?
 638                 be32_to_cpu((__force __be32)x) :
 639                 le32_to_cpu((__force __le32)x);
 640 }
 641
 642 static inline u32 hc32_to_cpup (const struct ohci_hcd *ohci, const __hc32 *x)
 643 {
 644         return big_endian_desc(ohci) ?
 645                 be32_to_cpup((__force __be32 *)x) :
 646                 le32_to_cpup((__force __le32 *)x);
 647 }
 648
 649 /*-------------------------------------------------------------------------*/
 650
 651 /*
 652  * The HCCA frame number is 16 bits, but is accessed as 32 bits since not all
 653  * hardware handles 16 bit reads.  Depending on the SoC implementation, the
 654  * frame number can wind up in either bits [31:16] (default) or
 655  * [15:0] (OHCI_QUIRK_FRAME_NO) on big endian hosts.
 656  *
 657  * Somewhat similarly, the 16-bit PSW fields in a transfer descriptor are
 658  * reordered on BE.
 659  */
 660
 661 static inline u16 ohci_frame_no(const struct ohci_hcd *ohci)
 662 {
 663         u32 tmp;
 664         if (big_endian_desc(ohci)) {
 665                 tmp = be32_to_cpup((__force __be32 *)&ohci->hcca->frame_no);
 666                 if (!(ohci->flags & OHCI_QUIRK_FRAME_NO))
 667                         tmp >>= 16;
 668         } else
 669                 tmp = le32_to_cpup((__force __le32 *)&ohci->hcca->frame_no);
 670
 671         return (u16)tmp;
 672 }
 673
 674 static inline __hc16 *ohci_hwPSWp(const struct ohci_hcd *ohci,
 675                                  const struct td *td, int index)
 676 {
 677         return (__hc16 *)(big_endian_desc(ohci) ?
 678                         &td->hwPSW[index ^ 1] : &td->hwPSW[index]);
 679 }
 680
 681 static inline u16 ohci_hwPSW(const struct ohci_hcd *ohci,
 682                                const struct td *td, int index)
 683 {
 684         return hc16_to_cpup(ohci, ohci_hwPSWp(ohci, td, index));
 685 }
 686
 687 /*-------------------------------------------------------------------------*/
 688
 689 #define FI                      0x2edf          /* 12000 bits per frame (-1) */
 690 #define FSMP(fi)                (0x7fff & ((6 * ((fi) - 210)) / 7))
 691 #define FIT                     (1 << 31)
 692 #define LSTHRESH                0x628           /* lowspeed bit threshold */
 693
 694 static inline void periodic_reinit (struct ohci_hcd *ohci)
 695 {
 696         u32     fi = ohci->fminterval & 0x03fff;
 697         u32     fit = ohci_readl(ohci, &ohci->regs->fminterval) & FIT;
 698
 699         ohci_writel (ohci, (fit ^ FIT) | ohci->fminterval,
 700                                                 &ohci->regs->fminterval);
 701         ohci_writel (ohci, ((9 * fi) / 10) & 0x3fff,
 702                                                 &ohci->regs->periodicstart);
 703 }
 704
 705 /* AMD-756 (D2 rev) reports corrupt register contents in some cases.
 706  * The erratum (#4) description is incorrect.  AMD's workaround waits
 707  * till some bits (mostly reserved) are clear; ok for all revs.
 708  */
 709 #define read_roothub(hc, register, mask) ({ \
 710         u32 temp = ohci_readl (hc, &hc->regs->roothub.register); \
 711         if (temp == -1) \
 712                 hc->rh_state = OHCI_RH_HALTED; \
 713         else if (hc->flags & OHCI_QUIRK_AMD756) \
 714                 while (temp & mask) \
 715                         temp = ohci_readl (hc, &hc->regs->roothub.register); \
 716         temp; })
 717
 718 static inline u32 roothub_a (struct ohci_hcd *hc)
 719         { return read_roothub (hc, a, 0xfc0fe000); }
 720 static inline u32 roothub_b (struct ohci_hcd *hc)
 721         { return ohci_readl (hc, &hc->regs->roothub.b); }
 722 static inline u32 roothub_status (struct ohci_hcd *hc)
 723         { return ohci_readl (hc, &hc->regs->roothub.status); }
 724 static inline u32 roothub_portstatus (struct ohci_hcd *hc, int i)
 725         { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
 726
 727 /* Declarations of things exported for use by ohci platform drivers */
 728
 729 struct ohci_driver_overrides {
 730         const char      *product_desc;
 731         size_t          extra_priv_size;
 732         int             (*reset)(struct usb_hcd *hcd);
 733 };
 734
 735 extern void     ohci_init_driver(struct hc_driver *drv,
 736                                 const struct ohci_driver_overrides *over);
 737 extern int      ohci_restart(struct ohci_hcd *ohci);
 738 extern int      ohci_setup(struct usb_hcd *hcd);
 739 extern int      ohci_suspend(struct usb_hcd *hcd, bool do_wakeup);
 740 extern int      ohci_resume(struct usb_hcd *hcd, bool hibernated);
 741 extern int      ohci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
 742                                  u16 wIndex, char *buf, u16 wLength);
 743 extern int      ohci_hub_status_data(struct usb_hcd *hcd, char *buf);