drivers/usb/host/xhci-pci.c

   1 /*
   2  * xHCI host controller driver PCI Bus Glue.
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/pci.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/acpi.h>
  27
  28 #include "xhci.h"
  29 #include "xhci-trace.h"
  30
  31 #define SSIC_PORT_NUM           2
  32 #define SSIC_PORT_CFG2          0x880c
  33 #define SSIC_PORT_CFG2_OFFSET   0x30
  34 #define PROG_DONE               (1 << 30)
  35 #define SSIC_PORT_UNUSED        (1 << 31)
  36
  37 /* Device for a quirk */
  38 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  39 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  40 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009       0x1009
  41 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  42
  43 #define PCI_VENDOR_ID_ETRON             0x1b6f
  44 #define PCI_DEVICE_ID_EJ168             0x7023
  45
  46 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  47 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  48 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI        0x9cb1
  49 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  50 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  51 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  52 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  53 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
  54 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
  55 #define PCI_DEVICE_ID_INTEL_DNV_XHCI                    0x19d0
  56
  57 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI                0x1142
  58
  59 static const char hcd_name[] = "xhci_hcd";
  60
  61 static struct hc_driver __read_mostly xhci_pci_hc_driver;
  62
  63 static int xhci_pci_setup(struct usb_hcd *hcd);
  64
  65 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  66         .reset = xhci_pci_setup,
  67 };
  68
  69 /* called after powerup, by probe or system-pm "wakeup" */
  70 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  71 {
  72         /*
  73          * TODO: Implement finding debug ports later.
  74          * TODO: see if there are any quirks that need to be added to handle
  75          * new extended capabilities.
  76          */
  77
  78         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  79         if (!pci_set_mwi(pdev))
  80                 xhci_dbg(xhci, "MWI active\n");
  81
  82         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  83         return 0;
  84 }
  85
  86 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
  87 {
  88         struct pci_dev          *pdev = to_pci_dev(dev);
  89
  90         /* Look for vendor-specific quirks */
  91         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
  92                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
  93                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
  94                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  95                                 pdev->revision == 0x0) {
  96                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
  97                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  98                                 "QUIRK: Fresco Logic xHC needs configure"
  99                                 " endpoint cmd after reset endpoint");
 100                 }
 101                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 102                                 pdev->revision == 0x4) {
 103                         xhci->quirks |= XHCI_SLOW_SUSPEND;
 104                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 105                                 "QUIRK: Fresco Logic xHC revision %u"
 106                                 "must be suspended extra slowly",
 107                                 pdev->revision);
 108                 }
 109                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
 110                         xhci->quirks |= XHCI_BROKEN_STREAMS;
 111                 /* Fresco Logic confirms: all revisions of this chip do not
 112                  * support MSI, even though some of them claim to in their PCI
 113                  * capabilities.
 114                  */
 115                 xhci->quirks |= XHCI_BROKEN_MSI;
 116                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 117                                 "QUIRK: Fresco Logic revision %u "
 118                                 "has broken MSI implementation",
 119                                 pdev->revision);
 120                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 121         }
 122
 123         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 124                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
 125                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 126
 127         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 128                 xhci->quirks |= XHCI_NEC_HOST;
 129
 130         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 131                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 132
 133         /* AMD PLL quirk */
 134         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
 135                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 136
 137         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 138                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 139
 140         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 141                 xhci->quirks |= XHCI_LPM_SUPPORT;
 142                 xhci->quirks |= XHCI_INTEL_HOST;
 143                 xhci->quirks |= XHCI_AVOID_BEI;
 144         }
 145         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 146                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 147                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 148                 xhci->limit_active_eps = 64;
 149                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 150                 /*
 151                  * PPT desktop boards DH77EB and DH77DF will power back on after
 152                  * a few seconds of being shutdown.  The fix for this is to
 153                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 154                  * DMI information to find those particular boards (since each
 155                  * vendor will change the board name), so we have to key off all
 156                  * PPT chipsets.
 157                  */
 158                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 159         }
 160         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 161                 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
 162                  pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
 163                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 164                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 165         }
 166         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 167                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 168                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 169                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 170                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
 171                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
 172                  pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 173                  pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) {
 174                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 175         }
 176         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 177                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
 178                 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
 179         }
 180         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 181             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 182              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 183              pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
 184                 xhci->quirks |= XHCI_MISSING_CAS;
 185
 186         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 187                         pdev->device == PCI_DEVICE_ID_EJ168) {
 188                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 189                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 190                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 191         }
 192         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 193                         pdev->device == 0x0014)
 194                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 195         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 196                         pdev->device == 0x0015)
 197                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 198         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 199                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 200
 201         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 202         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 203                         pdev->device == 0x3432)
 204                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 205
 206         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 207                         pdev->device == 0x1042)
 208                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 209         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 210                         pdev->device == 0x1142)
 211                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 212
 213         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 214                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
 215                 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
 216
 217         if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
 218                 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
 219
 220         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 221                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 222                                 "QUIRK: Resetting on resume");
 223 }
 224
 225 #ifdef CONFIG_ACPI
 226 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
 227 {
 228         static const u8 intel_dsm_uuid[] = {
 229                 0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0xbf, 0x45,
 230                 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23,
 231         };
 232         union acpi_object *obj;
 233
 234         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), intel_dsm_uuid, 3, 1,
 235                                 NULL);
 236         ACPI_FREE(obj);
 237 }
 238 #else
 239 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
 240 #endif /* CONFIG_ACPI */
 241
 242 /* called during probe() after chip reset completes */
 243 static int xhci_pci_setup(struct usb_hcd *hcd)
 244 {
 245         struct xhci_hcd         *xhci;
 246         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 247         int                     retval;
 248
 249         xhci = hcd_to_xhci(hcd);
 250         if (!xhci->sbrn)
 251                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 252
 253         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 254         if (retval)
 255                 return retval;
 256
 257         if (!usb_hcd_is_primary_hcd(hcd))
 258                 return 0;
 259
 260         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 261
 262         /* Find any debug ports */
 263         retval = xhci_pci_reinit(xhci, pdev);
 264         if (!retval)
 265                 return retval;
 266
 267         return retval;
 268 }
 269
 270 /*
 271  * We need to register our own PCI probe function (instead of the USB core's
 272  * function) in order to create a second roothub under xHCI.
 273  */
 274 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 275 {
 276         int retval;
 277         struct xhci_hcd *xhci;
 278         struct hc_driver *driver;
 279         struct usb_hcd *hcd;
 280
 281         driver = (struct hc_driver *)id->driver_data;
 282
 283         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 284         pm_runtime_get_noresume(&dev->dev);
 285
 286         /* Register the USB 2.0 roothub.
 287          * FIXME: USB core must know to register the USB 2.0 roothub first.
 288          * This is sort of silly, because we could just set the HCD driver flags
 289          * to say USB 2.0, but I'm not sure what the implications would be in
 290          * the other parts of the HCD code.
 291          */
 292         retval = usb_hcd_pci_probe(dev, id);
 293
 294         if (retval)
 295                 goto put_runtime_pm;
 296
 297         /* USB 2.0 roothub is stored in the PCI device now. */
 298         hcd = dev_get_drvdata(&dev->dev);
 299         xhci = hcd_to_xhci(hcd);
 300         xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
 301                                 pci_name(dev), hcd);
 302         if (!xhci->shared_hcd) {
 303                 retval = -ENOMEM;
 304                 goto dealloc_usb2_hcd;
 305         }
 306
 307         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 308                         IRQF_SHARED);
 309         if (retval)
 310                 goto put_usb3_hcd;
 311         /* Roothub already marked as USB 3.0 speed */
 312
 313         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 314                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 315                 xhci->shared_hcd->can_do_streams = 1;
 316
 317         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 318                 xhci_pme_acpi_rtd3_enable(dev);
 319
 320         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 321         pm_runtime_put_noidle(&dev->dev);
 322
 323         return 0;
 324
 325 put_usb3_hcd:
 326         usb_put_hcd(xhci->shared_hcd);
 327 dealloc_usb2_hcd:
 328         usb_hcd_pci_remove(dev);
 329 put_runtime_pm:
 330         pm_runtime_put_noidle(&dev->dev);
 331         return retval;
 332 }
 333
 334 static void xhci_pci_remove(struct pci_dev *dev)
 335 {
 336         struct xhci_hcd *xhci;
 337
 338         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 339         xhci->xhc_state |= XHCI_STATE_REMOVING;
 340         if (xhci->shared_hcd) {
 341                 usb_remove_hcd(xhci->shared_hcd);
 342                 usb_put_hcd(xhci->shared_hcd);
 343         }
 344
 345         /* Workaround for spurious wakeups at shutdown with HSW */
 346         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 347                 pci_set_power_state(dev, PCI_D3hot);
 348
 349         usb_hcd_pci_remove(dev);
 350 }
 351
 352 #ifdef CONFIG_PM
 353 /*
 354  * In some Intel xHCI controllers, in order to get D3 working,
 355  * through a vendor specific SSIC CONFIG register at offset 0x883c,
 356  * SSIC PORT need to be marked as "unused" before putting xHCI
 357  * into D3. After D3 exit, the SSIC port need to be marked as "used".
 358  * Without this change, xHCI might not enter D3 state.
 359  */
 360 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
 361 {
 362         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 363         u32 val;
 364         void __iomem *reg;
 365         int i;
 366
 367         for (i = 0; i < SSIC_PORT_NUM; i++) {
 368                 reg = (void __iomem *) xhci->cap_regs +
 369                                 SSIC_PORT_CFG2 +
 370                                 i * SSIC_PORT_CFG2_OFFSET;
 371
 372                 /* Notify SSIC that SSIC profile programming is not done. */
 373                 val = readl(reg) & ~PROG_DONE;
 374                 writel(val, reg);
 375
 376                 /* Mark SSIC port as unused(suspend) or used(resume) */
 377                 val = readl(reg);
 378                 if (suspend)
 379                         val |= SSIC_PORT_UNUSED;
 380                 else
 381                         val &= ~SSIC_PORT_UNUSED;
 382                 writel(val, reg);
 383
 384                 /* Notify SSIC that SSIC profile programming is done */
 385                 val = readl(reg) | PROG_DONE;
 386                 writel(val, reg);
 387                 readl(reg);
 388         }
 389 }
 390
 391 /*
 392  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 393  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 394  */
 395 static void xhci_pme_quirk(struct usb_hcd *hcd)
 396 {
 397         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 398         void __iomem *reg;
 399         u32 val;
 400
 401         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 402         val = readl(reg);
 403         writel(val | BIT(28), reg);
 404         readl(reg);
 405 }
 406
 407 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 408 {
 409         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 410         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 411         int                     ret;
 412
 413         /*
 414          * Systems with the TI redriver that loses port status change events
 415          * need to have the registers polled during D3, so avoid D3cold.
 416          */
 417         if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
 418                 pci_d3cold_disable(pdev);
 419
 420         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 421                 xhci_pme_quirk(hcd);
 422
 423         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 424                 xhci_ssic_port_unused_quirk(hcd, true);
 425
 426         ret = xhci_suspend(xhci, do_wakeup);
 427         if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
 428                 xhci_ssic_port_unused_quirk(hcd, false);
 429
 430         return ret;
 431 }
 432
 433 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 434 {
 435         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 436         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 437         int                     retval = 0;
 438
 439         /* The BIOS on systems with the Intel Panther Point chipset may or may
 440          * not support xHCI natively.  That means that during system resume, it
 441          * may switch the ports back to EHCI so that users can use their
 442          * keyboard to select a kernel from GRUB after resume from hibernate.
 443          *
 444          * The BIOS is supposed to remember whether the OS had xHCI ports
 445          * enabled before resume, and switch the ports back to xHCI when the
 446          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 447          * writers.
 448          *
 449          * Unconditionally switch the ports back to xHCI after a system resume.
 450          * It should not matter whether the EHCI or xHCI controller is
 451          * resumed first. It's enough to do the switchover in xHCI because
 452          * USB core won't notice anything as the hub driver doesn't start
 453          * running again until after all the devices (including both EHCI and
 454          * xHCI host controllers) have been resumed.
 455          */
 456
 457         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 458                 usb_enable_intel_xhci_ports(pdev);
 459
 460         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 461                 xhci_ssic_port_unused_quirk(hcd, false);
 462
 463         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 464                 xhci_pme_quirk(hcd);
 465
 466         retval = xhci_resume(xhci, hibernated);
 467         return retval;
 468 }
 469 #endif /* CONFIG_PM */
 470
 471 /*-------------------------------------------------------------------------*/
 472
 473 /* PCI driver selection metadata; PCI hotplugging uses this */
 474 static const struct pci_device_id pci_ids[] = { {
 475         /* handle any USB 3.0 xHCI controller */
 476         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 477         .driver_data =  (unsigned long) &xhci_pci_hc_driver,
 478         },
 479         { /* end: all zeroes */ }
 480 };
 481 MODULE_DEVICE_TABLE(pci, pci_ids);
 482
 483 /* pci driver glue; this is a "new style" PCI driver module */
 484 static struct pci_driver xhci_pci_driver = {
 485         .name =         (char *) hcd_name,
 486         .id_table =     pci_ids,
 487
 488         .probe =        xhci_pci_probe,
 489         .remove =       xhci_pci_remove,
 490         /* suspend and resume implemented later */
 491
 492         .shutdown =     usb_hcd_pci_shutdown,
 493 #ifdef CONFIG_PM
 494         .driver = {
 495                 .pm = &usb_hcd_pci_pm_ops
 496         },
 497 #endif
 498 };
 499
 500 static int __init xhci_pci_init(void)
 501 {
 502         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
 503 #ifdef CONFIG_PM
 504         xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
 505         xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
 506 #endif
 507         return pci_register_driver(&xhci_pci_driver);
 508 }
 509 module_init(xhci_pci_init);
 510
 511 static void __exit xhci_pci_exit(void)
 512 {
 513         pci_unregister_driver(&xhci_pci_driver);
 514 }
 515 module_exit(xhci_pci_exit);
 516
 517 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
 518 MODULE_LICENSE("GPL");