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[PATCH] skge: increase receive flush threshold default
[linux/fpc-iii.git] / drivers / net / skge.c
blob38fc66a1e14cd0f19aeaebcec415c8c4d0dbde43
1 /*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27 #include <linux/config.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/if_vlan.h>
36 #include <linux/ip.h>
37 #include <linux/delay.h>
38 #include <linux/crc32.h>
39 #include <linux/dma-mapping.h>
40 #include <asm/irq.h>
41
42 #include "skge.h"
43
44 #define DRV_NAME "skge"
45 #define DRV_VERSION "0.8"
46 #define PFX DRV_NAME " "
47
48 #define DEFAULT_TX_RING_SIZE 128
49 #define DEFAULT_RX_RING_SIZE 512
50 #define MAX_TX_RING_SIZE 1024
51 #define MAX_RX_RING_SIZE 4096
52 #define RX_COPY_THRESHOLD 128
53 #define RX_BUF_SIZE 1536
54 #define PHY_RETRIES 1000
55 #define ETH_JUMBO_MTU 9000
56 #define TX_WATCHDOG (5 * HZ)
57 #define NAPI_WEIGHT 64
58 #define BLINK_MS 250
59
60 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
61 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
62 MODULE_LICENSE("GPL");
63 MODULE_VERSION(DRV_VERSION);
64
65 static const u32 default_msg
66 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
67 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
68
69 static int debug = -1; /* defaults above */
70 module_param(debug, int, 0);
71 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
72
73 static const struct pci_device_id skge_id_table[] = {
74 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
75 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
76 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
77 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
78 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
79 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
80 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
81 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
82 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1032) },
83 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
84 { 0 }
85 };
86 MODULE_DEVICE_TABLE(pci, skge_id_table);
87
88 static int skge_up(struct net_device *dev);
89 static int skge_down(struct net_device *dev);
90 static void skge_tx_clean(struct skge_port *skge);
91 static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
92 static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
93 static void genesis_get_stats(struct skge_port *skge, u64 *data);
94 static void yukon_get_stats(struct skge_port *skge, u64 *data);
95 static void yukon_init(struct skge_hw *hw, int port);
96 static void yukon_reset(struct skge_hw *hw, int port);
97 static void genesis_mac_init(struct skge_hw *hw, int port);
98 static void genesis_reset(struct skge_hw *hw, int port);
99 static void genesis_link_up(struct skge_port *skge);
100
101 /* Avoid conditionals by using array */
102 static const int txqaddr[] = { Q_XA1, Q_XA2 };
103 static const int rxqaddr[] = { Q_R1, Q_R2 };
104 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
105 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
106 static const u32 portirqmask[] = { IS_PORT_1, IS_PORT_2 };
107
108 /* Don't need to look at whole 16K.
109 * last interesting register is descriptor poll timer.
110 */
111 #define SKGE_REGS_LEN (29*128)
112
113 static int skge_get_regs_len(struct net_device *dev)
114 {
115 return SKGE_REGS_LEN;
116 }
117
118 /*
119 * Returns copy of control register region
120 * I/O region is divided into banks and certain regions are unreadable
121 */
122 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
123 void *p)
124 {
125 const struct skge_port *skge = netdev_priv(dev);
126 unsigned long offs;
127 const void __iomem *io = skge->hw->regs;
128 static const unsigned long bankmap
129 = (1<<0) | (1<<2) | (1<<8) | (1<<9)
130 | (1<<12) | (1<<13) | (1<<14) | (1<<15) | (1<<16)
131 | (1<<17) | (1<<20) | (1<<21) | (1<<22) | (1<<23)
132 | (1<<24) | (1<<25) | (1<<26) | (1<<27) | (1<<28);
133
134 regs->version = 1;
135 for (offs = 0; offs < regs->len; offs += 128) {
136 u32 len = min_t(u32, 128, regs->len - offs);
137
138 if (bankmap & (1<<(offs/128)))
139 memcpy_fromio(p + offs, io + offs, len);
140 else
141 memset(p + offs, 0, len);
142 }
143 }
144
145 /* Wake on Lan only supported on Yukon chps with rev 1 or above */
146 static int wol_supported(const struct skge_hw *hw)
147 {
148 return !((hw->chip_id == CHIP_ID_GENESIS ||
149 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
150 }
151
152 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
153 {
154 struct skge_port *skge = netdev_priv(dev);
155
156 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
157 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
158 }
159
160 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
161 {
162 struct skge_port *skge = netdev_priv(dev);
163 struct skge_hw *hw = skge->hw;
164
165 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
166 return -EOPNOTSUPP;
167
168 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
169 return -EOPNOTSUPP;
170
171 skge->wol = wol->wolopts == WAKE_MAGIC;
172
173 if (skge->wol) {
174 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
175
176 skge_write16(hw, WOL_CTRL_STAT,
177 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
178 WOL_CTL_ENA_MAGIC_PKT_UNIT);
179 } else
180 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
181
182 return 0;
183 }
184
185 /* Determine supported/adverised modes based on hardware.
186 * Note: ethtoool ADVERTISED_xxx == SUPPORTED_xxx
187 */
188 static u32 skge_supported_modes(const struct skge_hw *hw)
189 {
190 u32 supported;
191
192 if (hw->copper) {
193 supported = SUPPORTED_10baseT_Half
194 | SUPPORTED_10baseT_Full
195 | SUPPORTED_100baseT_Half
196 | SUPPORTED_100baseT_Full
197 | SUPPORTED_1000baseT_Half
198 | SUPPORTED_1000baseT_Full
199 | SUPPORTED_Autoneg| SUPPORTED_TP;
200
201 if (hw->chip_id == CHIP_ID_GENESIS)
202 supported &= ~(SUPPORTED_10baseT_Half
203 | SUPPORTED_10baseT_Full
204 | SUPPORTED_100baseT_Half
205 | SUPPORTED_100baseT_Full);
206
207 else if (hw->chip_id == CHIP_ID_YUKON)
208 supported &= ~SUPPORTED_1000baseT_Half;
209 } else
210 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
211 | SUPPORTED_Autoneg;
212
213 return supported;
214 }
215
216 static int skge_get_settings(struct net_device *dev,
217 struct ethtool_cmd *ecmd)
218 {
219 struct skge_port *skge = netdev_priv(dev);
220 struct skge_hw *hw = skge->hw;
221
222 ecmd->transceiver = XCVR_INTERNAL;
223 ecmd->supported = skge_supported_modes(hw);
224
225 if (hw->copper) {
226 ecmd->port = PORT_TP;
227 ecmd->phy_address = hw->phy_addr;
228 } else
229 ecmd->port = PORT_FIBRE;
230
231 ecmd->advertising = skge->advertising;
232 ecmd->autoneg = skge->autoneg;
233 ecmd->speed = skge->speed;
234 ecmd->duplex = skge->duplex;
235 return 0;
236 }
237
238 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
239 {
240 struct skge_port *skge = netdev_priv(dev);
241 const struct skge_hw *hw = skge->hw;
242 u32 supported = skge_supported_modes(hw);
243
244 if (ecmd->autoneg == AUTONEG_ENABLE) {
245 ecmd->advertising = supported;
246 skge->duplex = -1;
247 skge->speed = -1;
248 } else {
249 u32 setting;
250
251 switch (ecmd->speed) {
252 case SPEED_1000:
253 if (ecmd->duplex == DUPLEX_FULL)
254 setting = SUPPORTED_1000baseT_Full;
255 else if (ecmd->duplex == DUPLEX_HALF)
256 setting = SUPPORTED_1000baseT_Half;
257 else
258 return -EINVAL;
259 break;
260 case SPEED_100:
261 if (ecmd->duplex == DUPLEX_FULL)
262 setting = SUPPORTED_100baseT_Full;
263 else if (ecmd->duplex == DUPLEX_HALF)
264 setting = SUPPORTED_100baseT_Half;
265 else
266 return -EINVAL;
267 break;
268
269 case SPEED_10:
270 if (ecmd->duplex == DUPLEX_FULL)
271 setting = SUPPORTED_10baseT_Full;
272 else if (ecmd->duplex == DUPLEX_HALF)
273 setting = SUPPORTED_10baseT_Half;
274 else
275 return -EINVAL;
276 break;
277 default:
278 return -EINVAL;
279 }
280
281 if ((setting & supported) == 0)
282 return -EINVAL;
283
284 skge->speed = ecmd->speed;
285 skge->duplex = ecmd->duplex;
286 }
287
288 skge->autoneg = ecmd->autoneg;
289 skge->advertising = ecmd->advertising;
290
291 if (netif_running(dev)) {
292 skge_down(dev);
293 skge_up(dev);
294 }
295 return (0);
296 }
297
298 static void skge_get_drvinfo(struct net_device *dev,
299 struct ethtool_drvinfo *info)
300 {
301 struct skge_port *skge = netdev_priv(dev);
302
303 strcpy(info->driver, DRV_NAME);
304 strcpy(info->version, DRV_VERSION);
305 strcpy(info->fw_version, "N/A");
306 strcpy(info->bus_info, pci_name(skge->hw->pdev));
307 }
308
309 static const struct skge_stat {
310 char name[ETH_GSTRING_LEN];
311 u16 xmac_offset;
312 u16 gma_offset;
313 } skge_stats[] = {
314 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
315 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
316
317 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
318 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
319 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
320 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
321 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
322 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
323 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
324 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
325
326 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
327 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
328 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
329 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
330 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
331 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
332
333 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
334 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
335 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
336 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
337 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
338 };
339
340 static int skge_get_stats_count(struct net_device *dev)
341 {
342 return ARRAY_SIZE(skge_stats);
343 }
344
345 static void skge_get_ethtool_stats(struct net_device *dev,
346 struct ethtool_stats *stats, u64 *data)
347 {
348 struct skge_port *skge = netdev_priv(dev);
349
350 if (skge->hw->chip_id == CHIP_ID_GENESIS)
351 genesis_get_stats(skge, data);
352 else
353 yukon_get_stats(skge, data);
354 }
355
356 /* Use hardware MIB variables for critical path statistics and
357 * transmit feedback not reported at interrupt.
358 * Other errors are accounted for in interrupt handler.
359 */
360 static struct net_device_stats *skge_get_stats(struct net_device *dev)
361 {
362 struct skge_port *skge = netdev_priv(dev);
363 u64 data[ARRAY_SIZE(skge_stats)];
364
365 if (skge->hw->chip_id == CHIP_ID_GENESIS)
366 genesis_get_stats(skge, data);
367 else
368 yukon_get_stats(skge, data);
369
370 skge->net_stats.tx_bytes = data[0];
371 skge->net_stats.rx_bytes = data[1];
372 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
373 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
374 skge->net_stats.multicast = data[5] + data[7];
375 skge->net_stats.collisions = data[10];
376 skge->net_stats.tx_aborted_errors = data[12];
377
378 return &skge->net_stats;
379 }
380
381 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
382 {
383 int i;
384
385 switch (stringset) {
386 case ETH_SS_STATS:
387 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
388 memcpy(data + i * ETH_GSTRING_LEN,
389 skge_stats[i].name, ETH_GSTRING_LEN);
390 break;
391 }
392 }
393
394 static void skge_get_ring_param(struct net_device *dev,
395 struct ethtool_ringparam *p)
396 {
397 struct skge_port *skge = netdev_priv(dev);
398
399 p->rx_max_pending = MAX_RX_RING_SIZE;
400 p->tx_max_pending = MAX_TX_RING_SIZE;
401 p->rx_mini_max_pending = 0;
402 p->rx_jumbo_max_pending = 0;
403
404 p->rx_pending = skge->rx_ring.count;
405 p->tx_pending = skge->tx_ring.count;
406 p->rx_mini_pending = 0;
407 p->rx_jumbo_pending = 0;
408 }
409
410 static int skge_set_ring_param(struct net_device *dev,
411 struct ethtool_ringparam *p)
412 {
413 struct skge_port *skge = netdev_priv(dev);
414
415 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
416 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
417 return -EINVAL;
418
419 skge->rx_ring.count = p->rx_pending;
420 skge->tx_ring.count = p->tx_pending;
421
422 if (netif_running(dev)) {
423 skge_down(dev);
424 skge_up(dev);
425 }
426
427 return 0;
428 }
429
430 static u32 skge_get_msglevel(struct net_device *netdev)
431 {
432 struct skge_port *skge = netdev_priv(netdev);
433 return skge->msg_enable;
434 }
435
436 static void skge_set_msglevel(struct net_device *netdev, u32 value)
437 {
438 struct skge_port *skge = netdev_priv(netdev);
439 skge->msg_enable = value;
440 }
441
442 static int skge_nway_reset(struct net_device *dev)
443 {
444 struct skge_port *skge = netdev_priv(dev);
445 struct skge_hw *hw = skge->hw;
446 int port = skge->port;
447
448 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
449 return -EINVAL;
450
451 spin_lock_bh(&hw->phy_lock);
452 if (hw->chip_id == CHIP_ID_GENESIS) {
453 genesis_reset(hw, port);
454 genesis_mac_init(hw, port);
455 } else {
456 yukon_reset(hw, port);
457 yukon_init(hw, port);
458 }
459 spin_unlock_bh(&hw->phy_lock);
460 return 0;
461 }
462
463 static int skge_set_sg(struct net_device *dev, u32 data)
464 {
465 struct skge_port *skge = netdev_priv(dev);
466 struct skge_hw *hw = skge->hw;
467
468 if (hw->chip_id == CHIP_ID_GENESIS && data)
469 return -EOPNOTSUPP;
470 return ethtool_op_set_sg(dev, data);
471 }
472
473 static int skge_set_tx_csum(struct net_device *dev, u32 data)
474 {
475 struct skge_port *skge = netdev_priv(dev);
476 struct skge_hw *hw = skge->hw;
477
478 if (hw->chip_id == CHIP_ID_GENESIS && data)
479 return -EOPNOTSUPP;
480
481 return ethtool_op_set_tx_csum(dev, data);
482 }
483
484 static u32 skge_get_rx_csum(struct net_device *dev)
485 {
486 struct skge_port *skge = netdev_priv(dev);
487
488 return skge->rx_csum;
489 }
490
491 /* Only Yukon supports checksum offload. */
492 static int skge_set_rx_csum(struct net_device *dev, u32 data)
493 {
494 struct skge_port *skge = netdev_priv(dev);
495
496 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
497 return -EOPNOTSUPP;
498
499 skge->rx_csum = data;
500 return 0;
501 }
502
503 static void skge_get_pauseparam(struct net_device *dev,
504 struct ethtool_pauseparam *ecmd)
505 {
506 struct skge_port *skge = netdev_priv(dev);
507
508 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
509 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
510 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
511 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
512
513 ecmd->autoneg = skge->autoneg;
514 }
515
516 static int skge_set_pauseparam(struct net_device *dev,
517 struct ethtool_pauseparam *ecmd)
518 {
519 struct skge_port *skge = netdev_priv(dev);
520
521 skge->autoneg = ecmd->autoneg;
522 if (ecmd->rx_pause && ecmd->tx_pause)
523 skge->flow_control = FLOW_MODE_SYMMETRIC;
524 else if (ecmd->rx_pause && !ecmd->tx_pause)
525 skge->flow_control = FLOW_MODE_REM_SEND;
526 else if (!ecmd->rx_pause && ecmd->tx_pause)
527 skge->flow_control = FLOW_MODE_LOC_SEND;
528 else
529 skge->flow_control = FLOW_MODE_NONE;
530
531 if (netif_running(dev)) {
532 skge_down(dev);
533 skge_up(dev);
534 }
535 return 0;
536 }
537
538 /* Chip internal frequency for clock calculations */
539 static inline u32 hwkhz(const struct skge_hw *hw)
540 {
541 if (hw->chip_id == CHIP_ID_GENESIS)
542 return 53215; /* or: 53.125 MHz */
543 else
544 return 78215; /* or: 78.125 MHz */
545 }
546
547 /* Chip hz to microseconds */
548 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
549 {
550 return (ticks * 1000) / hwkhz(hw);
551 }
552
553 /* Microseconds to chip hz */
554 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
555 {
556 return hwkhz(hw) * usec / 1000;
557 }
558
559 static int skge_get_coalesce(struct net_device *dev,
560 struct ethtool_coalesce *ecmd)
561 {
562 struct skge_port *skge = netdev_priv(dev);
563 struct skge_hw *hw = skge->hw;
564 int port = skge->port;
565
566 ecmd->rx_coalesce_usecs = 0;
567 ecmd->tx_coalesce_usecs = 0;
568
569 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
570 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
571 u32 msk = skge_read32(hw, B2_IRQM_MSK);
572
573 if (msk & rxirqmask[port])
574 ecmd->rx_coalesce_usecs = delay;
575 if (msk & txirqmask[port])
576 ecmd->tx_coalesce_usecs = delay;
577 }
578
579 return 0;
580 }
581
582 /* Note: interrupt timer is per board, but can turn on/off per port */
583 static int skge_set_coalesce(struct net_device *dev,
584 struct ethtool_coalesce *ecmd)
585 {
586 struct skge_port *skge = netdev_priv(dev);
587 struct skge_hw *hw = skge->hw;
588 int port = skge->port;
589 u32 msk = skge_read32(hw, B2_IRQM_MSK);
590 u32 delay = 25;
591
592 if (ecmd->rx_coalesce_usecs == 0)
593 msk &= ~rxirqmask[port];
594 else if (ecmd->rx_coalesce_usecs < 25 ||
595 ecmd->rx_coalesce_usecs > 33333)
596 return -EINVAL;
597 else {
598 msk |= rxirqmask[port];
599 delay = ecmd->rx_coalesce_usecs;
600 }
601
602 if (ecmd->tx_coalesce_usecs == 0)
603 msk &= ~txirqmask[port];
604 else if (ecmd->tx_coalesce_usecs < 25 ||
605 ecmd->tx_coalesce_usecs > 33333)
606 return -EINVAL;
607 else {
608 msk |= txirqmask[port];
609 delay = min(delay, ecmd->rx_coalesce_usecs);
610 }
611
612 skge_write32(hw, B2_IRQM_MSK, msk);
613 if (msk == 0)
614 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
615 else {
616 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
617 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
618 }
619 return 0;
620 }
621
622 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
623 static void skge_led(struct skge_port *skge, enum led_mode mode)
624 {
625 struct skge_hw *hw = skge->hw;
626 int port = skge->port;
627
628 spin_lock_bh(&hw->phy_lock);
629 if (hw->chip_id == CHIP_ID_GENESIS) {
630 switch (mode) {
631 case LED_MODE_OFF:
632 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
633 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
634 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
635 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
636 break;
637
638 case LED_MODE_ON:
639 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
640 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
641
642 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
643 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
644
645 break;
646
647 case LED_MODE_TST:
648 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
649 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
650 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
651
652 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
653 break;
654 }
655 } else {
656 switch (mode) {
657 case LED_MODE_OFF:
658 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
659 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
660 PHY_M_LED_MO_DUP(MO_LED_OFF) |
661 PHY_M_LED_MO_10(MO_LED_OFF) |
662 PHY_M_LED_MO_100(MO_LED_OFF) |
663 PHY_M_LED_MO_1000(MO_LED_OFF) |
664 PHY_M_LED_MO_RX(MO_LED_OFF));
665 break;
666 case LED_MODE_ON:
667 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
668 PHY_M_LED_PULS_DUR(PULS_170MS) |
669 PHY_M_LED_BLINK_RT(BLINK_84MS) |
670 PHY_M_LEDC_TX_CTRL |
671 PHY_M_LEDC_DP_CTRL);
672
673 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
674 PHY_M_LED_MO_RX(MO_LED_OFF) |
675 (skge->speed == SPEED_100 ?
676 PHY_M_LED_MO_100(MO_LED_ON) : 0));
677 break;
678 case LED_MODE_TST:
679 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
680 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
681 PHY_M_LED_MO_DUP(MO_LED_ON) |
682 PHY_M_LED_MO_10(MO_LED_ON) |
683 PHY_M_LED_MO_100(MO_LED_ON) |
684 PHY_M_LED_MO_1000(MO_LED_ON) |
685 PHY_M_LED_MO_RX(MO_LED_ON));
686 }
687 }
688 spin_unlock_bh(&hw->phy_lock);
689 }
690
691 /* blink LED's for finding board */
692 static int skge_phys_id(struct net_device *dev, u32 data)
693 {
694 struct skge_port *skge = netdev_priv(dev);
695 unsigned long ms;
696 enum led_mode mode = LED_MODE_TST;
697
698 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
699 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
700 else
701 ms = data * 1000;
702
703 while (ms > 0) {
704 skge_led(skge, mode);
705 mode ^= LED_MODE_TST;
706
707 if (msleep_interruptible(BLINK_MS))
708 break;
709 ms -= BLINK_MS;
710 }
711
712 /* back to regular LED state */
713 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
714
715 return 0;
716 }
717
718 static struct ethtool_ops skge_ethtool_ops = {
719 .get_settings = skge_get_settings,
720 .set_settings = skge_set_settings,
721 .get_drvinfo = skge_get_drvinfo,
722 .get_regs_len = skge_get_regs_len,
723 .get_regs = skge_get_regs,
724 .get_wol = skge_get_wol,
725 .set_wol = skge_set_wol,
726 .get_msglevel = skge_get_msglevel,
727 .set_msglevel = skge_set_msglevel,
728 .nway_reset = skge_nway_reset,
729 .get_link = ethtool_op_get_link,
730 .get_ringparam = skge_get_ring_param,
731 .set_ringparam = skge_set_ring_param,
732 .get_pauseparam = skge_get_pauseparam,
733 .set_pauseparam = skge_set_pauseparam,
734 .get_coalesce = skge_get_coalesce,
735 .set_coalesce = skge_set_coalesce,
736 .get_sg = ethtool_op_get_sg,
737 .set_sg = skge_set_sg,
738 .get_tx_csum = ethtool_op_get_tx_csum,
739 .set_tx_csum = skge_set_tx_csum,
740 .get_rx_csum = skge_get_rx_csum,
741 .set_rx_csum = skge_set_rx_csum,
742 .get_strings = skge_get_strings,
743 .phys_id = skge_phys_id,
744 .get_stats_count = skge_get_stats_count,
745 .get_ethtool_stats = skge_get_ethtool_stats,
746 };
747
748 /*
749 * Allocate ring elements and chain them together
750 * One-to-one association of board descriptors with ring elements
751 */
752 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
753 {
754 struct skge_tx_desc *d;
755 struct skge_element *e;
756 int i;
757
758 ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
759 if (!ring->start)
760 return -ENOMEM;
761
762 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
763 e->desc = d;
764 e->skb = NULL;
765 if (i == ring->count - 1) {
766 e->next = ring->start;
767 d->next_offset = base;
768 } else {
769 e->next = e + 1;
770 d->next_offset = base + (i+1) * sizeof(*d);
771 }
772 }
773 ring->to_use = ring->to_clean = ring->start;
774
775 return 0;
776 }
777
778 static struct sk_buff *skge_rx_alloc(struct net_device *dev, unsigned int size)
779 {
780 struct sk_buff *skb = dev_alloc_skb(size);
781
782 if (likely(skb)) {
783 skb->dev = dev;
784 skb_reserve(skb, NET_IP_ALIGN);
785 }
786 return skb;
787 }
788
789 /* Allocate and setup a new buffer for receiving */
790 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
791 struct sk_buff *skb, unsigned int bufsize)
792 {
793 struct skge_rx_desc *rd = e->desc;
794 u64 map;
795
796 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
797 PCI_DMA_FROMDEVICE);
798
799 rd->dma_lo = map;
800 rd->dma_hi = map >> 32;
801 e->skb = skb;
802 rd->csum1_start = ETH_HLEN;
803 rd->csum2_start = ETH_HLEN;
804 rd->csum1 = 0;
805 rd->csum2 = 0;
806
807 wmb();
808
809 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
810 pci_unmap_addr_set(e, mapaddr, map);
811 pci_unmap_len_set(e, maplen, bufsize);
812 }
813
814 /* Resume receiving using existing skb,
815 * Note: DMA address is not changed by chip.
816 * MTU not changed while receiver active.
817 */
818 static void skge_rx_reuse(struct skge_element *e, unsigned int size)
819 {
820 struct skge_rx_desc *rd = e->desc;
821
822 rd->csum2 = 0;
823 rd->csum2_start = ETH_HLEN;
824
825 wmb();
826
827 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
828 }
829
830
831 /* Free all buffers in receive ring, assumes receiver stopped */
832 static void skge_rx_clean(struct skge_port *skge)
833 {
834 struct skge_hw *hw = skge->hw;
835 struct skge_ring *ring = &skge->rx_ring;
836 struct skge_element *e;
837
838 e = ring->start;
839 do {
840 struct skge_rx_desc *rd = e->desc;
841 rd->control = 0;
842 if (e->skb) {
843 pci_unmap_single(hw->pdev,
844 pci_unmap_addr(e, mapaddr),
845 pci_unmap_len(e, maplen),
846 PCI_DMA_FROMDEVICE);
847 dev_kfree_skb(e->skb);
848 e->skb = NULL;
849 }
850 } while ((e = e->next) != ring->start);
851 }
852
853
854 /* Allocate buffers for receive ring
855 * For receive: to_clean is next received frame.
856 */
857 static int skge_rx_fill(struct skge_port *skge)
858 {
859 struct skge_ring *ring = &skge->rx_ring;
860 struct skge_element *e;
861 unsigned int bufsize = skge->rx_buf_size;
862
863 e = ring->start;
864 do {
865 struct sk_buff *skb = skge_rx_alloc(skge->netdev, bufsize);
866
867 if (!skb)
868 return -ENOMEM;
869
870 skge_rx_setup(skge, e, skb, bufsize);
871 } while ( (e = e->next) != ring->start);
872
873 ring->to_clean = ring->start;
874 return 0;
875 }
876
877 static void skge_link_up(struct skge_port *skge)
878 {
879 netif_carrier_on(skge->netdev);
880 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
881 netif_wake_queue(skge->netdev);
882
883 if (netif_msg_link(skge))
884 printk(KERN_INFO PFX
885 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
886 skge->netdev->name, skge->speed,
887 skge->duplex == DUPLEX_FULL ? "full" : "half",
888 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
889 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
890 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
891 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
892 "unknown");
893 }
894
895 static void skge_link_down(struct skge_port *skge)
896 {
897 netif_carrier_off(skge->netdev);
898 netif_stop_queue(skge->netdev);
899
900 if (netif_msg_link(skge))
901 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
902 }
903
904 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
905 {
906 int i;
907 u16 v;
908
909 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
910 v = xm_read16(hw, port, XM_PHY_DATA);
911
912 /* Need to wait for external PHY */
913 for (i = 0; i < PHY_RETRIES; i++) {
914 udelay(1);
915 if (xm_read16(hw, port, XM_MMU_CMD)
916 & XM_MMU_PHY_RDY)
917 goto ready;
918 }
919
920 printk(KERN_WARNING PFX "%s: phy read timed out\n",
921 hw->dev[port]->name);
922 return 0;
923 ready:
924 v = xm_read16(hw, port, XM_PHY_DATA);
925
926 return v;
927 }
928
929 static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
930 {
931 int i;
932
933 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
934 for (i = 0; i < PHY_RETRIES; i++) {
935 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
936 goto ready;
937 udelay(1);
938 }
939 printk(KERN_WARNING PFX "%s: phy write failed to come ready\n",
940 hw->dev[port]->name);
941
942
943 ready:
944 xm_write16(hw, port, XM_PHY_DATA, val);
945 for (i = 0; i < PHY_RETRIES; i++) {
946 udelay(1);
947 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
948 return;
949 }
950 printk(KERN_WARNING PFX "%s: phy write timed out\n",
951 hw->dev[port]->name);
952 }
953
954 static void genesis_init(struct skge_hw *hw)
955 {
956 /* set blink source counter */
957 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
958 skge_write8(hw, B2_BSC_CTRL, BSC_START);
959
960 /* configure mac arbiter */
961 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
962
963 /* configure mac arbiter timeout values */
964 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
965 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
966 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
967 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
968
969 skge_write8(hw, B3_MA_RCINI_RX1, 0);
970 skge_write8(hw, B3_MA_RCINI_RX2, 0);
971 skge_write8(hw, B3_MA_RCINI_TX1, 0);
972 skge_write8(hw, B3_MA_RCINI_TX2, 0);
973
974 /* configure packet arbiter timeout */
975 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
976 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
977 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
978 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
979 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
980 }
981
982 static void genesis_reset(struct skge_hw *hw, int port)
983 {
984 const u8 zero[8] = { 0 };
985
986 /* reset the statistics module */
987 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
988 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
989 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
990 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
991 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
992
993 /* disable Broadcom PHY IRQ */
994 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
995
996 xm_outhash(hw, port, XM_HSM, zero);
997 }
998
999
1000 /* Convert mode to MII values */
1001 static const u16 phy_pause_map[] = {
1002 [FLOW_MODE_NONE] = 0,
1003 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1004 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1005 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1006 };
1007
1008
1009 /* Check status of Broadcom phy link */
1010 static void bcom_check_link(struct skge_hw *hw, int port)
1011 {
1012 struct net_device *dev = hw->dev[port];
1013 struct skge_port *skge = netdev_priv(dev);
1014 u16 status;
1015
1016 /* read twice because of latch */
1017 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
1018 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1019
1020 pr_debug("bcom_check_link status=0x%x\n", status);
1021
1022 if ((status & PHY_ST_LSYNC) == 0) {
1023 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
1024 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1025 xm_write16(hw, port, XM_MMU_CMD, cmd);
1026 /* dummy read to ensure writing */
1027 (void) xm_read16(hw, port, XM_MMU_CMD);
1028
1029 if (netif_carrier_ok(dev))
1030 skge_link_down(skge);
1031 } else {
1032 if (skge->autoneg == AUTONEG_ENABLE &&
1033 (status & PHY_ST_AN_OVER)) {
1034 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1035 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1036
1037 if (lpa & PHY_B_AN_RF) {
1038 printk(KERN_NOTICE PFX "%s: remote fault\n",
1039 dev->name);
1040 return;
1041 }
1042
1043 /* Check Duplex mismatch */
1044 switch (aux & PHY_B_AS_AN_RES_MSK) {
1045 case PHY_B_RES_1000FD:
1046 skge->duplex = DUPLEX_FULL;
1047 break;
1048 case PHY_B_RES_1000HD:
1049 skge->duplex = DUPLEX_HALF;
1050 break;
1051 default:
1052 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1053 dev->name);
1054 return;
1055 }
1056
1057
1058 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1059 switch (aux & PHY_B_AS_PAUSE_MSK) {
1060 case PHY_B_AS_PAUSE_MSK:
1061 skge->flow_control = FLOW_MODE_SYMMETRIC;
1062 break;
1063 case PHY_B_AS_PRR:
1064 skge->flow_control = FLOW_MODE_REM_SEND;
1065 break;
1066 case PHY_B_AS_PRT:
1067 skge->flow_control = FLOW_MODE_LOC_SEND;
1068 break;
1069 default:
1070 skge->flow_control = FLOW_MODE_NONE;
1071 }
1072
1073 skge->speed = SPEED_1000;
1074 }
1075
1076 if (!netif_carrier_ok(dev))
1077 genesis_link_up(skge);
1078 }
1079 }
1080
1081 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1082 * Phy on for 100 or 10Mbit operation
1083 */
1084 static void bcom_phy_init(struct skge_port *skge, int jumbo)
1085 {
1086 struct skge_hw *hw = skge->hw;
1087 int port = skge->port;
1088 int i;
1089 u16 id1, r, ext, ctl;
1090
1091 /* magic workaround patterns for Broadcom */
1092 static const struct {
1093 u16 reg;
1094 u16 val;
1095 } A1hack[] = {
1096 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1097 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1098 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1099 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1100 }, C0hack[] = {
1101 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1102 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1103 };
1104
1105 pr_debug("bcom_phy_init\n");
1106
1107 /* read Id from external PHY (all have the same address) */
1108 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1109
1110 /* Optimize MDIO transfer by suppressing preamble. */
1111 r = xm_read16(hw, port, XM_MMU_CMD);
1112 r |= XM_MMU_NO_PRE;
1113 xm_write16(hw, port, XM_MMU_CMD,r);
1114
1115 switch (id1) {
1116 case PHY_BCOM_ID1_C0:
1117 /*
1118 * Workaround BCOM Errata for the C0 type.
1119 * Write magic patterns to reserved registers.
1120 */
1121 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1122 xm_phy_write(hw, port,
1123 C0hack[i].reg, C0hack[i].val);
1124
1125 break;
1126 case PHY_BCOM_ID1_A1:
1127 /*
1128 * Workaround BCOM Errata for the A1 type.
1129 * Write magic patterns to reserved registers.
1130 */
1131 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1132 xm_phy_write(hw, port,
1133 A1hack[i].reg, A1hack[i].val);
1134 break;
1135 }
1136
1137 /*
1138 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1139 * Disable Power Management after reset.
1140 */
1141 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1142 r |= PHY_B_AC_DIS_PM;
1143 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1144
1145 /* Dummy read */
1146 xm_read16(hw, port, XM_ISRC);
1147
1148 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1149 ctl = PHY_CT_SP1000; /* always 1000mbit */
1150
1151 if (skge->autoneg == AUTONEG_ENABLE) {
1152 /*
1153 * Workaround BCOM Errata #1 for the C5 type.
1154 * 1000Base-T Link Acquisition Failure in Slave Mode
1155 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1156 */
1157 u16 adv = PHY_B_1000C_RD;
1158 if (skge->advertising & ADVERTISED_1000baseT_Half)
1159 adv |= PHY_B_1000C_AHD;
1160 if (skge->advertising & ADVERTISED_1000baseT_Full)
1161 adv |= PHY_B_1000C_AFD;
1162 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1163
1164 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1165 } else {
1166 if (skge->duplex == DUPLEX_FULL)
1167 ctl |= PHY_CT_DUP_MD;
1168 /* Force to slave */
1169 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1170 }
1171
1172 /* Set autonegotiation pause parameters */
1173 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1174 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1175
1176 /* Handle Jumbo frames */
1177 if (jumbo) {
1178 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1179 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1180
1181 ext |= PHY_B_PEC_HIGH_LA;
1182
1183 }
1184
1185 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1186 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1187
1188 /* Use link status change interrrupt */
1189 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1190
1191 bcom_check_link(hw, port);
1192 }
1193
1194 static void genesis_mac_init(struct skge_hw *hw, int port)
1195 {
1196 struct net_device *dev = hw->dev[port];
1197 struct skge_port *skge = netdev_priv(dev);
1198 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1199 int i;
1200 u32 r;
1201 const u8 zero[6] = { 0 };
1202
1203 /* Clear MIB counters */
1204 xm_write16(hw, port, XM_STAT_CMD,
1205 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1206 /* Clear two times according to Errata #3 */
1207 xm_write16(hw, port, XM_STAT_CMD,
1208 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1209
1210 /* Unreset the XMAC. */
1211 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1212
1213 /*
1214 * Perform additional initialization for external PHYs,
1215 * namely for the 1000baseTX cards that use the XMAC's
1216 * GMII mode.
1217 */
1218 /* Take external Phy out of reset */
1219 r = skge_read32(hw, B2_GP_IO);
1220 if (port == 0)
1221 r |= GP_DIR_0|GP_IO_0;
1222 else
1223 r |= GP_DIR_2|GP_IO_2;
1224
1225 skge_write32(hw, B2_GP_IO, r);
1226 skge_read32(hw, B2_GP_IO);
1227
1228 /* Enable GMII interfac */
1229 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1230
1231 bcom_phy_init(skge, jumbo);
1232
1233 /* Set Station Address */
1234 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1235
1236 /* We don't use match addresses so clear */
1237 for (i = 1; i < 16; i++)
1238 xm_outaddr(hw, port, XM_EXM(i), zero);
1239
1240 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1241 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1242
1243 /* We don't need the FCS appended to the packet. */
1244 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1245 if (jumbo)
1246 r |= XM_RX_BIG_PK_OK;
1247
1248 if (skge->duplex == DUPLEX_HALF) {
1249 /*
1250 * If in manual half duplex mode the other side might be in
1251 * full duplex mode, so ignore if a carrier extension is not seen
1252 * on frames received
1253 */
1254 r |= XM_RX_DIS_CEXT;
1255 }
1256 xm_write16(hw, port, XM_RX_CMD, r);
1257
1258
1259 /* We want short frames padded to 60 bytes. */
1260 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1261
1262 /*
1263 * Bump up the transmit threshold. This helps hold off transmit
1264 * underruns when we're blasting traffic from both ports at once.
1265 */
1266 xm_write16(hw, port, XM_TX_THR, 512);
1267
1268 /*
1269 * Enable the reception of all error frames. This is is
1270 * a necessary evil due to the design of the XMAC. The
1271 * XMAC's receive FIFO is only 8K in size, however jumbo
1272 * frames can be up to 9000 bytes in length. When bad
1273 * frame filtering is enabled, the XMAC's RX FIFO operates
1274 * in 'store and forward' mode. For this to work, the
1275 * entire frame has to fit into the FIFO, but that means
1276 * that jumbo frames larger than 8192 bytes will be
1277 * truncated. Disabling all bad frame filtering causes
1278 * the RX FIFO to operate in streaming mode, in which
1279 * case the XMAC will start transfering frames out of the
1280 * RX FIFO as soon as the FIFO threshold is reached.
1281 */
1282 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1283
1284
1285 /*
1286 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1287 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1288 * and 'Octets Rx OK Hi Cnt Ov'.
1289 */
1290 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1291
1292 /*
1293 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1294 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1295 * and 'Octets Tx OK Hi Cnt Ov'.
1296 */
1297 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1298
1299 /* Configure MAC arbiter */
1300 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1301
1302 /* configure timeout values */
1303 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1304 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1305 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1306 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1307
1308 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1309 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1310 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1311 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1312
1313 /* Configure Rx MAC FIFO */
1314 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1315 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1316 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1317
1318 /* Configure Tx MAC FIFO */
1319 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1320 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1321 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1322
1323 if (jumbo) {
1324 /* Enable frame flushing if jumbo frames used */
1325 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1326 } else {
1327 /* enable timeout timers if normal frames */
1328 skge_write16(hw, B3_PA_CTRL,
1329 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1330 }
1331 }
1332
1333 static void genesis_stop(struct skge_port *skge)
1334 {
1335 struct skge_hw *hw = skge->hw;
1336 int port = skge->port;
1337 u32 reg;
1338
1339 /* Clear Tx packet arbiter timeout IRQ */
1340 skge_write16(hw, B3_PA_CTRL,
1341 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1342
1343 /*
1344 * If the transfer stucks at the MAC the STOP command will not
1345 * terminate if we don't flush the XMAC's transmit FIFO !
1346 */
1347 xm_write32(hw, port, XM_MODE,
1348 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1349
1350
1351 /* Reset the MAC */
1352 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1353
1354 /* For external PHYs there must be special handling */
1355 reg = skge_read32(hw, B2_GP_IO);
1356 if (port == 0) {
1357 reg |= GP_DIR_0;
1358 reg &= ~GP_IO_0;
1359 } else {
1360 reg |= GP_DIR_2;
1361 reg &= ~GP_IO_2;
1362 }
1363 skge_write32(hw, B2_GP_IO, reg);
1364 skge_read32(hw, B2_GP_IO);
1365
1366 xm_write16(hw, port, XM_MMU_CMD,
1367 xm_read16(hw, port, XM_MMU_CMD)
1368 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1369
1370 xm_read16(hw, port, XM_MMU_CMD);
1371 }
1372
1373
1374 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1375 {
1376 struct skge_hw *hw = skge->hw;
1377 int port = skge->port;
1378 int i;
1379 unsigned long timeout = jiffies + HZ;
1380
1381 xm_write16(hw, port,
1382 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1383
1384 /* wait for update to complete */
1385 while (xm_read16(hw, port, XM_STAT_CMD)
1386 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1387 if (time_after(jiffies, timeout))
1388 break;
1389 udelay(10);
1390 }
1391
1392 /* special case for 64 bit octet counter */
1393 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1394 | xm_read32(hw, port, XM_TXO_OK_LO);
1395 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1396 | xm_read32(hw, port, XM_RXO_OK_LO);
1397
1398 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1399 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1400 }
1401
1402 static void genesis_mac_intr(struct skge_hw *hw, int port)
1403 {
1404 struct skge_port *skge = netdev_priv(hw->dev[port]);
1405 u16 status = xm_read16(hw, port, XM_ISRC);
1406
1407 if (netif_msg_intr(skge))
1408 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1409 skge->netdev->name, status);
1410
1411 if (status & XM_IS_TXF_UR) {
1412 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1413 ++skge->net_stats.tx_fifo_errors;
1414 }
1415 if (status & XM_IS_RXF_OV) {
1416 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1417 ++skge->net_stats.rx_fifo_errors;
1418 }
1419 }
1420
1421 static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1422 {
1423 int i;
1424
1425 gma_write16(hw, port, GM_SMI_DATA, val);
1426 gma_write16(hw, port, GM_SMI_CTRL,
1427 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1428 for (i = 0; i < PHY_RETRIES; i++) {
1429 udelay(1);
1430
1431 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1432 break;
1433 }
1434 }
1435
1436 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1437 {
1438 int i;
1439
1440 gma_write16(hw, port, GM_SMI_CTRL,
1441 GM_SMI_CT_PHY_AD(hw->phy_addr)
1442 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1443
1444 for (i = 0; i < PHY_RETRIES; i++) {
1445 udelay(1);
1446 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1447 goto ready;
1448 }
1449
1450 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1451 hw->dev[port]->name);
1452 return 0;
1453 ready:
1454 return gma_read16(hw, port, GM_SMI_DATA);
1455 }
1456
1457 static void genesis_link_up(struct skge_port *skge)
1458 {
1459 struct skge_hw *hw = skge->hw;
1460 int port = skge->port;
1461 u16 cmd;
1462 u32 mode, msk;
1463
1464 pr_debug("genesis_link_up\n");
1465 cmd = xm_read16(hw, port, XM_MMU_CMD);
1466
1467 /*
1468 * enabling pause frame reception is required for 1000BT
1469 * because the XMAC is not reset if the link is going down
1470 */
1471 if (skge->flow_control == FLOW_MODE_NONE ||
1472 skge->flow_control == FLOW_MODE_LOC_SEND)
1473 /* Disable Pause Frame Reception */
1474 cmd |= XM_MMU_IGN_PF;
1475 else
1476 /* Enable Pause Frame Reception */
1477 cmd &= ~XM_MMU_IGN_PF;
1478
1479 xm_write16(hw, port, XM_MMU_CMD, cmd);
1480
1481 mode = xm_read32(hw, port, XM_MODE);
1482 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1483 skge->flow_control == FLOW_MODE_LOC_SEND) {
1484 /*
1485 * Configure Pause Frame Generation
1486 * Use internal and external Pause Frame Generation.
1487 * Sending pause frames is edge triggered.
1488 * Send a Pause frame with the maximum pause time if
1489 * internal oder external FIFO full condition occurs.
1490 * Send a zero pause time frame to re-start transmission.
1491 */
1492 /* XM_PAUSE_DA = '010000C28001' (default) */
1493 /* XM_MAC_PTIME = 0xffff (maximum) */
1494 /* remember this value is defined in big endian (!) */
1495 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1496
1497 mode |= XM_PAUSE_MODE;
1498 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1499 } else {
1500 /*
1501 * disable pause frame generation is required for 1000BT
1502 * because the XMAC is not reset if the link is going down
1503 */
1504 /* Disable Pause Mode in Mode Register */
1505 mode &= ~XM_PAUSE_MODE;
1506
1507 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1508 }
1509
1510 xm_write32(hw, port, XM_MODE, mode);
1511
1512 msk = XM_DEF_MSK;
1513 /* disable GP0 interrupt bit for external Phy */
1514 msk |= XM_IS_INP_ASS;
1515
1516 xm_write16(hw, port, XM_IMSK, msk);
1517 xm_read16(hw, port, XM_ISRC);
1518
1519 /* get MMU Command Reg. */
1520 cmd = xm_read16(hw, port, XM_MMU_CMD);
1521 if (skge->duplex == DUPLEX_FULL)
1522 cmd |= XM_MMU_GMII_FD;
1523
1524 /*
1525 * Workaround BCOM Errata (#10523) for all BCom Phys
1526 * Enable Power Management after link up
1527 */
1528 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1529 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1530 & ~PHY_B_AC_DIS_PM);
1531 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1532
1533 /* enable Rx/Tx */
1534 xm_write16(hw, port, XM_MMU_CMD,
1535 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1536 skge_link_up(skge);
1537 }
1538
1539
1540 static inline void bcom_phy_intr(struct skge_port *skge)
1541 {
1542 struct skge_hw *hw = skge->hw;
1543 int port = skge->port;
1544 u16 isrc;
1545
1546 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1547 if (netif_msg_intr(skge))
1548 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1549 skge->netdev->name, isrc);
1550
1551 if (isrc & PHY_B_IS_PSE)
1552 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1553 hw->dev[port]->name);
1554
1555 /* Workaround BCom Errata:
1556 * enable and disable loopback mode if "NO HCD" occurs.
1557 */
1558 if (isrc & PHY_B_IS_NO_HDCL) {
1559 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1560 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1561 ctrl | PHY_CT_LOOP);
1562 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1563 ctrl & ~PHY_CT_LOOP);
1564 }
1565
1566 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1567 bcom_check_link(hw, port);
1568
1569 }
1570
1571 /* Marvell Phy Initailization */
1572 static void yukon_init(struct skge_hw *hw, int port)
1573 {
1574 struct skge_port *skge = netdev_priv(hw->dev[port]);
1575 u16 ctrl, ct1000, adv;
1576
1577 pr_debug("yukon_init\n");
1578 if (skge->autoneg == AUTONEG_ENABLE) {
1579 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1580
1581 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1582 PHY_M_EC_MAC_S_MSK);
1583 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1584
1585 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1586
1587 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1588 }
1589
1590 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1591 if (skge->autoneg == AUTONEG_DISABLE)
1592 ctrl &= ~PHY_CT_ANE;
1593
1594 ctrl |= PHY_CT_RESET;
1595 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1596
1597 ctrl = 0;
1598 ct1000 = 0;
1599 adv = PHY_AN_CSMA;
1600
1601 if (skge->autoneg == AUTONEG_ENABLE) {
1602 if (hw->copper) {
1603 if (skge->advertising & ADVERTISED_1000baseT_Full)
1604 ct1000 |= PHY_M_1000C_AFD;
1605 if (skge->advertising & ADVERTISED_1000baseT_Half)
1606 ct1000 |= PHY_M_1000C_AHD;
1607 if (skge->advertising & ADVERTISED_100baseT_Full)
1608 adv |= PHY_M_AN_100_FD;
1609 if (skge->advertising & ADVERTISED_100baseT_Half)
1610 adv |= PHY_M_AN_100_HD;
1611 if (skge->advertising & ADVERTISED_10baseT_Full)
1612 adv |= PHY_M_AN_10_FD;
1613 if (skge->advertising & ADVERTISED_10baseT_Half)
1614 adv |= PHY_M_AN_10_HD;
1615 } else /* special defines for FIBER (88E1011S only) */
1616 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1617
1618 /* Set Flow-control capabilities */
1619 adv |= phy_pause_map[skge->flow_control];
1620
1621 /* Restart Auto-negotiation */
1622 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1623 } else {
1624 /* forced speed/duplex settings */
1625 ct1000 = PHY_M_1000C_MSE;
1626
1627 if (skge->duplex == DUPLEX_FULL)
1628 ctrl |= PHY_CT_DUP_MD;
1629
1630 switch (skge->speed) {
1631 case SPEED_1000:
1632 ctrl |= PHY_CT_SP1000;
1633 break;
1634 case SPEED_100:
1635 ctrl |= PHY_CT_SP100;
1636 break;
1637 }
1638
1639 ctrl |= PHY_CT_RESET;
1640 }
1641
1642 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1643
1644 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1645 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1646
1647 /* Enable phy interrupt on autonegotiation complete (or link up) */
1648 if (skge->autoneg == AUTONEG_ENABLE)
1649 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
1650 else
1651 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1652 }
1653
1654 static void yukon_reset(struct skge_hw *hw, int port)
1655 {
1656 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1657 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1658 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1659 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1660 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1661
1662 gma_write16(hw, port, GM_RX_CTRL,
1663 gma_read16(hw, port, GM_RX_CTRL)
1664 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1665 }
1666
1667 static void yukon_mac_init(struct skge_hw *hw, int port)
1668 {
1669 struct skge_port *skge = netdev_priv(hw->dev[port]);
1670 int i;
1671 u32 reg;
1672 const u8 *addr = hw->dev[port]->dev_addr;
1673
1674 /* WA code for COMA mode -- set PHY reset */
1675 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1676 hw->chip_rev >= CHIP_REV_YU_LITE_A3)
1677 skge_write32(hw, B2_GP_IO,
1678 (skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9));
1679
1680 /* hard reset */
1681 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1682 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1683
1684 /* WA code for COMA mode -- clear PHY reset */
1685 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1686 hw->chip_rev >= CHIP_REV_YU_LITE_A3)
1687 skge_write32(hw, B2_GP_IO,
1688 (skge_read32(hw, B2_GP_IO) | GP_DIR_9)
1689 & ~GP_IO_9);
1690
1691 /* Set hardware config mode */
1692 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1693 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1694 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1695
1696 /* Clear GMC reset */
1697 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1698 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1699 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
1700 if (skge->autoneg == AUTONEG_DISABLE) {
1701 reg = GM_GPCR_AU_ALL_DIS;
1702 gma_write16(hw, port, GM_GP_CTRL,
1703 gma_read16(hw, port, GM_GP_CTRL) | reg);
1704
1705 switch (skge->speed) {
1706 case SPEED_1000:
1707 reg |= GM_GPCR_SPEED_1000;
1708 /* fallthru */
1709 case SPEED_100:
1710 reg |= GM_GPCR_SPEED_100;
1711 }
1712
1713 if (skge->duplex == DUPLEX_FULL)
1714 reg |= GM_GPCR_DUP_FULL;
1715 } else
1716 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1717 switch (skge->flow_control) {
1718 case FLOW_MODE_NONE:
1719 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1720 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1721 break;
1722 case FLOW_MODE_LOC_SEND:
1723 /* disable Rx flow-control */
1724 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1725 }
1726
1727 gma_write16(hw, port, GM_GP_CTRL, reg);
1728 skge_read16(hw, GMAC_IRQ_SRC);
1729
1730 yukon_init(hw, port);
1731
1732 /* MIB clear */
1733 reg = gma_read16(hw, port, GM_PHY_ADDR);
1734 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
1735
1736 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
1737 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1738 gma_write16(hw, port, GM_PHY_ADDR, reg);
1739
1740 /* transmit control */
1741 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
1742
1743 /* receive control reg: unicast + multicast + no FCS */
1744 gma_write16(hw, port, GM_RX_CTRL,
1745 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1746
1747 /* transmit flow control */
1748 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
1749
1750 /* transmit parameter */
1751 gma_write16(hw, port, GM_TX_PARAM,
1752 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1753 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1754 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1755
1756 /* serial mode register */
1757 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1758 if (hw->dev[port]->mtu > 1500)
1759 reg |= GM_SMOD_JUMBO_ENA;
1760
1761 gma_write16(hw, port, GM_SERIAL_MODE, reg);
1762
1763 /* physical address: used for pause frames */
1764 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
1765 /* virtual address for data */
1766 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
1767
1768 /* enable interrupt mask for counter overflows */
1769 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1770 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1771 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
1772
1773 /* Initialize Mac Fifo */
1774
1775 /* Configure Rx MAC FIFO */
1776 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
1777 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1778 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1779 hw->chip_rev >= CHIP_REV_YU_LITE_A3)
1780 reg &= ~GMF_RX_F_FL_ON;
1781 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1782 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1783 /*
1784 * because Pause Packet Truncation in GMAC is not working
1785 * we have to increase the Flush Threshold to 64 bytes
1786 * in order to flush pause packets in Rx FIFO on Yukon-1
1787 */
1788 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
1789
1790 /* Configure Tx MAC FIFO */
1791 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1792 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1793 }
1794
1795 static void yukon_stop(struct skge_port *skge)
1796 {
1797 struct skge_hw *hw = skge->hw;
1798 int port = skge->port;
1799
1800 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1801 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1802 skge_write32(hw, B2_GP_IO,
1803 skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9);
1804 }
1805
1806 gma_write16(hw, port, GM_GP_CTRL,
1807 gma_read16(hw, port, GM_GP_CTRL)
1808 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
1809 gma_read16(hw, port, GM_GP_CTRL);
1810
1811 /* set GPHY Control reset */
1812 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1813 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1814 }
1815
1816 static void yukon_get_stats(struct skge_port *skge, u64 *data)
1817 {
1818 struct skge_hw *hw = skge->hw;
1819 int port = skge->port;
1820 int i;
1821
1822 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1823 | gma_read32(hw, port, GM_TXO_OK_LO);
1824 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1825 | gma_read32(hw, port, GM_RXO_OK_LO);
1826
1827 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1828 data[i] = gma_read32(hw, port,
1829 skge_stats[i].gma_offset);
1830 }
1831
1832 static void yukon_mac_intr(struct skge_hw *hw, int port)
1833 {
1834 struct net_device *dev = hw->dev[port];
1835 struct skge_port *skge = netdev_priv(dev);
1836 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1837
1838 if (netif_msg_intr(skge))
1839 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1840 dev->name, status);
1841
1842 if (status & GM_IS_RX_FF_OR) {
1843 ++skge->net_stats.rx_fifo_errors;
1844 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1845 }
1846
1847 if (status & GM_IS_TX_FF_UR) {
1848 ++skge->net_stats.tx_fifo_errors;
1849 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1850 }
1851
1852 }
1853
1854 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1855 {
1856 switch (aux & PHY_M_PS_SPEED_MSK) {
1857 case PHY_M_PS_SPEED_1000:
1858 return SPEED_1000;
1859 case PHY_M_PS_SPEED_100:
1860 return SPEED_100;
1861 default:
1862 return SPEED_10;
1863 }
1864 }
1865
1866 static void yukon_link_up(struct skge_port *skge)
1867 {
1868 struct skge_hw *hw = skge->hw;
1869 int port = skge->port;
1870 u16 reg;
1871
1872 pr_debug("yukon_link_up\n");
1873
1874 /* Enable Transmit FIFO Underrun */
1875 skge_write8(hw, GMAC_IRQ_MSK, GMAC_DEF_MSK);
1876
1877 reg = gma_read16(hw, port, GM_GP_CTRL);
1878 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1879 reg |= GM_GPCR_DUP_FULL;
1880
1881 /* enable Rx/Tx */
1882 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1883 gma_write16(hw, port, GM_GP_CTRL, reg);
1884
1885 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1886 skge_link_up(skge);
1887 }
1888
1889 static void yukon_link_down(struct skge_port *skge)
1890 {
1891 struct skge_hw *hw = skge->hw;
1892 int port = skge->port;
1893 u16 ctrl;
1894
1895 pr_debug("yukon_link_down\n");
1896 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1897
1898 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1899 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1900 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1901
1902 if (skge->flow_control == FLOW_MODE_REM_SEND) {
1903 /* restore Asymmetric Pause bit */
1904 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1905 gm_phy_read(hw, port,
1906 PHY_MARV_AUNE_ADV)
1907 | PHY_M_AN_ASP);
1908
1909 }
1910
1911 yukon_reset(hw, port);
1912 skge_link_down(skge);
1913
1914 yukon_init(hw, port);
1915 }
1916
1917 static void yukon_phy_intr(struct skge_port *skge)
1918 {
1919 struct skge_hw *hw = skge->hw;
1920 int port = skge->port;
1921 const char *reason = NULL;
1922 u16 istatus, phystat;
1923
1924 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1925 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1926
1927 if (netif_msg_intr(skge))
1928 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1929 skge->netdev->name, istatus, phystat);
1930
1931 if (istatus & PHY_M_IS_AN_COMPL) {
1932 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
1933 & PHY_M_AN_RF) {
1934 reason = "remote fault";
1935 goto failed;
1936 }
1937
1938 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1939 reason = "master/slave fault";
1940 goto failed;
1941 }
1942
1943 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1944 reason = "speed/duplex";
1945 goto failed;
1946 }
1947
1948 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1949 ? DUPLEX_FULL : DUPLEX_HALF;
1950 skge->speed = yukon_speed(hw, phystat);
1951
1952 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1953 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1954 case PHY_M_PS_PAUSE_MSK:
1955 skge->flow_control = FLOW_MODE_SYMMETRIC;
1956 break;
1957 case PHY_M_PS_RX_P_EN:
1958 skge->flow_control = FLOW_MODE_REM_SEND;
1959 break;
1960 case PHY_M_PS_TX_P_EN:
1961 skge->flow_control = FLOW_MODE_LOC_SEND;
1962 break;
1963 default:
1964 skge->flow_control = FLOW_MODE_NONE;
1965 }
1966
1967 if (skge->flow_control == FLOW_MODE_NONE ||
1968 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
1969 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1970 else
1971 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1972 yukon_link_up(skge);
1973 return;
1974 }
1975
1976 if (istatus & PHY_M_IS_LSP_CHANGE)
1977 skge->speed = yukon_speed(hw, phystat);
1978
1979 if (istatus & PHY_M_IS_DUP_CHANGE)
1980 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1981 if (istatus & PHY_M_IS_LST_CHANGE) {
1982 if (phystat & PHY_M_PS_LINK_UP)
1983 yukon_link_up(skge);
1984 else
1985 yukon_link_down(skge);
1986 }
1987 return;
1988 failed:
1989 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
1990 skge->netdev->name, reason);
1991
1992 /* XXX restart autonegotiation? */
1993 }
1994
1995 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
1996 {
1997 u32 end;
1998
1999 start /= 8;
2000 len /= 8;
2001 end = start + len - 1;
2002
2003 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2004 skge_write32(hw, RB_ADDR(q, RB_START), start);
2005 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2006 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2007 skge_write32(hw, RB_ADDR(q, RB_END), end);
2008
2009 if (q == Q_R1 || q == Q_R2) {
2010 /* Set thresholds on receive queue's */
2011 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2012 start + (2*len)/3);
2013 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2014 start + (len/3));
2015 } else {
2016 /* Enable store & forward on Tx queue's because
2017 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2018 */
2019 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2020 }
2021
2022 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2023 }
2024
2025 /* Setup Bus Memory Interface */
2026 static void skge_qset(struct skge_port *skge, u16 q,
2027 const struct skge_element *e)
2028 {
2029 struct skge_hw *hw = skge->hw;
2030 u32 watermark = 0x600;
2031 u64 base = skge->dma + (e->desc - skge->mem);
2032
2033 /* optimization to reduce window on 32bit/33mhz */
2034 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2035 watermark /= 2;
2036
2037 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2038 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2039 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2040 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2041 }
2042
2043 static int skge_up(struct net_device *dev)
2044 {
2045 struct skge_port *skge = netdev_priv(dev);
2046 struct skge_hw *hw = skge->hw;
2047 int port = skge->port;
2048 u32 chunk, ram_addr;
2049 size_t rx_size, tx_size;
2050 int err;
2051
2052 if (netif_msg_ifup(skge))
2053 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2054
2055 if (dev->mtu > RX_BUF_SIZE)
2056 skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;
2057 else
2058 skge->rx_buf_size = RX_BUF_SIZE;
2059
2060
2061 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2062 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2063 skge->mem_size = tx_size + rx_size;
2064 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2065 if (!skge->mem)
2066 return -ENOMEM;
2067
2068 memset(skge->mem, 0, skge->mem_size);
2069
2070 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2071 goto free_pci_mem;
2072
2073 err = skge_rx_fill(skge);
2074 if (err)
2075 goto free_rx_ring;
2076
2077 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2078 skge->dma + rx_size)))
2079 goto free_rx_ring;
2080
2081 skge->tx_avail = skge->tx_ring.count - 1;
2082
2083 /* Enable IRQ from port */
2084 hw->intr_mask |= portirqmask[port];
2085 skge_write32(hw, B0_IMSK, hw->intr_mask);
2086
2087 /* Initialze MAC */
2088 spin_lock_bh(&hw->phy_lock);
2089 if (hw->chip_id == CHIP_ID_GENESIS)
2090 genesis_mac_init(hw, port);
2091 else
2092 yukon_mac_init(hw, port);
2093 spin_unlock_bh(&hw->phy_lock);
2094
2095 /* Configure RAMbuffers */
2096 chunk = hw->ram_size / ((hw->ports + 1)*2);
2097 ram_addr = hw->ram_offset + 2 * chunk * port;
2098
2099 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2100 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2101
2102 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2103 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2104 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2105
2106 /* Start receiver BMU */
2107 wmb();
2108 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2109 skge_led(skge, LED_MODE_ON);
2110
2111 pr_debug("skge_up completed\n");
2112 return 0;
2113
2114 free_rx_ring:
2115 skge_rx_clean(skge);
2116 kfree(skge->rx_ring.start);
2117 free_pci_mem:
2118 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2119
2120 return err;
2121 }
2122
2123 static int skge_down(struct net_device *dev)
2124 {
2125 struct skge_port *skge = netdev_priv(dev);
2126 struct skge_hw *hw = skge->hw;
2127 int port = skge->port;
2128
2129 if (netif_msg_ifdown(skge))
2130 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2131
2132 netif_stop_queue(dev);
2133
2134 /* Stop transmitter */
2135 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2136 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2137 RB_RST_SET|RB_DIS_OP_MD);
2138
2139 if (hw->chip_id == CHIP_ID_GENESIS)
2140 genesis_stop(skge);
2141 else
2142 yukon_stop(skge);
2143
2144 /* Disable Force Sync bit and Enable Alloc bit */
2145 skge_write8(hw, SK_REG(port, TXA_CTRL),
2146 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2147
2148 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2149 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2150 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2151
2152 /* Reset PCI FIFO */
2153 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2154 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2155
2156 /* Reset the RAM Buffer async Tx queue */
2157 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2158 /* stop receiver */
2159 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2160 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2161 RB_RST_SET|RB_DIS_OP_MD);
2162 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2163
2164 if (hw->chip_id == CHIP_ID_GENESIS) {
2165 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2166 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2167 } else {
2168 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2169 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2170 }
2171
2172 skge_led(skge, LED_MODE_OFF);
2173
2174 skge_tx_clean(skge);
2175 skge_rx_clean(skge);
2176
2177 kfree(skge->rx_ring.start);
2178 kfree(skge->tx_ring.start);
2179 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2180 return 0;
2181 }
2182
2183 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2184 {
2185 struct skge_port *skge = netdev_priv(dev);
2186 struct skge_hw *hw = skge->hw;
2187 struct skge_ring *ring = &skge->tx_ring;
2188 struct skge_element *e;
2189 struct skge_tx_desc *td;
2190 int i;
2191 u32 control, len;
2192 u64 map;
2193 unsigned long flags;
2194
2195 skb = skb_padto(skb, ETH_ZLEN);
2196 if (!skb)
2197 return NETDEV_TX_OK;
2198
2199 local_irq_save(flags);
2200 if (!spin_trylock(&skge->tx_lock)) {
2201 /* Collision - tell upper layer to requeue */
2202 local_irq_restore(flags);
2203 return NETDEV_TX_LOCKED;
2204 }
2205
2206 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
2207 netif_stop_queue(dev);
2208 spin_unlock_irqrestore(&skge->tx_lock, flags);
2209
2210 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2211 dev->name);
2212 return NETDEV_TX_BUSY;
2213 }
2214
2215 e = ring->to_use;
2216 td = e->desc;
2217 e->skb = skb;
2218 len = skb_headlen(skb);
2219 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2220 pci_unmap_addr_set(e, mapaddr, map);
2221 pci_unmap_len_set(e, maplen, len);
2222
2223 td->dma_lo = map;
2224 td->dma_hi = map >> 32;
2225
2226 if (skb->ip_summed == CHECKSUM_HW) {
2227 const struct iphdr *ip
2228 = (const struct iphdr *) (skb->data + ETH_HLEN);
2229 int offset = skb->h.raw - skb->data;
2230
2231 /* This seems backwards, but it is what the sk98lin
2232 * does. Looks like hardware is wrong?
2233 */
2234 if (ip->protocol == IPPROTO_UDP
2235 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2236 control = BMU_TCP_CHECK;
2237 else
2238 control = BMU_UDP_CHECK;
2239
2240 td->csum_offs = 0;
2241 td->csum_start = offset;
2242 td->csum_write = offset + skb->csum;
2243 } else
2244 control = BMU_CHECK;
2245
2246 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2247 control |= BMU_EOF| BMU_IRQ_EOF;
2248 else {
2249 struct skge_tx_desc *tf = td;
2250
2251 control |= BMU_STFWD;
2252 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2253 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2254
2255 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2256 frag->size, PCI_DMA_TODEVICE);
2257
2258 e = e->next;
2259 e->skb = NULL;
2260 tf = e->desc;
2261 tf->dma_lo = map;
2262 tf->dma_hi = (u64) map >> 32;
2263 pci_unmap_addr_set(e, mapaddr, map);
2264 pci_unmap_len_set(e, maplen, frag->size);
2265
2266 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2267 }
2268 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2269 }
2270 /* Make sure all the descriptors written */
2271 wmb();
2272 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2273 wmb();
2274
2275 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2276
2277 if (netif_msg_tx_queued(skge))
2278 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2279 dev->name, e - ring->start, skb->len);
2280
2281 ring->to_use = e->next;
2282 skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2283 if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2284 pr_debug("%s: transmit queue full\n", dev->name);
2285 netif_stop_queue(dev);
2286 }
2287
2288 dev->trans_start = jiffies;
2289 spin_unlock_irqrestore(&skge->tx_lock, flags);
2290
2291 return NETDEV_TX_OK;
2292 }
2293
2294 static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2295 {
2296 /* This ring element can be skb or fragment */
2297 if (e->skb) {
2298 pci_unmap_single(hw->pdev,
2299 pci_unmap_addr(e, mapaddr),
2300 pci_unmap_len(e, maplen),
2301 PCI_DMA_TODEVICE);
2302 dev_kfree_skb_any(e->skb);
2303 e->skb = NULL;
2304 } else {
2305 pci_unmap_page(hw->pdev,
2306 pci_unmap_addr(e, mapaddr),
2307 pci_unmap_len(e, maplen),
2308 PCI_DMA_TODEVICE);
2309 }
2310 }
2311
2312 static void skge_tx_clean(struct skge_port *skge)
2313 {
2314 struct skge_ring *ring = &skge->tx_ring;
2315 struct skge_element *e;
2316 unsigned long flags;
2317
2318 spin_lock_irqsave(&skge->tx_lock, flags);
2319 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2320 ++skge->tx_avail;
2321 skge_tx_free(skge->hw, e);
2322 }
2323 ring->to_clean = e;
2324 spin_unlock_irqrestore(&skge->tx_lock, flags);
2325 }
2326
2327 static void skge_tx_timeout(struct net_device *dev)
2328 {
2329 struct skge_port *skge = netdev_priv(dev);
2330
2331 if (netif_msg_timer(skge))
2332 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2333
2334 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2335 skge_tx_clean(skge);
2336 }
2337
2338 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2339 {
2340 int err = 0;
2341 int running = netif_running(dev);
2342
2343 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2344 return -EINVAL;
2345
2346
2347 if (running)
2348 skge_down(dev);
2349 dev->mtu = new_mtu;
2350 if (running)
2351 skge_up(dev);
2352
2353 return err;
2354 }
2355
2356 static void genesis_set_multicast(struct net_device *dev)
2357 {
2358 struct skge_port *skge = netdev_priv(dev);
2359 struct skge_hw *hw = skge->hw;
2360 int port = skge->port;
2361 int i, count = dev->mc_count;
2362 struct dev_mc_list *list = dev->mc_list;
2363 u32 mode;
2364 u8 filter[8];
2365
2366 pr_debug("genesis_set_multicast flags=%x count=%d\n", dev->flags, dev->mc_count);
2367
2368 mode = xm_read32(hw, port, XM_MODE);
2369 mode |= XM_MD_ENA_HASH;
2370 if (dev->flags & IFF_PROMISC)
2371 mode |= XM_MD_ENA_PROM;
2372 else
2373 mode &= ~XM_MD_ENA_PROM;
2374
2375 if (dev->flags & IFF_ALLMULTI)
2376 memset(filter, 0xff, sizeof(filter));
2377 else {
2378 memset(filter, 0, sizeof(filter));
2379 for (i = 0; list && i < count; i++, list = list->next) {
2380 u32 crc, bit;
2381 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2382 bit = ~crc & 0x3f;
2383 filter[bit/8] |= 1 << (bit%8);
2384 }
2385 }
2386
2387 xm_write32(hw, port, XM_MODE, mode);
2388 xm_outhash(hw, port, XM_HSM, filter);
2389 }
2390
2391 static void yukon_set_multicast(struct net_device *dev)
2392 {
2393 struct skge_port *skge = netdev_priv(dev);
2394 struct skge_hw *hw = skge->hw;
2395 int port = skge->port;
2396 struct dev_mc_list *list = dev->mc_list;
2397 u16 reg;
2398 u8 filter[8];
2399
2400 memset(filter, 0, sizeof(filter));
2401
2402 reg = gma_read16(hw, port, GM_RX_CTRL);
2403 reg |= GM_RXCR_UCF_ENA;
2404
2405 if (dev->flags & IFF_PROMISC) /* promiscious */
2406 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2407 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2408 memset(filter, 0xff, sizeof(filter));
2409 else if (dev->mc_count == 0) /* no multicast */
2410 reg &= ~GM_RXCR_MCF_ENA;
2411 else {
2412 int i;
2413 reg |= GM_RXCR_MCF_ENA;
2414
2415 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2416 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2417 filter[bit/8] |= 1 << (bit%8);
2418 }
2419 }
2420
2421
2422 gma_write16(hw, port, GM_MC_ADDR_H1,
2423 (u16)filter[0] | ((u16)filter[1] << 8));
2424 gma_write16(hw, port, GM_MC_ADDR_H2,
2425 (u16)filter[2] | ((u16)filter[3] << 8));
2426 gma_write16(hw, port, GM_MC_ADDR_H3,
2427 (u16)filter[4] | ((u16)filter[5] << 8));
2428 gma_write16(hw, port, GM_MC_ADDR_H4,
2429 (u16)filter[6] | ((u16)filter[7] << 8));
2430
2431 gma_write16(hw, port, GM_RX_CTRL, reg);
2432 }
2433
2434 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2435 {
2436 if (hw->chip_id == CHIP_ID_GENESIS)
2437 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2438 else
2439 return (status & GMR_FS_ANY_ERR) ||
2440 (status & GMR_FS_RX_OK) == 0;
2441 }
2442
2443 static void skge_rx_error(struct skge_port *skge, int slot,
2444 u32 control, u32 status)
2445 {
2446 if (netif_msg_rx_err(skge))
2447 printk(KERN_DEBUG PFX "%s: rx err, slot %d control 0x%x status 0x%x\n",
2448 skge->netdev->name, slot, control, status);
2449
2450 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2451 skge->net_stats.rx_length_errors++;
2452 else if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2453 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2454 skge->net_stats.rx_length_errors++;
2455 if (status & XMR_FS_FRA_ERR)
2456 skge->net_stats.rx_frame_errors++;
2457 if (status & XMR_FS_FCS_ERR)
2458 skge->net_stats.rx_crc_errors++;
2459 } else {
2460 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2461 skge->net_stats.rx_length_errors++;
2462 if (status & GMR_FS_FRAGMENT)
2463 skge->net_stats.rx_frame_errors++;
2464 if (status & GMR_FS_CRC_ERR)
2465 skge->net_stats.rx_crc_errors++;
2466 }
2467 }
2468
2469 /* Get receive buffer from descriptor.
2470 * Handles copy of small buffers and reallocation failures
2471 */
2472 static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2473 struct skge_element *e,
2474 unsigned int len)
2475 {
2476 struct sk_buff *nskb, *skb;
2477
2478 if (len < RX_COPY_THRESHOLD) {
2479 nskb = skge_rx_alloc(skge->netdev, len + NET_IP_ALIGN);
2480 if (unlikely(!nskb))
2481 return NULL;
2482
2483 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2484 pci_unmap_addr(e, mapaddr),
2485 len, PCI_DMA_FROMDEVICE);
2486 memcpy(nskb->data, e->skb->data, len);
2487 pci_dma_sync_single_for_device(skge->hw->pdev,
2488 pci_unmap_addr(e, mapaddr),
2489 len, PCI_DMA_FROMDEVICE);
2490
2491 if (skge->rx_csum) {
2492 struct skge_rx_desc *rd = e->desc;
2493 nskb->csum = le16_to_cpu(rd->csum2);
2494 nskb->ip_summed = CHECKSUM_HW;
2495 }
2496 skge_rx_reuse(e, skge->rx_buf_size);
2497 return nskb;
2498 } else {
2499 nskb = skge_rx_alloc(skge->netdev, skge->rx_buf_size);
2500 if (unlikely(!nskb))
2501 return NULL;
2502
2503 pci_unmap_single(skge->hw->pdev,
2504 pci_unmap_addr(e, mapaddr),
2505 pci_unmap_len(e, maplen),
2506 PCI_DMA_FROMDEVICE);
2507 skb = e->skb;
2508 if (skge->rx_csum) {
2509 struct skge_rx_desc *rd = e->desc;
2510 skb->csum = le16_to_cpu(rd->csum2);
2511 skb->ip_summed = CHECKSUM_HW;
2512 }
2513
2514 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2515 return skb;
2516 }
2517 }
2518
2519
2520 static int skge_poll(struct net_device *dev, int *budget)
2521 {
2522 struct skge_port *skge = netdev_priv(dev);
2523 struct skge_hw *hw = skge->hw;
2524 struct skge_ring *ring = &skge->rx_ring;
2525 struct skge_element *e;
2526 unsigned int to_do = min(dev->quota, *budget);
2527 unsigned int work_done = 0;
2528
2529 pr_debug("skge_poll\n");
2530
2531 for (e = ring->to_clean; work_done < to_do; e = e->next) {
2532 struct skge_rx_desc *rd = e->desc;
2533 struct sk_buff *skb;
2534 u32 control, len, status;
2535
2536 rmb();
2537 control = rd->control;
2538 if (control & BMU_OWN)
2539 break;
2540
2541 len = control & BMU_BBC;
2542 status = rd->status;
2543
2544 if (unlikely((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)
2545 || bad_phy_status(hw, status))) {
2546 skge_rx_error(skge, e - ring->start, control, status);
2547 skge_rx_reuse(e, skge->rx_buf_size);
2548 continue;
2549 }
2550
2551 if (netif_msg_rx_status(skge))
2552 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2553 dev->name, e - ring->start, rd->status, len);
2554
2555 skb = skge_rx_get(skge, e, len);
2556 if (likely(skb)) {
2557 skb_put(skb, len);
2558 skb->protocol = eth_type_trans(skb, dev);
2559
2560 dev->last_rx = jiffies;
2561 netif_receive_skb(skb);
2562
2563 ++work_done;
2564 } else
2565 skge_rx_reuse(e, skge->rx_buf_size);
2566 }
2567 ring->to_clean = e;
2568
2569 /* restart receiver */
2570 wmb();
2571 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
2572 CSR_START | CSR_IRQ_CL_F);
2573
2574 *budget -= work_done;
2575 dev->quota -= work_done;
2576
2577 if (work_done >= to_do)
2578 return 1; /* not done */
2579
2580 local_irq_disable();
2581 __netif_rx_complete(dev);
2582 hw->intr_mask |= portirqmask[skge->port];
2583 skge_write32(hw, B0_IMSK, hw->intr_mask);
2584 local_irq_enable();
2585 return 0;
2586 }
2587
2588 static inline void skge_tx_intr(struct net_device *dev)
2589 {
2590 struct skge_port *skge = netdev_priv(dev);
2591 struct skge_hw *hw = skge->hw;
2592 struct skge_ring *ring = &skge->tx_ring;
2593 struct skge_element *e;
2594
2595 spin_lock(&skge->tx_lock);
2596 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2597 struct skge_tx_desc *td = e->desc;
2598 u32 control;
2599
2600 rmb();
2601 control = td->control;
2602 if (control & BMU_OWN)
2603 break;
2604
2605 if (unlikely(netif_msg_tx_done(skge)))
2606 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
2607 dev->name, e - ring->start, td->status);
2608
2609 skge_tx_free(hw, e);
2610 e->skb = NULL;
2611 ++skge->tx_avail;
2612 }
2613 ring->to_clean = e;
2614 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2615
2616 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2617 netif_wake_queue(dev);
2618
2619 spin_unlock(&skge->tx_lock);
2620 }
2621
2622 /* Parity errors seem to happen when Genesis is connected to a switch
2623 * with no other ports present. Heartbeat error??
2624 */
2625 static void skge_mac_parity(struct skge_hw *hw, int port)
2626 {
2627 struct net_device *dev = hw->dev[port];
2628
2629 if (dev) {
2630 struct skge_port *skge = netdev_priv(dev);
2631 ++skge->net_stats.tx_heartbeat_errors;
2632 }
2633
2634 if (hw->chip_id == CHIP_ID_GENESIS)
2635 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
2636 MFF_CLR_PERR);
2637 else
2638 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
2639 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
2640 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
2641 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2642 }
2643
2644 static void skge_pci_clear(struct skge_hw *hw)
2645 {
2646 u16 status;
2647
2648 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2649 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2650 pci_write_config_word(hw->pdev, PCI_STATUS,
2651 status | PCI_STATUS_ERROR_BITS);
2652 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2653 }
2654
2655 static void skge_mac_intr(struct skge_hw *hw, int port)
2656 {
2657 if (hw->chip_id == CHIP_ID_GENESIS)
2658 genesis_mac_intr(hw, port);
2659 else
2660 yukon_mac_intr(hw, port);
2661 }
2662
2663 /* Handle device specific framing and timeout interrupts */
2664 static void skge_error_irq(struct skge_hw *hw)
2665 {
2666 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2667
2668 if (hw->chip_id == CHIP_ID_GENESIS) {
2669 /* clear xmac errors */
2670 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
2671 skge_write16(hw, SK_REG(0, RX_MFF_CTRL1), MFF_CLR_INSTAT);
2672 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
2673 skge_write16(hw, SK_REG(0, RX_MFF_CTRL2), MFF_CLR_INSTAT);
2674 } else {
2675 /* Timestamp (unused) overflow */
2676 if (hwstatus & IS_IRQ_TIST_OV)
2677 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2678 }
2679
2680 if (hwstatus & IS_RAM_RD_PAR) {
2681 printk(KERN_ERR PFX "Ram read data parity error\n");
2682 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2683 }
2684
2685 if (hwstatus & IS_RAM_WR_PAR) {
2686 printk(KERN_ERR PFX "Ram write data parity error\n");
2687 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2688 }
2689
2690 if (hwstatus & IS_M1_PAR_ERR)
2691 skge_mac_parity(hw, 0);
2692
2693 if (hwstatus & IS_M2_PAR_ERR)
2694 skge_mac_parity(hw, 1);
2695
2696 if (hwstatus & IS_R1_PAR_ERR)
2697 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2698
2699 if (hwstatus & IS_R2_PAR_ERR)
2700 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2701
2702 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2703 printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2704 hwstatus);
2705
2706 skge_pci_clear(hw);
2707
2708 /* if error still set then just ignore it */
2709 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2710 if (hwstatus & IS_IRQ_STAT) {
2711 pr_debug("IRQ status %x: still set ignoring hardware errors\n",
2712 hwstatus);
2713 hw->intr_mask &= ~IS_HW_ERR;
2714 }
2715 }
2716 }
2717
2718 /*
2719 * Interrrupt from PHY are handled in tasklet (soft irq)
2720 * because accessing phy registers requires spin wait which might
2721 * cause excess interrupt latency.
2722 */
2723 static void skge_extirq(unsigned long data)
2724 {
2725 struct skge_hw *hw = (struct skge_hw *) data;
2726 int port;
2727
2728 spin_lock(&hw->phy_lock);
2729 for (port = 0; port < 2; port++) {
2730 struct net_device *dev = hw->dev[port];
2731
2732 if (dev && netif_running(dev)) {
2733 struct skge_port *skge = netdev_priv(dev);
2734
2735 if (hw->chip_id != CHIP_ID_GENESIS)
2736 yukon_phy_intr(skge);
2737 else
2738 bcom_phy_intr(skge);
2739 }
2740 }
2741 spin_unlock(&hw->phy_lock);
2742
2743 local_irq_disable();
2744 hw->intr_mask |= IS_EXT_REG;
2745 skge_write32(hw, B0_IMSK, hw->intr_mask);
2746 local_irq_enable();
2747 }
2748
2749 static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2750 {
2751 struct skge_hw *hw = dev_id;
2752 u32 status = skge_read32(hw, B0_SP_ISRC);
2753
2754 if (status == 0 || status == ~0) /* hotplug or shared irq */
2755 return IRQ_NONE;
2756
2757 status &= hw->intr_mask;
2758 if (status & IS_R1_F) {
2759 hw->intr_mask &= ~IS_R1_F;
2760 netif_rx_schedule(hw->dev[0]);
2761 }
2762
2763 if (status & IS_R2_F) {
2764 hw->intr_mask &= ~IS_R2_F;
2765 netif_rx_schedule(hw->dev[1]);
2766 }
2767
2768 if (status & IS_XA1_F)
2769 skge_tx_intr(hw->dev[0]);
2770
2771 if (status & IS_XA2_F)
2772 skge_tx_intr(hw->dev[1]);
2773
2774 if (status & IS_PA_TO_RX1) {
2775 struct skge_port *skge = netdev_priv(hw->dev[0]);
2776 ++skge->net_stats.rx_over_errors;
2777 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2778 }
2779
2780 if (status & IS_PA_TO_RX2) {
2781 struct skge_port *skge = netdev_priv(hw->dev[1]);
2782 ++skge->net_stats.rx_over_errors;
2783 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2784 }
2785
2786 if (status & IS_PA_TO_TX1)
2787 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2788
2789 if (status & IS_PA_TO_TX2)
2790 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2791
2792 if (status & IS_MAC1)
2793 skge_mac_intr(hw, 0);
2794
2795 if (status & IS_MAC2)
2796 skge_mac_intr(hw, 1);
2797
2798 if (status & IS_HW_ERR)
2799 skge_error_irq(hw);
2800
2801 if (status & IS_EXT_REG) {
2802 hw->intr_mask &= ~IS_EXT_REG;
2803 tasklet_schedule(&hw->ext_tasklet);
2804 }
2805
2806 skge_write32(hw, B0_IMSK, hw->intr_mask);
2807
2808 return IRQ_HANDLED;
2809 }
2810
2811 #ifdef CONFIG_NET_POLL_CONTROLLER
2812 static void skge_netpoll(struct net_device *dev)
2813 {
2814 struct skge_port *skge = netdev_priv(dev);
2815
2816 disable_irq(dev->irq);
2817 skge_intr(dev->irq, skge->hw, NULL);
2818 enable_irq(dev->irq);
2819 }
2820 #endif
2821
2822 static int skge_set_mac_address(struct net_device *dev, void *p)
2823 {
2824 struct skge_port *skge = netdev_priv(dev);
2825 struct sockaddr *addr = p;
2826 int err = 0;
2827
2828 if (!is_valid_ether_addr(addr->sa_data))
2829 return -EADDRNOTAVAIL;
2830
2831 skge_down(dev);
2832 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2833 memcpy_toio(skge->hw->regs + B2_MAC_1 + skge->port*8,
2834 dev->dev_addr, ETH_ALEN);
2835 memcpy_toio(skge->hw->regs + B2_MAC_2 + skge->port*8,
2836 dev->dev_addr, ETH_ALEN);
2837 if (dev->flags & IFF_UP)
2838 err = skge_up(dev);
2839 return err;
2840 }
2841
2842 static const struct {
2843 u8 id;
2844 const char *name;
2845 } skge_chips[] = {
2846 { CHIP_ID_GENESIS, "Genesis" },
2847 { CHIP_ID_YUKON, "Yukon" },
2848 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2849 { CHIP_ID_YUKON_LP, "Yukon-LP"},
2850 };
2851
2852 static const char *skge_board_name(const struct skge_hw *hw)
2853 {
2854 int i;
2855 static char buf[16];
2856
2857 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2858 if (skge_chips[i].id == hw->chip_id)
2859 return skge_chips[i].name;
2860
2861 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2862 return buf;
2863 }
2864
2865
2866 /*
2867 * Setup the board data structure, but don't bring up
2868 * the port(s)
2869 */
2870 static int skge_reset(struct skge_hw *hw)
2871 {
2872 u16 ctst;
2873 u8 t8, mac_cfg, pmd_type, phy_type;
2874 int i;
2875
2876 ctst = skge_read16(hw, B0_CTST);
2877
2878 /* do a SW reset */
2879 skge_write8(hw, B0_CTST, CS_RST_SET);
2880 skge_write8(hw, B0_CTST, CS_RST_CLR);
2881
2882 /* clear PCI errors, if any */
2883 skge_pci_clear(hw);
2884
2885 skge_write8(hw, B0_CTST, CS_MRST_CLR);
2886
2887 /* restore CLK_RUN bits (for Yukon-Lite) */
2888 skge_write16(hw, B0_CTST,
2889 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
2890
2891 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
2892 phy_type = skge_read8(hw, B2_E_1) & 0xf;
2893 pmd_type = skge_read8(hw, B2_PMD_TYP);
2894 hw->copper = (pmd_type == 'T' || pmd_type == '1');
2895
2896 switch (hw->chip_id) {
2897 case CHIP_ID_GENESIS:
2898 switch (phy_type) {
2899 case SK_PHY_BCOM:
2900 hw->phy_addr = PHY_ADDR_BCOM;
2901 break;
2902 default:
2903 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
2904 pci_name(hw->pdev), phy_type);
2905 return -EOPNOTSUPP;
2906 }
2907 break;
2908
2909 case CHIP_ID_YUKON:
2910 case CHIP_ID_YUKON_LITE:
2911 case CHIP_ID_YUKON_LP:
2912 if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
2913 hw->copper = 1;
2914
2915 hw->phy_addr = PHY_ADDR_MARV;
2916 break;
2917
2918 default:
2919 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2920 pci_name(hw->pdev), hw->chip_id);
2921 return -EOPNOTSUPP;
2922 }
2923
2924 mac_cfg = skge_read8(hw, B2_MAC_CFG);
2925 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
2926 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
2927
2928 /* read the adapters RAM size */
2929 t8 = skge_read8(hw, B2_E_0);
2930 if (hw->chip_id == CHIP_ID_GENESIS) {
2931 if (t8 == 3) {
2932 /* special case: 4 x 64k x 36, offset = 0x80000 */
2933 hw->ram_size = 0x100000;
2934 hw->ram_offset = 0x80000;
2935 } else
2936 hw->ram_size = t8 * 512;
2937 }
2938 else if (t8 == 0)
2939 hw->ram_size = 0x20000;
2940 else
2941 hw->ram_size = t8 * 4096;
2942
2943 hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
2944 if (hw->chip_id == CHIP_ID_GENESIS)
2945 genesis_init(hw);
2946 else {
2947 /* switch power to VCC (WA for VAUX problem) */
2948 skge_write8(hw, B0_POWER_CTRL,
2949 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
2950 /* avoid boards with stuck Hardware error bits */
2951 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
2952 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
2953 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
2954 hw->intr_mask &= ~IS_HW_ERR;
2955 }
2956
2957 for (i = 0; i < hw->ports; i++) {
2958 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2959 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2960 }
2961 }
2962
2963 /* turn off hardware timer (unused) */
2964 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
2965 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2966 skge_write8(hw, B0_LED, LED_STAT_ON);
2967
2968 /* enable the Tx Arbiters */
2969 for (i = 0; i < hw->ports; i++)
2970 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2971
2972 /* Initialize ram interface */
2973 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
2974
2975 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
2976 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
2977 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
2978 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
2979 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
2980 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
2981 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
2982 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
2983 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
2984 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
2985 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
2986 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
2987
2988 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
2989
2990 /* Set interrupt moderation for Transmit only
2991 * Receive interrupts avoided by NAPI
2992 */
2993 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
2994 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
2995 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
2996
2997 skge_write32(hw, B0_IMSK, hw->intr_mask);
2998
2999 if (hw->chip_id != CHIP_ID_GENESIS)
3000 skge_write8(hw, GMAC_IRQ_MSK, 0);
3001
3002 spin_lock_bh(&hw->phy_lock);
3003 for (i = 0; i < hw->ports; i++) {
3004 if (hw->chip_id == CHIP_ID_GENESIS)
3005 genesis_reset(hw, i);
3006 else
3007 yukon_reset(hw, i);
3008 }
3009 spin_unlock_bh(&hw->phy_lock);
3010
3011 return 0;
3012 }
3013
3014 /* Initialize network device */
3015 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3016 int highmem)
3017 {
3018 struct skge_port *skge;
3019 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3020
3021 if (!dev) {
3022 printk(KERN_ERR "skge etherdev alloc failed");
3023 return NULL;
3024 }
3025
3026 SET_MODULE_OWNER(dev);
3027 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3028 dev->open = skge_up;
3029 dev->stop = skge_down;
3030 dev->hard_start_xmit = skge_xmit_frame;
3031 dev->get_stats = skge_get_stats;
3032 if (hw->chip_id == CHIP_ID_GENESIS)
3033 dev->set_multicast_list = genesis_set_multicast;
3034 else
3035 dev->set_multicast_list = yukon_set_multicast;
3036
3037 dev->set_mac_address = skge_set_mac_address;
3038 dev->change_mtu = skge_change_mtu;
3039 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3040 dev->tx_timeout = skge_tx_timeout;
3041 dev->watchdog_timeo = TX_WATCHDOG;
3042 dev->poll = skge_poll;
3043 dev->weight = NAPI_WEIGHT;
3044 #ifdef CONFIG_NET_POLL_CONTROLLER
3045 dev->poll_controller = skge_netpoll;
3046 #endif
3047 dev->irq = hw->pdev->irq;
3048 dev->features = NETIF_F_LLTX;
3049 if (highmem)
3050 dev->features |= NETIF_F_HIGHDMA;
3051
3052 skge = netdev_priv(dev);
3053 skge->netdev = dev;
3054 skge->hw = hw;
3055 skge->msg_enable = netif_msg_init(debug, default_msg);
3056 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3057 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3058
3059 /* Auto speed and flow control */
3060 skge->autoneg = AUTONEG_ENABLE;
3061 skge->flow_control = FLOW_MODE_SYMMETRIC;
3062 skge->duplex = -1;
3063 skge->speed = -1;
3064 skge->advertising = skge_supported_modes(hw);
3065
3066 hw->dev[port] = dev;
3067
3068 skge->port = port;
3069
3070 spin_lock_init(&skge->tx_lock);
3071
3072 if (hw->chip_id != CHIP_ID_GENESIS) {
3073 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3074 skge->rx_csum = 1;
3075 }
3076
3077 /* read the mac address */
3078 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3079
3080 /* device is off until link detection */
3081 netif_carrier_off(dev);
3082 netif_stop_queue(dev);
3083
3084 return dev;
3085 }
3086
3087 static void __devinit skge_show_addr(struct net_device *dev)
3088 {
3089 const struct skge_port *skge = netdev_priv(dev);
3090
3091 if (netif_msg_probe(skge))
3092 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3093 dev->name,
3094 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3095 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3096 }
3097
3098 static int __devinit skge_probe(struct pci_dev *pdev,
3099 const struct pci_device_id *ent)
3100 {
3101 struct net_device *dev, *dev1;
3102 struct skge_hw *hw;
3103 int err, using_dac = 0;
3104
3105 if ((err = pci_enable_device(pdev))) {
3106 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3107 pci_name(pdev));
3108 goto err_out;
3109 }
3110
3111 if ((err = pci_request_regions(pdev, DRV_NAME))) {
3112 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3113 pci_name(pdev));
3114 goto err_out_disable_pdev;
3115 }
3116
3117 pci_set_master(pdev);
3118
3119 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)))
3120 using_dac = 1;
3121 else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3122 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3123 pci_name(pdev));
3124 goto err_out_free_regions;
3125 }
3126
3127 #ifdef __BIG_ENDIAN
3128 /* byte swap decriptors in hardware */
3129 {
3130 u32 reg;
3131
3132 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3133 reg |= PCI_REV_DESC;
3134 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3135 }
3136 #endif
3137
3138 err = -ENOMEM;
3139 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
3140 if (!hw) {
3141 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3142 pci_name(pdev));
3143 goto err_out_free_regions;
3144 }
3145
3146 memset(hw, 0, sizeof(*hw));
3147 hw->pdev = pdev;
3148 spin_lock_init(&hw->phy_lock);
3149 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3150
3151 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3152 if (!hw->regs) {
3153 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3154 pci_name(pdev));
3155 goto err_out_free_hw;
3156 }
3157
3158 if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3159 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3160 pci_name(pdev), pdev->irq);
3161 goto err_out_iounmap;
3162 }
3163 pci_set_drvdata(pdev, hw);
3164
3165 err = skge_reset(hw);
3166 if (err)
3167 goto err_out_free_irq;
3168
3169 printk(KERN_INFO PFX "addr 0x%lx irq %d chip %s rev %d\n",
3170 pci_resource_start(pdev, 0), pdev->irq,
3171 skge_board_name(hw), hw->chip_rev);
3172
3173 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
3174 goto err_out_led_off;
3175
3176 if ((err = register_netdev(dev))) {
3177 printk(KERN_ERR PFX "%s: cannot register net device\n",
3178 pci_name(pdev));
3179 goto err_out_free_netdev;
3180 }
3181
3182 skge_show_addr(dev);
3183
3184 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
3185 if (register_netdev(dev1) == 0)
3186 skge_show_addr(dev1);
3187 else {
3188 /* Failure to register second port need not be fatal */
3189 printk(KERN_WARNING PFX "register of second port failed\n");
3190 hw->dev[1] = NULL;
3191 free_netdev(dev1);
3192 }
3193 }
3194
3195 return 0;
3196
3197 err_out_free_netdev:
3198 free_netdev(dev);
3199 err_out_led_off:
3200 skge_write16(hw, B0_LED, LED_STAT_OFF);
3201 err_out_free_irq:
3202 free_irq(pdev->irq, hw);
3203 err_out_iounmap:
3204 iounmap(hw->regs);
3205 err_out_free_hw:
3206 kfree(hw);
3207 err_out_free_regions:
3208 pci_release_regions(pdev);
3209 err_out_disable_pdev:
3210 pci_disable_device(pdev);
3211 pci_set_drvdata(pdev, NULL);
3212 err_out:
3213 return err;
3214 }
3215
3216 static void __devexit skge_remove(struct pci_dev *pdev)
3217 {
3218 struct skge_hw *hw = pci_get_drvdata(pdev);
3219 struct net_device *dev0, *dev1;
3220
3221 if (!hw)
3222 return;
3223
3224 if ((dev1 = hw->dev[1]))
3225 unregister_netdev(dev1);
3226 dev0 = hw->dev[0];
3227 unregister_netdev(dev0);
3228
3229 tasklet_kill(&hw->ext_tasklet);
3230
3231 free_irq(pdev->irq, hw);
3232 pci_release_regions(pdev);
3233 pci_disable_device(pdev);
3234 if (dev1)
3235 free_netdev(dev1);
3236 free_netdev(dev0);
3237 skge_write16(hw, B0_LED, LED_STAT_OFF);
3238 iounmap(hw->regs);
3239 kfree(hw);
3240 pci_set_drvdata(pdev, NULL);
3241 }
3242
3243 #ifdef CONFIG_PM
3244 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3245 {
3246 struct skge_hw *hw = pci_get_drvdata(pdev);
3247 int i, wol = 0;
3248
3249 for (i = 0; i < 2; i++) {
3250 struct net_device *dev = hw->dev[i];
3251
3252 if (dev) {
3253 struct skge_port *skge = netdev_priv(dev);
3254 if (netif_running(dev)) {
3255 netif_carrier_off(dev);
3256 skge_down(dev);
3257 }
3258 netif_device_detach(dev);
3259 wol |= skge->wol;
3260 }
3261 }
3262
3263 pci_save_state(pdev);
3264 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3265 pci_disable_device(pdev);
3266 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3267
3268 return 0;
3269 }
3270
3271 static int skge_resume(struct pci_dev *pdev)
3272 {
3273 struct skge_hw *hw = pci_get_drvdata(pdev);
3274 int i;
3275
3276 pci_set_power_state(pdev, PCI_D0);
3277 pci_restore_state(pdev);
3278 pci_enable_wake(pdev, PCI_D0, 0);
3279
3280 skge_reset(hw);
3281
3282 for (i = 0; i < 2; i++) {
3283 struct net_device *dev = hw->dev[i];
3284 if (dev) {
3285 netif_device_attach(dev);
3286 if (netif_running(dev))
3287 skge_up(dev);
3288 }
3289 }
3290 return 0;
3291 }
3292 #endif
3293
3294 static struct pci_driver skge_driver = {
3295 .name = DRV_NAME,
3296 .id_table = skge_id_table,
3297 .probe = skge_probe,
3298 .remove = __devexit_p(skge_remove),
3299 #ifdef CONFIG_PM
3300 .suspend = skge_suspend,
3301 .resume = skge_resume,
3302 #endif
3303 };
3304
3305 static int __init skge_init_module(void)
3306 {
3307 return pci_module_init(&skge_driver);
3308 }
3309
3310 static void __exit skge_cleanup_module(void)
3311 {
3312 pci_unregister_driver(&skge_driver);
3313 }
3314
3315 module_init(skge_init_module);
3316 module_exit(skge_cleanup_module);
Linux with added FPC-III support