arch/arc/plat-hsdk/platform.c

   1 /*
   2  * ARC HSDK Platform support code
   3  *
   4  * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/smp.h>
  13 #include <asm/arcregs.h>
  14 #include <asm/io.h>
  15 #include <asm/mach_desc.h>
  16
  17 #define ARC_CCM_UNUSED_ADDR     0x60000000
  18
  19 static void __init hsdk_init_per_cpu(unsigned int cpu)
  20 {
  21         /*
  22          * By default ICCM is mapped to 0x7z while this area is used for
  23          * kernel virtual mappings, so move it to currently unused area.
  24          */
  25         if (cpuinfo_arc700[cpu].iccm.sz)
  26                 write_aux_reg(ARC_REG_AUX_ICCM, ARC_CCM_UNUSED_ADDR);
  27
  28         /*
  29          * By default DCCM is mapped to 0x8z while this area is used by kernel,
  30          * so move it to currently unused area.
  31          */
  32         if (cpuinfo_arc700[cpu].dccm.sz)
  33                 write_aux_reg(ARC_REG_AUX_DCCM, ARC_CCM_UNUSED_ADDR);
  34 }
  35
  36 #define ARC_PERIPHERAL_BASE     0xf0000000
  37 #define CREG_BASE               (ARC_PERIPHERAL_BASE + 0x1000)
  38 #define CREG_PAE                (CREG_BASE + 0x180)
  39 #define CREG_PAE_UPDATE         (CREG_BASE + 0x194)
  40
  41 #define CREG_CORE_IF_CLK_DIV    (CREG_BASE + 0x4B8)
  42 #define CREG_CORE_IF_CLK_DIV_2  0x1
  43 #define CGU_BASE                ARC_PERIPHERAL_BASE
  44 #define CGU_PLL_STATUS          (ARC_PERIPHERAL_BASE + 0x4)
  45 #define CGU_PLL_CTRL            (ARC_PERIPHERAL_BASE + 0x0)
  46 #define CGU_PLL_STATUS_LOCK     BIT(0)
  47 #define CGU_PLL_STATUS_ERR      BIT(1)
  48 #define CGU_PLL_CTRL_1GHZ       0x3A10
  49 #define HSDK_PLL_LOCK_TIMEOUT   500
  50
  51 #define HSDK_PLL_LOCKED() \
  52         !!(ioread32((void __iomem *) CGU_PLL_STATUS) & CGU_PLL_STATUS_LOCK)
  53
  54 #define HSDK_PLL_ERR() \
  55         !!(ioread32((void __iomem *) CGU_PLL_STATUS) & CGU_PLL_STATUS_ERR)
  56
  57 static void __init hsdk_set_cpu_freq_1ghz(void)
  58 {
  59         u32 timeout = HSDK_PLL_LOCK_TIMEOUT;
  60
  61         /*
  62          * As we set cpu clock which exceeds 500MHz, the divider for the interface
  63          * clock must be programmed to div-by-2.
  64          */
  65         iowrite32(CREG_CORE_IF_CLK_DIV_2, (void __iomem *) CREG_CORE_IF_CLK_DIV);
  66
  67         /* Set cpu clock to 1GHz */
  68         iowrite32(CGU_PLL_CTRL_1GHZ, (void __iomem *) CGU_PLL_CTRL);
  69
  70         while (!HSDK_PLL_LOCKED() && timeout--)
  71                 cpu_relax();
  72
  73         if (!HSDK_PLL_LOCKED() || HSDK_PLL_ERR())
  74                 pr_err("Failed to setup CPU frequency to 1GHz!");
  75 }
  76
  77 #define SDIO_BASE               (ARC_PERIPHERAL_BASE + 0xA000)
  78 #define SDIO_UHS_REG_EXT        (SDIO_BASE + 0x108)
  79 #define SDIO_UHS_REG_EXT_DIV_2  (2 << 30)
  80
  81 static void __init hsdk_init_early(void)
  82 {
  83         /*
  84          * PAE remapping for DMA clients does not work due to an RTL bug, so
  85          * CREG_PAE register must be programmed to all zeroes, otherwise it
  86          * will cause problems with DMA to/from peripherals even if PAE40 is
  87          * not used.
  88          */
  89
  90         /* Default is 1, which means "PAE offset = 4GByte" */
  91         writel_relaxed(0, (void __iomem *) CREG_PAE);
  92
  93         /* Really apply settings made above */
  94         writel(1, (void __iomem *) CREG_PAE_UPDATE);
  95
  96         /*
  97          * Switch SDIO external ciu clock divider from default div-by-8 to
  98          * minimum possible div-by-2.
  99          */
 100         iowrite32(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *) SDIO_UHS_REG_EXT);
 101
 102         /*
 103          * Setup CPU frequency to 1GHz.
 104          * TODO: remove it after smart hsdk pll driver will be introduced.
 105          */
 106         hsdk_set_cpu_freq_1ghz();
 107 }
 108
 109 static const char *hsdk_compat[] __initconst = {
 110         "snps,hsdk",
 111         NULL,
 112 };
 113
 114 MACHINE_START(SIMULATION, "hsdk")
 115         .dt_compat      = hsdk_compat,
 116         .init_early     = hsdk_init_early,
 117         .init_per_cpu   = hsdk_init_per_cpu,
 118 MACHINE_END