arch/arm/boot/dts/armada-xp-98dx3236.dtsi

   1 /*
   2  * Device Tree Include file for Marvell 98dx3236 family SoC
   3  *
   4  * Copyright (C) 2016 Allied Telesis Labs
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  *
  44  * Contains definitions specific to the 98dx3236 SoC that are not
  45  * common to all Armada XP SoCs.
  46  */
  47
  48 #include "armada-370-xp.dtsi"
  49
  50 / {
  51         #address-cells = <2>;
  52         #size-cells = <2>;
  53
  54         model = "Marvell 98DX3236 SoC";
  55         compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
  56
  57         aliases {
  58                 gpio0 = &gpio0;
  59                 gpio1 = &gpio1;
  60                 gpio2 = &gpio2;
  61         };
  62
  63         cpus {
  64                 #address-cells = <1>;
  65                 #size-cells = <0>;
  66                 enable-method = "marvell,98dx3236-smp";
  67
  68                 cpu@0 {
  69                         device_type = "cpu";
  70                         compatible = "marvell,sheeva-v7";
  71                         reg = <0>;
  72                         clocks = <&cpuclk 0>;
  73                         clock-latency = <1000000>;
  74                 };
  75         };
  76
  77         soc {
  78                 compatible = "marvell,armadaxp-mbus", "simple-bus";
  79
  80                 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
  81                           MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
  82                           MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
  83                           MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
  84                           MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
  85
  86                 bootrom {
  87                         compatible = "marvell,bootrom";
  88                         reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
  89                 };
  90
  91                 /*
  92                  * 98DX3236 has 1 x1 PCIe unit Gen2.0
  93                  */
  94                 pciec: pcie@82000000 {
  95                         compatible = "marvell,armada-xp-pcie";
  96                         status = "disabled";
  97                         device_type = "pci";
  98
  99                         #address-cells = <3>;
 100                         #size-cells = <2>;
 101
 102                         msi-parent = <&mpic>;
 103                         bus-range = <0x00 0xff>;
 104
 105                         ranges =
 106                                <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
 107                                 0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
 108                                 0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */>;
 109
 110                         pcie1: pcie@1,0 {
 111                                 device_type = "pci";
 112                                 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
 113                                 reg = <0x0800 0 0 0 0>;
 114                                 #address-cells = <3>;
 115                                 #size-cells = <2>;
 116                                 #interrupt-cells = <1>;
 117                                 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
 118                                           0x81000000 0 0 0x81000000 0x1 0 1 0>;
 119                                 bus-range = <0x00 0xff>;
 120                                 interrupt-map-mask = <0 0 0 0>;
 121                                 interrupt-map = <0 0 0 0 &mpic 58>;
 122                                 marvell,pcie-port = <0>;
 123                                 marvell,pcie-lane = <0>;
 124                                 clocks = <&gateclk 5>;
 125                                 status = "disabled";
 126                         };
 127                 };
 128
 129                 internal-regs {
 130                         sdramc@1400 {
 131                                 compatible = "marvell,armada-xp-sdram-controller";
 132                                 reg = <0x1400 0x500>;
 133                         };
 134
 135                         L2: l2-cache@8000 {
 136                                 compatible = "marvell,aurora-system-cache";
 137                                 reg = <0x08000 0x1000>;
 138                                 cache-id-part = <0x100>;
 139                                 cache-level = <2>;
 140                                 cache-unified;
 141                                 wt-override;
 142                         };
 143
 144                         gpio0: gpio@18100 {
 145                                 compatible = "marvell,orion-gpio";
 146                                 reg = <0x18100 0x40>;
 147                                 ngpios = <32>;
 148                                 gpio-controller;
 149                                 #gpio-cells = <2>;
 150                                 interrupt-controller;
 151                                 #interrupt-cells = <2>;
 152                                 interrupts = <82>, <83>, <84>, <85>;
 153                         };
 154
 155                         /* does not exist */
 156                         gpio1: gpio@18140 {
 157                                 compatible = "marvell,orion-gpio";
 158                                 reg = <0x18140 0x40>;
 159                                 status = "disabled";
 160                         };
 161
 162                         gpio2: gpio@18180 { /* rework some properties */
 163                                 compatible = "marvell,orion-gpio";
 164                                 reg = <0x18180 0x40>;
 165                                 ngpios = <1>; /* only gpio #32 */
 166                                 gpio-controller;
 167                                 #gpio-cells = <2>;
 168                                 interrupt-controller;
 169                                 #interrupt-cells = <2>;
 170                                 interrupts = <87>;
 171                         };
 172
 173                         systemc: system-controller@18200 {
 174                                 compatible = "marvell,armada-370-xp-system-controller";
 175                                 reg = <0x18200 0x500>;
 176                         };
 177
 178                         gateclk: clock-gating-control@18220 {
 179                                 compatible = "marvell,mv98dx3236-gating-clock";
 180                                 reg = <0x18220 0x4>;
 181                                 clocks = <&coreclk 0>;
 182                                 #clock-cells = <1>;
 183                         };
 184
 185                         cpuclk: clock-complex@18700 {
 186                                 #clock-cells = <1>;
 187                                 compatible = "marvell,mv98dx3236-cpu-clock";
 188                                 reg = <0x18700 0x24>, <0x1c054 0x10>;
 189                                 clocks = <&coreclk 1>;
 190                         };
 191
 192                         corediv-clock@18740 {
 193                                 status = "disabled";
 194                         };
 195
 196                         cpu-config@21000 {
 197                                 compatible = "marvell,armada-xp-cpu-config";
 198                                 reg = <0x21000 0x8>;
 199                         };
 200
 201                         ethernet@70000 {
 202                                 compatible = "marvell,armada-xp-neta";
 203                         };
 204
 205                         ethernet@74000 {
 206                                 compatible = "marvell,armada-xp-neta";
 207                         };
 208
 209                         xor1: xor@f0800 {
 210                                 compatible = "marvell,orion-xor";
 211                                 reg = <0xf0800 0x100
 212                                        0xf0a00 0x100>;
 213                                 clocks = <&gateclk 22>;
 214                                 status = "okay";
 215
 216                                 xor10 {
 217                                         interrupts = <51>;
 218                                         dmacap,memcpy;
 219                                         dmacap,xor;
 220                                 };
 221                                 xor11 {
 222                                         interrupts = <52>;
 223                                         dmacap,memcpy;
 224                                         dmacap,xor;
 225                                         dmacap,memset;
 226                                 };
 227                         };
 228
 229                         nand: nand@d0000 {
 230                                 clocks = <&dfx_coredivclk 0>;
 231                         };
 232
 233                         xor0: xor@f0900 {
 234                                 compatible = "marvell,orion-xor";
 235                                 reg = <0xF0900 0x100
 236                                        0xF0B00 0x100>;
 237                                 clocks = <&gateclk 28>;
 238                                 status = "okay";
 239
 240                                 xor00 {
 241                                         interrupts = <94>;
 242                                         dmacap,memcpy;
 243                                         dmacap,xor;
 244                                 };
 245                                 xor01 {
 246                                         interrupts = <95>;
 247                                         dmacap,memcpy;
 248                                         dmacap,xor;
 249                                         dmacap,memset;
 250                                 };
 251                         };
 252                 };
 253
 254                 dfx: dfx-server@ac000000 {
 255                         compatible = "marvell,dfx-server", "simple-bus";
 256                         #address-cells = <1>;
 257                         #size-cells = <1>;
 258                         ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
 259                         reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
 260
 261                         coreclk: mvebu-sar@f8204 {
 262                                 compatible = "marvell,mv98dx3236-core-clock";
 263                                 reg = <0xf8204 0x4>;
 264                                 #clock-cells = <1>;
 265                         };
 266
 267                         dfx_coredivclk: corediv-clock@f8268 {
 268                                 compatible = "marvell,mv98dx3236-corediv-clock";
 269                                 reg = <0xf8268 0xc>;
 270                                 #clock-cells = <1>;
 271                                 clocks = <&mainpll>;
 272                                 clock-output-names = "nand";
 273                         };
 274                 };
 275
 276                 switch: switch@a8000000 {
 277                         compatible = "simple-bus";
 278                         #address-cells = <1>;
 279                         #size-cells = <1>;
 280                         ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
 281
 282                         pp0: packet-processor@0 {
 283                                 compatible = "marvell,prestera-98dx3236";
 284                                 reg = <0 0x4000000>;
 285                                 interrupts = <33>, <34>, <35>;
 286                                 dfx = <&dfx>;
 287                         };
 288                 };
 289         };
 290
 291         clocks {
 292                 /* 25 MHz reference crystal */
 293                 refclk: oscillator {
 294                         compatible = "fixed-clock";
 295                         #clock-cells = <0>;
 296                         clock-frequency = <25000000>;
 297                 };
 298         };
 299 };
 300
 301 &i2c0 {
 302         compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
 303         reg = <0x11000 0x100>;
 304 };
 305
 306 &i2c1 {
 307         compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
 308         reg = <0x11100 0x100>;
 309 };
 310
 311 &mpic {
 312         reg = <0x20a00 0x2d0>, <0x21070 0x58>;
 313 };
 314
 315 &rtc {
 316         status = "disabled";
 317 };
 318
 319 &timer {
 320         compatible = "marvell,armada-xp-timer";
 321         clocks = <&coreclk 2>, <&refclk>;
 322         clock-names = "nbclk", "fixed";
 323 };
 324
 325 &watchdog {
 326         compatible = "marvell,armada-xp-wdt";
 327         clocks = <&coreclk 2>, <&refclk>;
 328         clock-names = "nbclk", "fixed";
 329 };
 330
 331 &cpurst {
 332         reg = <0x20800 0x20>;
 333 };
 334
 335 &usb0 {
 336         clocks = <&gateclk 18>;
 337 };
 338
 339 &usb1 {
 340         clocks = <&gateclk 19>;
 341 };
 342
 343 &pinctrl {
 344         compatible = "marvell,98dx3236-pinctrl";
 345
 346         spi0_pins: spi0-pins {
 347                 marvell,pins = "mpp0", "mpp1",
 348                                "mpp2", "mpp3";
 349                 marvell,function = "spi0";
 350         };
 351 };
 352
 353 &spi0 {
 354         compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
 355         pinctrl-0 = <&spi0_pins>;
 356         pinctrl-names = "default";
 357 };
 358
 359 &sdio {
 360         status = "disabled";
 361 };
 362