mm: fix exec activate_mm vs TLB shootdown and lazy tlb switching race
[linux/fpc-iii.git] / arch / arm / boot / dts / imx51-apf51dev.dts
bloba5e6091c8729968beef3bd4279c325a3212a5ca8
1 /*
2  * Copyright 2013 Armadeus Systems - <support@armadeus.com>
3  *
4  * The code contained herein is licensed under the GNU General Public
5  * License. You may obtain a copy of the GNU General Public License
6  * Version 2 or later at the following locations:
7  *
8  * http://www.opensource.org/licenses/gpl-license.html
9  * http://www.gnu.org/copyleft/gpl.html
10  */
12 /* APF51Dev is a docking board for the APF51 SOM */
13 #include "imx51-apf51.dts"
15 / {
16         model = "Armadeus Systems APF51Dev docking/development board";
17         compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51";
19         backlight@bl1{
20                 pinctrl-names = "default";
21                 pinctrl-0 = <&pinctrl_backlight>;
22                 compatible = "gpio-backlight";
23                 gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
24                 default-on;
25         };
27         display@di1 {
28                 compatible = "fsl,imx-parallel-display";
29                 interface-pix-fmt = "bgr666";
30                 pinctrl-names = "default";
31                 pinctrl-0 = <&pinctrl_ipu_disp1>;
33                 display-timings {
34                         lw700 {
35                                 native-mode;
36                                 clock-frequency = <33000033>;
37                                 hactive = <800>;
38                                 vactive = <480>;
39                                 hback-porch = <96>;
40                                 hfront-porch = <96>;
41                                 vback-porch = <20>;
42                                 vfront-porch = <21>;
43                                 hsync-len = <64>;
44                                 vsync-len = <4>;
45                                 hsync-active = <1>;
46                                 vsync-active = <1>;
47                                 de-active = <1>;
48                                 pixelclk-active = <0>;
49                         };
50                 };
52                 port {
53                         display_in: endpoint {
54                                 remote-endpoint = <&ipu_di0_disp0>;
55                         };
56                 };
57         };
59         gpio-keys {
60                 compatible = "gpio-keys";
62                 user-key {
63                         label = "user";
64                         gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
65                         linux,code = <256>; /* BTN_0 */
66                 };
67         };
69         leds {
70                 compatible = "gpio-leds";
72                 user {
73                         label = "Heartbeat";
74                         gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
75                         linux,default-trigger = "heartbeat";
76                 };
77         };
80 &ecspi1 {
81         pinctrl-names = "default";
82         pinctrl-0 = <&pinctrl_ecspi1>;
83         cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
84                    <&gpio4 25 GPIO_ACTIVE_HIGH>;
85         status = "okay";
88 &ecspi2 {
89         pinctrl-names = "default";
90         pinctrl-0 = <&pinctrl_ecspi2>;
91         cs-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>,
92                    <&gpio3 27 GPIO_ACTIVE_LOW>;
93         status = "okay";
96 &esdhc1 {
97         pinctrl-names = "default";
98         pinctrl-0 = <&pinctrl_esdhc1>;
99         cd-gpios = <&gpio2 29 GPIO_ACTIVE_LOW>;
100         bus-width = <4>;
101         status = "okay";
104 &esdhc2 {
105         pinctrl-names = "default";
106         pinctrl-0 = <&pinctrl_esdhc2>;
107         bus-width = <4>;
108         non-removable;
109         status = "okay";
112 &i2c2 {
113         pinctrl-names = "default";
114         pinctrl-0 = <&pinctrl_i2c2>;
115         status = "okay";
118 &iomuxc {
119         pinctrl-names = "default";
120         pinctrl-0 = <&pinctrl_hog>;
122         imx51-apf51dev {
123                 pinctrl_backlight: bl1grp {
124                         fsl,pins = <
125                                 MX51_PAD_DI1_D1_CS__GPIO3_4 0x1F5
126                         >;
127                 };
129                 pinctrl_hog: hoggrp {
130                         fsl,pins = <
131                                 MX51_PAD_EIM_EB2__GPIO2_22   0x0C5
132                                 MX51_PAD_EIM_EB3__GPIO2_23   0x0C5
133                                 MX51_PAD_EIM_CS4__GPIO2_29   0x100
134                                 MX51_PAD_NANDF_D13__GPIO3_27 0x0C5
135                                 MX51_PAD_NANDF_D12__GPIO3_28 0x0C5
136                                 MX51_PAD_CSPI1_SS0__GPIO4_24 0x0C5
137                                 MX51_PAD_CSPI1_SS1__GPIO4_25 0x0C5
138                                 MX51_PAD_GPIO1_2__GPIO1_2    0x0C5
139                                 MX51_PAD_GPIO1_3__GPIO1_3    0x0C5
140                         >;
141                 };
143                 pinctrl_ecspi1: ecspi1grp {
144                         fsl,pins = <
145                                 MX51_PAD_CSPI1_MISO__ECSPI1_MISO        0x185
146                                 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI        0x185
147                                 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK        0x185
148                         >;
149                 };
151                 pinctrl_ecspi2: ecspi2grp {
152                         fsl,pins = <
153                                 MX51_PAD_NANDF_RB3__ECSPI2_MISO         0x185
154                                 MX51_PAD_NANDF_D15__ECSPI2_MOSI         0x185
155                                 MX51_PAD_NANDF_RB2__ECSPI2_SCLK         0x185
156                         >;
157                 };
159                 pinctrl_esdhc1: esdhc1grp {
160                         fsl,pins = <
161                                 MX51_PAD_SD1_CMD__SD1_CMD               0x400020d5
162                                 MX51_PAD_SD1_CLK__SD1_CLK               0x20d5
163                                 MX51_PAD_SD1_DATA0__SD1_DATA0           0x20d5
164                                 MX51_PAD_SD1_DATA1__SD1_DATA1           0x20d5
165                                 MX51_PAD_SD1_DATA2__SD1_DATA2           0x20d5
166                                 MX51_PAD_SD1_DATA3__SD1_DATA3           0x20d5
167                         >;
168                 };
170                 pinctrl_esdhc2: esdhc2grp {
171                         fsl,pins = <
172                                 MX51_PAD_SD2_CMD__SD2_CMD               0x400020d5
173                                 MX51_PAD_SD2_CLK__SD2_CLK               0x20d5
174                                 MX51_PAD_SD2_DATA0__SD2_DATA0           0x20d5
175                                 MX51_PAD_SD2_DATA1__SD2_DATA1           0x20d5
176                                 MX51_PAD_SD2_DATA2__SD2_DATA2           0x20d5
177                                 MX51_PAD_SD2_DATA3__SD2_DATA3           0x20d5
178                         >;
179                 };
181                 pinctrl_i2c2: i2c2grp {
182                         fsl,pins = <
183                                 MX51_PAD_EIM_D27__I2C2_SCL              0x400001ed
184                                 MX51_PAD_EIM_D24__I2C2_SDA              0x400001ed
185                         >;
186                 };
188                 pinctrl_ipu_disp1: ipudisp1grp {
189                         fsl,pins = <
190                                 MX51_PAD_DISP1_DAT0__DISP1_DAT0         0x5
191                                 MX51_PAD_DISP1_DAT1__DISP1_DAT1         0x5
192                                 MX51_PAD_DISP1_DAT2__DISP1_DAT2         0x5
193                                 MX51_PAD_DISP1_DAT3__DISP1_DAT3         0x5
194                                 MX51_PAD_DISP1_DAT4__DISP1_DAT4         0x5
195                                 MX51_PAD_DISP1_DAT5__DISP1_DAT5         0x5
196                                 MX51_PAD_DISP1_DAT6__DISP1_DAT6         0x5
197                                 MX51_PAD_DISP1_DAT7__DISP1_DAT7         0x5
198                                 MX51_PAD_DISP1_DAT8__DISP1_DAT8         0x5
199                                 MX51_PAD_DISP1_DAT9__DISP1_DAT9         0x5
200                                 MX51_PAD_DISP1_DAT10__DISP1_DAT10       0x5
201                                 MX51_PAD_DISP1_DAT11__DISP1_DAT11       0x5
202                                 MX51_PAD_DISP1_DAT12__DISP1_DAT12       0x5
203                                 MX51_PAD_DISP1_DAT13__DISP1_DAT13       0x5
204                                 MX51_PAD_DISP1_DAT14__DISP1_DAT14       0x5
205                                 MX51_PAD_DISP1_DAT15__DISP1_DAT15       0x5
206                                 MX51_PAD_DISP1_DAT16__DISP1_DAT16       0x5
207                                 MX51_PAD_DISP1_DAT17__DISP1_DAT17       0x5
208                                 MX51_PAD_DISP1_DAT18__DISP1_DAT18       0x5
209                                 MX51_PAD_DISP1_DAT19__DISP1_DAT19       0x5
210                                 MX51_PAD_DISP1_DAT20__DISP1_DAT20       0x5
211                                 MX51_PAD_DISP1_DAT21__DISP1_DAT21       0x5
212                                 MX51_PAD_DISP1_DAT22__DISP1_DAT22       0x5
213                                 MX51_PAD_DISP1_DAT23__DISP1_DAT23       0x5
214                                 MX51_PAD_DI1_PIN2__DI1_PIN2             0x5
215                                 MX51_PAD_DI1_PIN3__DI1_PIN3             0x5
216                         >;
217                 };
218         };
221 &ipu_di0_disp0 {
222         remote-endpoint = <&display_in>;