mm: fix exec activate_mm vs TLB shootdown and lazy tlb switching race
[linux/fpc-iii.git] / arch / arm / boot / dts / imx6q-novena.dts
blobd83cfb6ec598993831d5447fb89803107fe45edc
1 /*
2  * Copyright 2015 Sutajio Ko-Usagi PTE LTD
3  *
4  * This file is dual-licensed: you can use it either under the terms
5  * of the GPL or the X11 license, at your option. Note that this dual
6  * licensing only applies to this file, and not this project as a
7  * whole.
8  *
9  *  a) This file is free software; you can redistribute it and/or
10  *     modify it under the terms of the GNU General Public License as
11  *     published by the Free Software Foundation; either version 2 of
12  *     the License, or (at your option) any later version.
13  *
14  *     This file is distributed in the hope that it will be useful,
15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  *     GNU General Public License for more details.
18  *
19  *     You should have received a copy of the GNU General Public
20  *     License along with this file; if not, write to the Free
21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22  *     MA 02110-1301 USA
23  *
24  * Or, alternatively,
25  *
26  *  b) Permission is hereby granted, free of charge, to any person
27  *     obtaining a copy of this software and associated documentation
28  *     files (the "Software"), to deal in the Software without
29  *     restriction, including without limitation the rights to use,
30  *     copy, modify, merge, publish, distribute, sublicense, and/or
31  *     sell copies of the Software, and to permit persons to whom the
32  *     Software is furnished to do so, subject to the following
33  *     conditions:
34  *
35  *     The above copyright notice and this permission notice shall be
36  *     included in all copies or substantial portions of the Software.
37  *
38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45  *     OTHER DEALINGS IN THE SOFTWARE.
46  *
47  */
49 /dts-v1/;
50 #include "imx6q.dtsi"
51 #include <dt-bindings/gpio/gpio.h>
52 #include <dt-bindings/input/input.h>
54 / {
55         model = "Kosagi Novena Dual/Quad";
56         compatible = "kosagi,imx6q-novena", "fsl,imx6q";
58         chosen {
59                 stdout-path = &uart2;
60         };
62         backlight: backlight {
63                 compatible = "pwm-backlight";
64                 pwms = <&pwm1 0 10000000>;
65                 pinctrl-names = "default";
66                 pinctrl-0 = <&pinctrl_backlight_novena>;
67                 power-supply = <&reg_lvds_lcd>;
68                 brightness-levels = <0 3 6 12 16 24 32 48 64 96 128 192 255>;
69                 default-brightness-level = <12>;
70         };
72         gpio-keys {
73                 compatible = "gpio-keys";
74                 pinctrl-names = "default";
75                 pinctrl-0 = <&pinctrl_gpio_keys_novena>;
77                 user-button {
78                         label = "User Button";
79                         gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
80                         linux,code = <KEY_POWER>;
81                 };
83                 lid {
84                         label = "Lid";
85                         gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
86                         linux,input-type = <5>; /* EV_SW */
87                         linux,code = <0>;       /* SW_LID */
88                 };
89         };
91         leds {
92                 compatible = "gpio-leds";
93                 pinctrl-names = "default";
94                 pinctrl-0 = <&pinctrl_leds_novena>;
96                 heartbeat {
97                         label = "novena:white:panel";
98                         gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
99                         linux,default-trigger = "default-on";
100                 };
101         };
103         panel: panel {
104                 compatible = "innolux,n133hse-ea1", "simple-panel";
105                 backlight = <&backlight>;
106         };
108         reg_2p5v: regulator-2p5v {
109                 compatible = "regulator-fixed";
110                 regulator-name = "2P5V";
111                 regulator-min-microvolt = <2500000>;
112                 regulator-max-microvolt = <2500000>;
113                 regulator-always-on;
114         };
116         reg_3p3v: regulator-3p3v {
117                 compatible = "regulator-fixed";
118                 regulator-name = "3P3V";
119                 regulator-min-microvolt = <3300000>;
120                 regulator-max-microvolt = <3300000>;
121                 regulator-always-on;
122         };
124         reg_audio_codec: regulator-audio-codec {
125                 compatible = "regulator-fixed";
126                 regulator-name = "es8328-power";
127                 regulator-boot-on;
128                 regulator-min-microvolt = <5000000>;
129                 regulator-max-microvolt = <5000000>;
130                 startup-delay-us = <400000>;
131                 gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
132                 enable-active-high;
133         };
135         reg_display: regulator-display {
136                 compatible = "regulator-fixed";
137                 regulator-name = "lcd-display-power";
138                 regulator-min-microvolt = <3300000>;
139                 regulator-max-microvolt = <3300000>;
140                 startup-delay-us = <200000>;
141                 gpio = <&gpio5 28 GPIO_ACTIVE_HIGH>;
142                 enable-active-high;
143         };
145         reg_lvds_lcd: regulator-lvds-lcd {
146                 compatible = "regulator-fixed";
147                 regulator-name = "lcd-lvds-power";
148                 regulator-min-microvolt = <3300000>;
149                 regulator-max-microvolt = <3300000>;
150                 gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
151                 enable-active-high;
152         };
154         reg_pcie: regulator-pcie {
155                 compatible = "regulator-fixed";
156                 regulator-name = "pcie-bus-power";
157                 regulator-min-microvolt = <1500000>;
158                 regulator-max-microvolt = <1500000>;
159                 gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
160                 enable-active-high;
161                 regulator-always-on;
162         };
164         reg_sata: regulator-sata {
165                 compatible = "regulator-fixed";
166                 regulator-name = "sata-power";
167                 regulator-boot-on;
168                 regulator-min-microvolt = <3300000>;
169                 regulator-max-microvolt = <3300000>;
170                 startup-delay-us = <10000>;
171                 gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
172                 enable-active-high;
173         };
175         reg_usb_otg_vbus: regulator-usb-otg-vbus {
176                 compatible = "regulator-fixed";
177                 regulator-name = "usb_otg_vbus";
178                 regulator-min-microvolt = <5000000>;
179                 regulator-max-microvolt = <5000000>;
180                 enable-active-high;
181         };
183         sound {
184                 compatible = "fsl,imx-audio-es8328";
185                 model = "imx-audio-es8328";
186                 ssi-controller = <&ssi1>;
187                 audio-codec = <&codec>;
188                 audio-amp-supply = <&reg_audio_codec>;
189                 jack-gpio = <&gpio5 15 GPIO_ACTIVE_HIGH>;
190                 audio-routing =
191                         "Speaker", "LOUT2",
192                         "Speaker", "ROUT2",
193                         "Speaker", "audio-amp",
194                         "Headphone", "ROUT1",
195                         "Headphone", "LOUT1",
196                         "LINPUT1", "Mic Jack",
197                         "RINPUT1", "Mic Jack",
198                         "Mic Jack", "Mic Bias";
199                 mux-int-port = <0x1>;
200                 mux-ext-port = <0x3>;
201         };
204 &audmux {
205         pinctrl-names = "default";
206         pinctrl-0 = <&pinctrl_audmux_novena>;
207         status = "okay";
210 &ecspi3 {
211         pinctrl-names = "default";
212         pinctrl-0 = <&pinctrl_ecspi3_novena>;
213         status = "okay";
216 &fec {
217         pinctrl-names = "default";
218         pinctrl-0 = <&pinctrl_enet_novena>;
219         phy-mode = "rgmii";
220         phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
221         rxc-skew-ps = <3000>;
222         rxdv-skew-ps = <0>;
223         txc-skew-ps = <3000>;
224         txen-skew-ps = <0>;
225         rxd0-skew-ps = <0>;
226         rxd1-skew-ps = <0>;
227         rxd2-skew-ps = <0>;
228         rxd3-skew-ps = <0>;
229         txd0-skew-ps = <3000>;
230         txd1-skew-ps = <3000>;
231         txd2-skew-ps = <3000>;
232         txd3-skew-ps = <3000>;
233         status = "okay";
236 &hdmi {
237         pinctrl-names = "default";
238         pinctrl-0 = <&pinctrl_hdmi_novena>;
239         ddc-i2c-bus = <&i2c2>;
240         status = "okay";
243 &i2c1 {
244         pinctrl-names = "default";
245         pinctrl-0 = <&pinctrl_i2c1_novena>;
246         status = "okay";
248         accel: mma8452@1c {
249                 compatible = "fsl,mma8452";
250                 reg = <0x1c>;
251         };
253         rtc: pcf8523@68 {
254                 compatible = "nxp,pcf8523";
255                 reg = <0x68>;
256         };
258         sbs_battery: bq20z75@0b {
259                 compatible = "sbs,sbs-battery";
260                 reg = <0x0b>;
261                 sbs,i2c-retry-count = <50>;
262         };
264         touch: stmpe811@44 {
265                 compatible = "st,stmpe811";
266                 reg = <0x44>;
267                 #address-cells = <1>;
268                 #size-cells = <0>;
269                 irq-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>;
270                 id = <0>;
271                 blocks = <0x5>;
272                 irq-trigger = <0x1>;
273                 pinctrl-names = "default";
274                 pinctrl-0 = <&pinctrl_stmpe_novena>;
275                 vio-supply = <&reg_3p3v>;
276                 vcc-supply = <&reg_3p3v>;
278                 stmpe_touchscreen {
279                         compatible = "st,stmpe-ts";
280                         st,sample-time = <4>;
281                         st,mod-12b = <1>;
282                         st,ref-sel = <0>;
283                         st,adc-freq = <1>;
284                         st,ave-ctrl = <1>;
285                         st,touch-det-delay = <2>;
286                         st,settling = <2>;
287                         st,fraction-z = <7>;
288                         st,i-drive = <1>;
289                 };
290         };
293 &i2c2 {
294         pinctrl-names = "default";
295         pinctrl-0 = <&pinctrl_i2c2_novena>;
296         status = "okay";
298         pmic: pfuze100@08 {
299                 compatible = "fsl,pfuze100";
300                 reg = <0x08>;
302                 regulators {
303                         reg_sw1a: sw1a {
304                                 regulator-min-microvolt = <300000>;
305                                 regulator-max-microvolt = <1875000>;
306                                 regulator-boot-on;
307                                 regulator-always-on;
308                                 regulator-ramp-delay = <6250>;
309                         };
311                         reg_sw1c: sw1c {
312                                 regulator-min-microvolt = <300000>;
313                                 regulator-max-microvolt = <1875000>;
314                                 regulator-boot-on;
315                                 regulator-always-on;
316                         };
318                         reg_sw2: sw2 {
319                                 regulator-min-microvolt = <800000>;
320                                 regulator-max-microvolt = <3300000>;
321                                 regulator-boot-on;
322                                 regulator-always-on;
323                         };
325                         reg_sw3a: sw3a {
326                                 regulator-min-microvolt = <400000>;
327                                 regulator-max-microvolt = <1975000>;
328                                 regulator-boot-on;
329                                 regulator-always-on;
330                         };
332                         reg_sw3b: sw3b {
333                                 regulator-min-microvolt = <400000>;
334                                 regulator-max-microvolt = <1975000>;
335                                 regulator-boot-on;
336                                 regulator-always-on;
337                         };
339                         reg_sw4: sw4 {
340                                 regulator-min-microvolt = <800000>;
341                                 regulator-max-microvolt = <3300000>;
342                         };
344                         reg_swbst: swbst {
345                                 regulator-min-microvolt = <5000000>;
346                                 regulator-max-microvolt = <5150000>;
347                                 regulator-boot-on;
348                         };
350                         reg_snvs: vsnvs {
351                                 regulator-min-microvolt = <1000000>;
352                                 regulator-max-microvolt = <3000000>;
353                                 regulator-boot-on;
354                                 regulator-always-on;
355                         };
357                         reg_vref: vrefddr {
358                                 regulator-boot-on;
359                                 regulator-always-on;
360                         };
362                         reg_vgen1: vgen1 {
363                                 regulator-min-microvolt = <800000>;
364                                 regulator-max-microvolt = <1550000>;
365                         };
367                         reg_vgen2: vgen2 {
368                                 regulator-min-microvolt = <800000>;
369                                 regulator-max-microvolt = <1550000>;
370                         };
372                         reg_vgen3: vgen3 {
373                                 regulator-min-microvolt = <1800000>;
374                                 regulator-max-microvolt = <3300000>;
375                         };
377                         reg_vgen4: vgen4 {
378                                 regulator-min-microvolt = <1800000>;
379                                 regulator-max-microvolt = <3300000>;
380                                 regulator-always-on;
381                         };
383                         reg_vgen5: vgen5 {
384                                 regulator-min-microvolt = <1800000>;
385                                 regulator-max-microvolt = <3300000>;
386                                 regulator-always-on;
387                         };
389                         reg_vgen6: vgen6 {
390                                 regulator-min-microvolt = <1800000>;
391                                 regulator-max-microvolt = <3300000>;
392                                 regulator-always-on;
393                         };
394                 };
395         };
398 &i2c3 {
399         pinctrl-names = "default";
400         pinctrl-0 = <&pinctrl_i2c3_novena>;
401         status = "okay";
403         codec: es8328@11 {
404                 compatible = "everest,es8328";
405                 reg = <0x11>;
406                 DVDD-supply = <&reg_audio_codec>;
407                 AVDD-supply = <&reg_audio_codec>;
408                 PVDD-supply = <&reg_audio_codec>;
409                 HPVDD-supply = <&reg_audio_codec>;
410                 pinctrl-names = "default";
411                 pinctrl-0 = <&pinctrl_sound_novena>;
412                 clocks = <&clks IMX6QDL_CLK_CKO1>;
413                 assigned-clocks = <&clks IMX6QDL_CLK_CKO>,
414                                   <&clks IMX6QDL_CLK_CKO1_SEL>,
415                                   <&clks IMX6QDL_CLK_PLL4_AUDIO>,
416                                   <&clks IMX6QDL_CLK_CKO1>;
417                 assigned-clock-parents = <&clks IMX6QDL_CLK_CKO1>,
418                                          <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>,
419                                          <&clks IMX6QDL_CLK_OSC>,
420                                          <&clks IMX6QDL_CLK_CKO1_PODF>;
421                 assigned-clock-rates = <0 0 722534400 22579200>;
422         };
425 &kpp {
426         pinctrl-names = "default";
427         pinctrl-0 = <&pinctrl_kpp_novena>;
428         linux,keymap = <
429                 MATRIX_KEY(1, 1, KEY_CONFIG)
430         >;
431         status = "okay";
434 &ldb {
435         fsl,dual-channel;
436         status = "okay";
438         lvds-channel@0 {
439                 fsl,data-mapping = "jeida";
440                 fsl,data-width = <24>;
441                 fsl,panel = <&panel>;
442                 status = "okay";
443         };
446 &pcie {
447         pinctrl-names = "default";
448         pinctrl-0 = <&pinctrl_pcie_novena>;
449         reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>;
450         status = "okay";
453 &pwm1 {
454         status = "okay";
457 &sata {
458         target-supply = <&reg_sata>;
459         fsl,transmit-level-mV = <1025>;
460         fsl,transmit-boost-mdB = <0>;
461         fsl,transmit-atten-16ths = <8>;
462         status = "okay";
465 &ssi1 {
466         status = "okay";
469 &uart2 {
470         pinctrl-names = "default";
471         pinctrl-0 = <&pinctrl_uart2_novena>;
472         status = "okay";
475 &uart3 {
476         pinctrl-names = "default";
477         pinctrl-0 = <&pinctrl_uart3_novena>;
478         status = "okay";
481 &uart4 {
482         pinctrl-names = "default";
483         pinctrl-0 = <&pinctrl_uart4_novena>;
484         status = "okay";
487 &usbotg {
488         vbus-supply = <&reg_usb_otg_vbus>;
489         dr_mode = "otg";
490         pinctrl-names = "default";
491         pinctrl-0 = <&pinctrl_usbotg_novena>;
492         disable-over-current;
493         status = "okay";
496 &usbh1 {
497         vbus-supply = <&reg_swbst>;
498         status = "okay";
501 &usdhc2 {
502         pinctrl-names = "default";
503         pinctrl-0 = <&pinctrl_usdhc2_novena>;
504         cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
505         wp-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
506         bus-width = <4>;
507         status = "okay";
510 &usdhc3 {
511         pinctrl-names = "default";
512         pinctrl-0 = <&pinctrl_usdhc3_novena>;
513         bus-width = <4>;
514         non-removable;
515         status = "okay";
518 &iomuxc {
519         pinctrl_audmux_novena: audmuxgrp-novena {
520                 fsl,pins = <
521                         MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
522                         MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
523                         MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
524                         MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
525                 >;
526         };
528         pinctrl_backlight_novena: backlightgrp-novena {
529                 fsl,pins = <
530                         MX6QDL_PAD_DISP0_DAT8__PWM1_OUT         0x1b0b0
531                         MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28       0x1b0b1
532                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b1
533                 >;
534         };
536         pinctrl_ecspi3_novena: ecspi3grp-novena {
537                 fsl,pins = <
538                         MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
539                         MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
540                         MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
541                 >;
542         };
544         pinctrl_enet_novena: enetgrp-novena {
545                 fsl,pins = <
546                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
547                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
548                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b020
549                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b028
550                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b028
551                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b028
552                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b028
553                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b028
554                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
555                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
556                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
557                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
558                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
559                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
560                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
561                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
562                         /* Ethernet reset */
563                         MX6QDL_PAD_EIM_D23__GPIO3_IO23          0x1b0b1
564                 >;
565         };
567         pinctrl_fpga_gpio: fpgagpiogrp-novena {
568                 fsl,pins = <
569                         /* FPGA power */
570                         MX6QDL_PAD_SD1_DAT1__GPIO1_IO17         0x1b0b1
571                         /* Reset */
572                         MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07      0x1b0b1
573                         /* FPGA GPIOs */
574                         MX6QDL_PAD_EIM_DA0__GPIO3_IO00          0x1b0b1
575                         MX6QDL_PAD_EIM_DA1__GPIO3_IO01          0x1b0b1
576                         MX6QDL_PAD_EIM_DA2__GPIO3_IO02          0x1b0b1
577                         MX6QDL_PAD_EIM_DA3__GPIO3_IO03          0x1b0b1
578                         MX6QDL_PAD_EIM_DA4__GPIO3_IO04          0x1b0b1
579                         MX6QDL_PAD_EIM_DA5__GPIO3_IO05          0x1b0b1
580                         MX6QDL_PAD_EIM_DA6__GPIO3_IO06          0x1b0b1
581                         MX6QDL_PAD_EIM_DA7__GPIO3_IO07          0x1b0b1
582                         MX6QDL_PAD_EIM_DA8__GPIO3_IO08          0x1b0b1
583                         MX6QDL_PAD_EIM_DA9__GPIO3_IO09          0x1b0b1
584                         MX6QDL_PAD_EIM_DA10__GPIO3_IO10         0x1b0b1
585                         MX6QDL_PAD_EIM_DA11__GPIO3_IO11         0x1b0b1
586                         MX6QDL_PAD_EIM_DA12__GPIO3_IO12         0x1b0b1
587                         MX6QDL_PAD_EIM_DA13__GPIO3_IO13         0x1b0b1
588                         MX6QDL_PAD_EIM_DA14__GPIO3_IO14         0x1b0b1
589                         MX6QDL_PAD_EIM_DA15__GPIO3_IO15         0x1b0b1
590                         MX6QDL_PAD_EIM_A16__GPIO2_IO22          0x1b0b1
591                         MX6QDL_PAD_EIM_A17__GPIO2_IO21          0x1b0b1
592                         MX6QDL_PAD_EIM_A18__GPIO2_IO20          0x1b0b1
593                         MX6QDL_PAD_EIM_CS0__GPIO2_IO23          0x1b0b1
594                         MX6QDL_PAD_EIM_CS1__GPIO2_IO24          0x1b0b1
595                         MX6QDL_PAD_EIM_LBA__GPIO2_IO27          0x1b0b1
596                         MX6QDL_PAD_EIM_OE__GPIO2_IO25           0x1b0b1
597                         MX6QDL_PAD_EIM_RW__GPIO2_IO26           0x1b0b1
598                         MX6QDL_PAD_EIM_WAIT__GPIO5_IO00         0x1b0b1
599                         MX6QDL_PAD_EIM_BCLK__GPIO6_IO31         0x1b0b1
600                 >;
601         };
603         pinctrl_fpga_eim: fpgaeimgrp-novena {
604                 fsl,pins = <
605                         /* FPGA power */
606                         MX6QDL_PAD_SD1_DAT1__GPIO1_IO17         0x1b0b1
607                         /* Reset */
608                         MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07      0x1b0b1
609                         /* FPGA GPIOs */
610                         MX6QDL_PAD_EIM_DA0__EIM_AD00            0xb0f1
611                         MX6QDL_PAD_EIM_DA1__EIM_AD01            0xb0f1
612                         MX6QDL_PAD_EIM_DA2__EIM_AD02            0xb0f1
613                         MX6QDL_PAD_EIM_DA3__EIM_AD03            0xb0f1
614                         MX6QDL_PAD_EIM_DA4__EIM_AD04            0xb0f1
615                         MX6QDL_PAD_EIM_DA5__EIM_AD05            0xb0f1
616                         MX6QDL_PAD_EIM_DA6__EIM_AD06            0xb0f1
617                         MX6QDL_PAD_EIM_DA7__EIM_AD07            0xb0f1
618                         MX6QDL_PAD_EIM_DA8__EIM_AD08            0xb0f1
619                         MX6QDL_PAD_EIM_DA9__EIM_AD09            0xb0f1
620                         MX6QDL_PAD_EIM_DA10__EIM_AD10           0xb0f1
621                         MX6QDL_PAD_EIM_DA11__EIM_AD11           0xb0f1
622                         MX6QDL_PAD_EIM_DA12__EIM_AD12           0xb0f1
623                         MX6QDL_PAD_EIM_DA13__EIM_AD13           0xb0f1
624                         MX6QDL_PAD_EIM_DA14__EIM_AD14           0xb0f1
625                         MX6QDL_PAD_EIM_DA15__EIM_AD15           0xb0f1
626                         MX6QDL_PAD_EIM_A16__EIM_ADDR16          0xb0f1
627                         MX6QDL_PAD_EIM_A17__EIM_ADDR17          0xb0f1
628                         MX6QDL_PAD_EIM_A18__EIM_ADDR18          0xb0f1
629                         MX6QDL_PAD_EIM_CS0__EIM_CS0_B           0xb0f1
630                         MX6QDL_PAD_EIM_CS1__EIM_CS1_B           0xb0f1
631                         MX6QDL_PAD_EIM_LBA__EIM_LBA_B           0xb0f1
632                         MX6QDL_PAD_EIM_OE__EIM_OE_B             0xb0f1
633                         MX6QDL_PAD_EIM_RW__EIM_RW               0xb0f1
634                         MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B         0xb0f1
635                         MX6QDL_PAD_EIM_BCLK__EIM_BCLK           0xb0f1
636                 >;
637         };
639         pinctrl_gpio_keys_novena: gpiokeysgrp-novena {
640                 fsl,pins = <
641                         /* User button */
642                         MX6QDL_PAD_KEY_COL4__GPIO4_IO14         0x1b0b0
643                         /* PCIe Wakeup */
644                         MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1f0e0
645                         /* Lid switch */
646                         MX6QDL_PAD_KEY_COL3__GPIO4_IO12         0x1b0b0
647                 >;
648         };
650         pinctrl_hdmi_novena: hdmigrp-novena {
651                 fsl,pins = <
652                         MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE   0x1f8b0
653                         MX6QDL_PAD_EIM_A24__GPIO5_IO04          0x1b0b1
654                 >;
655         };
657         pinctrl_i2c1_novena: i2c1grp-novena {
658                 fsl,pins = <
659                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
660                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
661                 >;
662         };
664         pinctrl_i2c2_novena: i2c2grp-novena {
665                 fsl,pins = <
666                         MX6QDL_PAD_EIM_EB2__I2C2_SCL            0x4001b8b1
667                         MX6QDL_PAD_EIM_D16__I2C2_SDA            0x4001b8b1
668                 >;
669         };
671         pinctrl_i2c3_novena: i2c3grp-novena {
672                 fsl,pins = <
673                         MX6QDL_PAD_EIM_D17__I2C3_SCL            0x4001b8b1
674                         MX6QDL_PAD_EIM_D18__I2C3_SDA            0x4001b8b1
675                 >;
676         };
678         pinctrl_kpp_novena: kppgrp-novena {
679                 fsl,pins = <
680                         /* Front panel button */
681                         MX6QDL_PAD_KEY_ROW1__KEY_ROW1           0x1b0b1
682                         /* Fake column driver, not connected */
683                         MX6QDL_PAD_KEY_COL1__KEY_COL1           0x1b0b1
684                 >;
685         };
687         pinctrl_leds_novena: ledsgrp-novena {
688                 fsl,pins = <
689                         MX6QDL_PAD_SD1_DAT3__GPIO1_IO21         0x1b0b1
690                 >;
691         };
693         pinctrl_pcie_novena: pciegrp-novena {
694                 fsl,pins = <
695                         /* Reset */
696                         MX6QDL_PAD_EIM_D29__GPIO3_IO29          0x1b0b1
697                         /* Power On */
698                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x1b0b1
699                         /* Wifi kill */
700                         MX6QDL_PAD_EIM_A22__GPIO2_IO16          0x1b0b1
701                 >;
702         };
704         pinctrl_sata_novena: satagrp-novena {
705                 fsl,pins = <
706                         MX6QDL_PAD_EIM_D30__GPIO3_IO30          0x1b0b1
707                 >;
708         };
710         pinctrl_senoko_novena: senokogrp-novena {
711                 fsl,pins = <
712                         /* Senoko IRQ line */
713                         MX6QDL_PAD_SD1_CLK__GPIO1_IO20          0x13048
714                         /* Senoko reset line */
715                         MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21       0x1b0b1
716                 >;
717         };
719         pinctrl_sound_novena: soundgrp-novena {
720                 fsl,pins = <
721                         /* Audio power regulator */
722                         MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17      0x1b0b1
723                         /* Headphone plug */
724                         MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15      0x1b0b1
725                         MX6QDL_PAD_GPIO_0__CCM_CLKO1            0x000b0
726                 >;
727         };
729         pinctrl_stmpe_novena: stmpegrp-novena {
730                 fsl,pins = <
731                         /* Touchscreen interrupt */
732                         MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13      0x1b0b1
733                 >;
734         };
736         pinctrl_uart2_novena: uart2grp-novena {
737                 fsl,pins = <
738                         MX6QDL_PAD_EIM_D26__UART2_TX_DATA       0x1b0b1
739                         MX6QDL_PAD_EIM_D27__UART2_RX_DATA       0x1b0b1
740                 >;
741         };
743         pinctrl_uart3_novena: uart3grp-novena {
744                 fsl,pins = <
745                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
746                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
747                 >;
748         };
750         pinctrl_uart4_novena: uart4grp-novena {
751                 fsl,pins = <
752                         MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
753                         MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
754                 >;
755         };
757         pinctrl_usbotg_novena: usbotggrp-novena {
758                 fsl,pins = <
759                         MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
760                 >;
761         };
763         pinctrl_usdhc2_novena: usdhc2grp-novena {
764                 fsl,pins = <
765                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x170f9
766                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x100f9
767                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x170f9
768                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x170f9
769                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x170f9
770                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x170f9
771                         /* Write protect */
772                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1b0b1
773                         /* Card detect */
774                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1b0b1
775                 >;
776         };
778         pinctrl_usdhc3_novena: usdhc3grp-novena {
779                 fsl,pins = <
780                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
781                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
782                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
783                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
784                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
785                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
786                 >;
787         };