| blob | 7cae9c5e27db0b15b53dfce8ae7670b6eab2f011 |
1 /*
2 * Common base for NXP LPC18xx and LPC43xx devices.
3 *
4 * Copyright 2015 Joachim Eastwood <manabian@gmail.com>
5 *
6 * This code is released using a dual license strategy: BSD/GPL
7 * You can choose the licence that better fits your requirements.
8 *
9 * Released under the terms of 3-clause BSD License
10 * Released under the terms of GNU General Public License Version 2.0
11 *
12 */
14 #include "armv7-m.dtsi"
16 #include "dt-bindings/clock/lpc18xx-cgu.h"
17 #include "dt-bindings/clock/lpc18xx-ccu.h"
19 #define LPC_PIN(port, pin) (0x##port * 32 + pin)
20 #define LPC_GPIO(port, pin) (port * 32 + pin)
22 / {
23 #address-cells = <1>;
24 #size-cells = <1>;
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
30 cpu@0 {
31 compatible = "arm,cortex-m3";
32 device_type = "cpu";
33 reg = <0x0>;
34 clocks = <&ccu1 CLK_CPU_CORE>;
35 };
36 };
38 clocks {
39 xtal: xtal {
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
42 clock-frequency = <12000000>;
43 };
45 xtal32: xtal32 {
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
48 clock-frequency = <32768>;
49 };
51 enet_rx_clk: enet_rx_clk {
52 compatible = "fixed-clock";
53 #clock-cells = <0>;
54 clock-frequency = <0>;
55 clock-output-names = "enet_rx_clk";
56 };
58 enet_tx_clk: enet_tx_clk {
59 compatible = "fixed-clock";
60 #clock-cells = <0>;
61 clock-frequency = <0>;
62 clock-output-names = "enet_tx_clk";
63 };
65 gp_clkin: gp_clkin {
66 compatible = "fixed-clock";
67 #clock-cells = <0>;
68 clock-frequency = <0>;
69 clock-output-names = "gp_clkin";
70 };
71 };
73 soc {
74 sct_pwm: pwm@40000000 {
75 compatible = "nxp,lpc1850-sct-pwm";
76 reg = <0x40000000 0x1000>;
77 clocks =<&ccu1 CLK_CPU_SCT>;
78 clock-names = "pwm";
79 resets = <&rgu 37>;
80 #pwm-cells = <3>;
81 status = "disabled";
82 };
84 dmac: dma-controller@40002000 {
85 compatible = "arm,pl080", "arm,primecell";
86 arm,primecell-periphid = <0x00041080>;
87 reg = <0x40002000 0x1000>;
88 interrupts = <2>;
89 clocks = <&ccu1 CLK_CPU_DMA>;
90 clock-names = "apb_pclk";
91 resets = <&rgu 19>;
92 #dma-cells = <2>;
93 dma-channels = <8>;
94 dma-requests = <16>;
95 lli-bus-interface-ahb1;
96 lli-bus-interface-ahb2;
97 mem-bus-interface-ahb1;
98 mem-bus-interface-ahb2;
99 memcpy-burst-size = <256>;
100 memcpy-bus-width = <32>;
101 };
103 spifi: flash-controller@40003000 {
104 compatible = "nxp,lpc1773-spifi";
105 reg = <0x40003000 0x1000>, <0x14000000 0x4000000>;
106 reg-names = "spifi", "flash";
107 interrupts = <30>;
108 clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>;
109 clock-names = "spifi", "reg";
110 resets = <&rgu 53>;
111 status = "disabled";
112 };
114 mmcsd: mmcsd@40004000 {
115 compatible = "snps,dw-mshc";
116 reg = <0x40004000 0x1000>;
117 interrupts = <6>;
118 num-slots = <1>;
119 clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>;
120 clock-names = "ciu", "biu";
121 resets = <&rgu 20>;
122 status = "disabled";
123 };
125 usb0: ehci@40006100 {
126 compatible = "nxp,lpc1850-ehci", "generic-ehci";
127 reg = <0x40006100 0x100>;
128 interrupts = <8>;
129 clocks = <&ccu1 CLK_CPU_USB0>;
130 resets = <&rgu 17>;
131 phys = <&usb0_otg_phy>;
132 phy-names = "usb";
133 has-transaction-translator;
134 status = "disabled";
135 };
137 usb1: ehci@40007100 {
138 compatible = "nxp,lpc1850-ehci", "generic-ehci";
139 reg = <0x40007100 0x100>;
140 interrupts = <9>;
141 clocks = <&ccu1 CLK_CPU_USB1>;
142 resets = <&rgu 18>;
143 status = "disabled";
144 };
146 emc: memory-controller@40005000 {
147 compatible = "arm,pl172", "arm,primecell";
148 reg = <0x40005000 0x1000>;
149 clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;
150 clock-names = "mpmcclk", "apb_pclk";
151 resets = <&rgu 21>;
152 #address-cells = <2>;
153 #size-cells = <1>;
154 ranges = <0 0 0x1c000000 0x1000000
155 1 0 0x1d000000 0x1000000
156 2 0 0x1e000000 0x1000000
157 3 0 0x1f000000 0x1000000>;
158 status = "disabled";
159 };
161 lcdc: lcd-controller@40008000 {
162 compatible = "arm,pl111", "arm,primecell";
163 reg = <0x40008000 0x1000>;
164 interrupts = <7>;
165 interrupt-names = "combined";
166 clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
167 clock-names = "clcdclk", "apb_pclk";
168 resets = <&rgu 16>;
169 status = "disabled";
170 };
172 eeprom: eeprom@4000e000 {
173 compatible = "nxp,lpc1857-eeprom";
174 reg = <0x4000e000 0x1000>, <0x20040000 0x4000>;
175 reg-names = "reg", "mem";
176 clocks = <&ccu1 CLK_CPU_EEPROM>;
177 clock-names = "eeprom";
178 resets = <&rgu 27>;
179 interrupts = <4>;
180 status = "disabled";
181 };
183 mac: ethernet@40010000 {
184 compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";
185 reg = <0x40010000 0x2000>;
186 interrupts = <5>;
187 interrupt-names = "macirq";
188 clocks = <&ccu1 CLK_CPU_ETHERNET>;
189 clock-names = "stmmaceth";
190 resets = <&rgu 22>;
191 reset-names = "stmmaceth";
192 rx-fifo-depth = <256>;
193 tx-fifo-depth = <256>;
194 snps,pbl = <4>; /* 32 (8x mode) */
195 snps,force_thresh_dma_mode;
196 status = "disabled";
197 };
199 creg: syscon@40043000 {
200 compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
201 reg = <0x40043000 0x1000>;
202 clocks = <&ccu1 CLK_CPU_CREG>;
203 resets = <&rgu 5>;
205 creg_clk: clock-controller {
206 compatible = "nxp,lpc1850-creg-clk";
207 clocks = <&xtal32>;
208 #clock-cells = <1>;
209 };
211 usb0_otg_phy: phy {
212 compatible = "nxp,lpc1850-usb-otg-phy";
213 clocks = <&ccu1 CLK_USB0>;
214 #phy-cells = <0>;
215 };
217 dmamux: dma-mux {
218 compatible = "nxp,lpc1850-dmamux";
219 #dma-cells = <3>;
220 dma-requests = <64>;
221 dma-masters = <&dmac>;
222 };
223 };
225 rtc: rtc@40046000 {
226 compatible = "nxp,lpc1850-rtc", "nxp,lpc1788-rtc";
227 reg = <0x40046000 0x1000>;
228 interrupts = <47>;
229 clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
230 clock-names = "rtc", "reg";
231 };
233 cgu: clock-controller@40050000 {
234 compatible = "nxp,lpc1850-cgu";
235 reg = <0x40050000 0x1000>;
236 #clock-cells = <1>;
237 clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
238 };
240 ccu1: clock-controller@40051000 {
241 compatible = "nxp,lpc1850-ccu";
242 reg = <0x40051000 0x1000>;
243 #clock-cells = <1>;
244 clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
245 <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
246 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
247 <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
248 clock-names = "base_apb3_clk", "base_apb1_clk",
249 "base_spifi_clk", "base_cpu_clk",
250 "base_periph_clk", "base_usb0_clk",
251 "base_usb1_clk", "base_spi_clk";
252 };
254 ccu2: clock-controller@40052000 {
255 compatible = "nxp,lpc1850-ccu";
256 reg = <0x40052000 0x1000>;
257 #clock-cells = <1>;
258 clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
259 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
260 <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
261 <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>;
262 clock-names = "base_audio_clk", "base_uart3_clk",
263 "base_uart2_clk", "base_uart1_clk",
264 "base_uart0_clk", "base_ssp1_clk",
265 "base_ssp0_clk", "base_sdio_clk";
266 };
268 rgu: reset-controller@40053000 {
269 compatible = "nxp,lpc1850-rgu";
270 reg = <0x40053000 0x1000>;
271 clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>;
272 clock-names = "delay", "reg";
273 #reset-cells = <1>;
274 };
276 watchdog@40080000 {
277 compatible = "nxp,lpc1850-wwdt";
278 reg = <0x40080000 0x24>;
279 interrupts = <49>;
280 clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_WWDT>;
281 clock-names = "wdtclk", "reg";
282 };
284 uart0: serial@40081000 {
285 compatible = "nxp,lpc1850-uart", "ns16550a";
286 reg = <0x40081000 0x1000>;
287 reg-shift = <2>;
288 interrupts = <24>;
289 clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
290 clock-names = "uartclk", "reg";
291 resets = <&rgu 44>;
292 dmas = <&dmamux 1 1 2
293 &dmamux 2 1 2
294 &dmamux 11 2 2
295 &dmamux 12 2 2>;
296 dma-names = "tx", "rx", "tx", "rx";
297 status = "disabled";
298 };
300 uart1: serial@40082000 {
301 compatible = "nxp,lpc1850-uart", "ns16550a";
302 reg = <0x40082000 0x1000>;
303 reg-shift = <2>;
304 interrupts = <25>;
305 clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
306 clock-names = "uartclk", "reg";
307 resets = <&rgu 45>;
308 dmas = <&dmamux 3 1 2
309 &dmamux 4 1 2>;
310 dma-names = "tx", "rx";
311 status = "disabled";
312 };
314 ssp0: spi@40083000 {
315 compatible = "arm,pl022", "arm,primecell";
316 reg = <0x40083000 0x1000>;
317 interrupts = <22>;
318 clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>;
319 clock-names = "sspclk", "apb_pclk";
320 resets = <&rgu 50>;
321 dmas = <&dmamux 9 0 2
322 &dmamux 10 0 2>;
323 dma-names = "rx", "tx";
324 #address-cells = <1>;
325 #size-cells = <0>;
326 status = "disabled";
327 };
329 timer0: timer@40084000 {
330 compatible = "nxp,lpc3220-timer";
331 reg = <0x40084000 0x1000>;
332 interrupts = <12>;
333 clocks = <&ccu1 CLK_CPU_TIMER0>;
334 clock-names = "timerclk";
335 resets = <&rgu 32>;
336 };
338 timer1: timer@40085000 {
339 compatible = "nxp,lpc3220-timer";
340 reg = <0x40085000 0x1000>;
341 interrupts = <13>;
342 clocks = <&ccu1 CLK_CPU_TIMER1>;
343 clock-names = "timerclk";
344 resets = <&rgu 33>;
345 };
347 pinctrl: pinctrl@40086000 {
348 compatible = "nxp,lpc1850-scu";
349 reg = <0x40086000 0x1000>;
350 clocks = <&ccu1 CLK_CPU_SCU>;
351 };
353 i2c0: i2c@400a1000 {
354 compatible = "nxp,lpc1788-i2c";
355 reg = <0x400a1000 0x1000>;
356 interrupts = <18>;
357 clocks = <&ccu1 CLK_APB1_I2C0>;
358 resets = <&rgu 48>;
359 #address-cells = <1>;
360 #size-cells = <0>;
361 status = "disabled";
362 };
364 can1: can@400a4000 {
365 compatible = "bosch,c_can";
366 reg = <0x400a4000 0x1000>;
367 interrupts = <43>;
368 clocks = <&ccu1 CLK_APB1_CAN1>;
369 resets = <&rgu 54>;
370 status = "disabled";
371 };
373 uart2: serial@400c1000 {
374 compatible = "nxp,lpc1850-uart", "ns16550a";
375 reg = <0x400c1000 0x1000>;
376 reg-shift = <2>;
377 interrupts = <26>;
378 clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>;
379 clock-names = "uartclk", "reg";
380 resets = <&rgu 46>;
381 dmas = <&dmamux 5 1 2
382 &dmamux 6 1 2>;
383 dma-names = "tx", "rx";
384 status = "disabled";
385 };
387 uart3: serial@400c2000 {
388 compatible = "nxp,lpc1850-uart", "ns16550a";
389 reg = <0x400c2000 0x1000>;
390 reg-shift = <2>;
391 interrupts = <27>;
392 clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>;
393 clock-names = "uartclk", "reg";
394 resets = <&rgu 47>;
395 dmas = <&dmamux 7 1 2
396 &dmamux 8 1 2
397 &dmamux 13 3 2
398 &dmamux 14 3 2>;
399 dma-names = "tx", "rx", "rx", "tx";
400 status = "disabled";
401 };
403 timer2: timer@400c3000 {
404 compatible = "nxp,lpc3220-timer";
405 reg = <0x400c3000 0x1000>;
406 interrupts = <14>;
407 clocks = <&ccu1 CLK_CPU_TIMER2>;
408 clock-names = "timerclk";
409 resets = <&rgu 34>;
410 };
412 timer3: timer@400c4000 {
413 compatible = "nxp,lpc3220-timer";
414 reg = <0x400c4000 0x1000>;
415 interrupts = <15>;
416 clocks = <&ccu1 CLK_CPU_TIMER3>;
417 clock-names = "timerclk";
418 resets = <&rgu 35>;
419 };
421 ssp1: spi@400c5000 {
422 compatible = "arm,pl022", "arm,primecell";
423 reg = <0x400c5000 0x1000>;
424 interrupts = <23>;
425 clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>;
426 clock-names = "sspclk", "apb_pclk";
427 resets = <&rgu 51>;
428 dmas = <&dmamux 11 2 2
429 &dmamux 12 2 2
430 &dmamux 3 3 2
431 &dmamux 4 3 2
432 &dmamux 5 2 2
433 &dmamux 6 2 2
434 &dmamux 13 2 2
435 &dmamux 14 2 2>;
436 dma-names = "rx", "tx", "tx", "rx",
437 "tx", "rx", "rx", "tx";
438 #address-cells = <1>;
439 #size-cells = <0>;
440 status = "disabled";
441 };
443 i2c1: i2c@400e0000 {
444 compatible = "nxp,lpc1788-i2c";
445 reg = <0x400e0000 0x1000>;
446 interrupts = <19>;
447 clocks = <&ccu1 CLK_APB3_I2C1>;
448 resets = <&rgu 49>;
449 #address-cells = <1>;
450 #size-cells = <0>;
451 status = "disabled";
452 };
454 dac: dac@400e1000 {
455 compatible = "nxp,lpc1850-dac";
456 reg = <0x400e1000 0x1000>;
457 interrupts = <0>;
458 clocks = <&ccu1 CLK_APB3_DAC>;
459 resets = <&rgu 42>;
460 status = "disabled";
461 };
463 can0: can@400e2000 {
464 compatible = "bosch,c_can";
465 reg = <0x400e2000 0x1000>;
466 interrupts = <51>;
467 clocks = <&ccu1 CLK_APB3_CAN0>;
468 resets = <&rgu 55>;
469 status = "disabled";
470 };
472 adc0: adc@400e3000 {
473 compatible = "nxp,lpc1850-adc";
474 reg = <0x400e3000 0x1000>;
475 interrupts = <17>;
476 clocks = <&ccu1 CLK_APB3_ADC0>;
477 resets = <&rgu 40>;
478 status = "disabled";
479 };
481 adc1: adc@400e4000 {
482 compatible = "nxp,lpc1850-adc";
483 reg = <0x400e4000 0x1000>;
484 interrupts = <21>;
485 clocks = <&ccu1 CLK_APB3_ADC1>;
486 resets = <&rgu 41>;
487 status = "disabled";
488 };
490 gpio: gpio@400f4000 {
491 compatible = "nxp,lpc1850-gpio";
492 reg = <0x400f4000 0x4000>;
493 clocks = <&ccu1 CLK_CPU_GPIO>;
494 gpio-controller;
495 #gpio-cells = <2>;
496 gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>,
497 <&pinctrl LPC_GPIO(0,4) LPC_PIN(1,0) 1>,
498 <&pinctrl LPC_GPIO(0,8) LPC_PIN(1,1) 4>,
499 <&pinctrl LPC_GPIO(1,8) LPC_PIN(1,5) 2>,
500 <&pinctrl LPC_GPIO(1,0) LPC_PIN(1,7) 8>,
501 <&pinctrl LPC_GPIO(0,2) LPC_PIN(1,15) 2>,
502 <&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>,
503 <&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>,
504 <&pinctrl LPC_GPIO(5,0) LPC_PIN(2,0) 7>,
505 <&pinctrl LPC_GPIO(0,7) LPC_PIN(2,7) 1>,
506 <&pinctrl LPC_GPIO(5,7) LPC_PIN(2,8) 1>,
507 <&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9) 1>,
508 <&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>,
509 <&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>,
510 <&pinctrl LPC_GPIO(5,8) LPC_PIN(3,1) 2>,
511 <&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4) 2>,
512 <&pinctrl LPC_GPIO(0,6) LPC_PIN(3,6) 1>,
513 <&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7) 2>,
514 <&pinctrl LPC_GPIO(2,0) LPC_PIN(4,0) 7>,
515 <&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8) 3>,
516 <&pinctrl LPC_GPIO(2,9) LPC_PIN(5,0) 7>,
517 <&pinctrl LPC_GPIO(2,7) LPC_PIN(5,7) 1>,
518 <&pinctrl LPC_GPIO(3,0) LPC_PIN(6,1) 5>,
519 <&pinctrl LPC_GPIO(0,5) LPC_PIN(6,6) 1>,
520 <&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7) 2>,
521 <&pinctrl LPC_GPIO(3,5) LPC_PIN(6,9) 3>,
522 <&pinctrl LPC_GPIO(2,8) LPC_PIN(6,12) 1>,
523 <&pinctrl LPC_GPIO(3,8) LPC_PIN(7,0) 8>,
524 <&pinctrl LPC_GPIO(4,0) LPC_PIN(8,0) 8>,
525 <&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0) 4>,
526 <&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4) 2>,
527 <&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6) 1>,
528 <&pinctrl LPC_GPIO(4,8) LPC_PIN(a,1) 3>,
529 <&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4) 1>,
530 <&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0) 7>,
531 <&pinctrl LPC_GPIO(6,0) LPC_PIN(c,1) 14>,
532 <&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>,
533 <&pinctrl LPC_GPIO(7,0) LPC_PIN(e,0) 16>,
534 <&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1) 3>,
535 <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>;
536 };
537 };
538 };