mm: fix exec activate_mm vs TLB shootdown and lazy tlb switching race
[linux/fpc-iii.git] / arch / arm / boot / dts / omap2.dtsi
blobf1d6de8b3c193eee0d88b0465f33de4e122ba266
1 /*
2  * Device Tree Source for OMAP2 SoC
3  *
4  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5  *
6  * This file is licensed under the terms of the GNU General Public License
7  * version 2.  This program is licensed "as is" without any warranty of any
8  * kind, whether express or implied.
9  */
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/omap.h>
15 / {
16         compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
17         interrupt-parent = <&intc>;
18         #address-cells = <1>;
19         #size-cells = <1>;
20         chosen { };
22         aliases {
23                 serial0 = &uart1;
24                 serial1 = &uart2;
25                 serial2 = &uart3;
26                 i2c0 = &i2c1;
27                 i2c1 = &i2c2;
28         };
30         cpus {
31                 #address-cells = <0>;
32                 #size-cells = <0>;
34                 cpu {
35                         compatible = "arm,arm1136jf-s";
36                         device_type = "cpu";
37                 };
38         };
40         pmu {
41                 compatible = "arm,arm1136-pmu";
42                 interrupts = <3>;
43         };
45         soc {
46                 compatible = "ti,omap-infra";
47                 mpu {
48                         compatible = "ti,omap2-mpu";
49                         ti,hwmods = "mpu";
50                 };
51         };
53         ocp {
54                 compatible = "simple-bus";
55                 #address-cells = <1>;
56                 #size-cells = <1>;
57                 ranges;
58                 ti,hwmods = "l3_main";
60                 aes: aes@480a6000 {
61                         compatible = "ti,omap2-aes";
62                         ti,hwmods = "aes";
63                         reg = <0x480a6000 0x50>;
64                         dmas = <&sdma 9 &sdma 10>;
65                         dma-names = "tx", "rx";
66                 };
68                 hdq1w: 1w@480b2000 {
69                         compatible = "ti,omap2420-1w";
70                         ti,hwmods = "hdq1w";
71                         reg = <0x480b2000 0x1000>;
72                         interrupts = <58>;
73                 };
75                 intc: interrupt-controller@1 {
76                         compatible = "ti,omap2-intc";
77                         interrupt-controller;
78                         #interrupt-cells = <1>;
79                         reg = <0x480FE000 0x1000>;
80                 };
82                 sdma: dma-controller@48056000 {
83                         compatible = "ti,omap2430-sdma", "ti,omap2420-sdma";
84                         ti,hwmods = "dma";
85                         reg = <0x48056000 0x1000>;
86                         interrupts = <12>,
87                                      <13>,
88                                      <14>,
89                                      <15>;
90                         #dma-cells = <1>;
91                         dma-channels = <32>;
92                         dma-requests = <64>;
93                 };
95                 i2c1: i2c@48070000 {
96                         compatible = "ti,omap2-i2c";
97                         ti,hwmods = "i2c1";
98                         reg = <0x48070000 0x80>;
99                         #address-cells = <1>;
100                         #size-cells = <0>;
101                         interrupts = <56>;
102                         dmas = <&sdma 27 &sdma 28>;
103                         dma-names = "tx", "rx";
104                 };
106                 i2c2: i2c@48072000 {
107                         compatible = "ti,omap2-i2c";
108                         ti,hwmods = "i2c2";
109                         reg = <0x48072000 0x80>;
110                         #address-cells = <1>;
111                         #size-cells = <0>;
112                         interrupts = <57>;
113                         dmas = <&sdma 29 &sdma 30>;
114                         dma-names = "tx", "rx";
115                 };
117                 mcspi1: mcspi@48098000 {
118                         compatible = "ti,omap2-mcspi";
119                         ti,hwmods = "mcspi1";
120                         reg = <0x48098000 0x100>;
121                         interrupts = <65>;
122                         dmas = <&sdma 35 &sdma 36 &sdma 37 &sdma 38
123                                 &sdma 39 &sdma 40 &sdma 41 &sdma 42>;
124                         dma-names = "tx0", "rx0", "tx1", "rx1",
125                                     "tx2", "rx2", "tx3", "rx3";
126                 };
128                 mcspi2: mcspi@4809a000 {
129                         compatible = "ti,omap2-mcspi";
130                         ti,hwmods = "mcspi2";
131                         reg = <0x4809a000 0x100>;
132                         interrupts = <66>;
133                         dmas = <&sdma 43 &sdma 44 &sdma 45 &sdma 46>;
134                         dma-names = "tx0", "rx0", "tx1", "rx1";
135                 };
137                 rng: rng@480a0000 {
138                         compatible = "ti,omap2-rng";
139                         ti,hwmods = "rng";
140                         reg = <0x480a0000 0x50>;
141                         interrupts = <52>;
142                 };
144                 sham: sham@480a4000 {
145                         compatible = "ti,omap2-sham";
146                         ti,hwmods = "sham";
147                         reg = <0x480a4000 0x64>;
148                         interrupts = <51>;
149                         dmas = <&sdma 13>;
150                         dma-names = "rx";
151                 };
153                 uart1: serial@4806a000 {
154                         compatible = "ti,omap2-uart";
155                         ti,hwmods = "uart1";
156                         reg = <0x4806a000 0x2000>;
157                         interrupts = <72>;
158                         dmas = <&sdma 49 &sdma 50>;
159                         dma-names = "tx", "rx";
160                         clock-frequency = <48000000>;
161                 };
163                 uart2: serial@4806c000 {
164                         compatible = "ti,omap2-uart";
165                         ti,hwmods = "uart2";
166                         reg = <0x4806c000 0x400>;
167                         interrupts = <73>;
168                         dmas = <&sdma 51 &sdma 52>;
169                         dma-names = "tx", "rx";
170                         clock-frequency = <48000000>;
171                 };
173                 uart3: serial@4806e000 {
174                         compatible = "ti,omap2-uart";
175                         ti,hwmods = "uart3";
176                         reg = <0x4806e000 0x400>;
177                         interrupts = <74>;
178                         dmas = <&sdma 53 &sdma 54>;
179                         dma-names = "tx", "rx";
180                         clock-frequency = <48000000>;
181                 };
183                 timer2: timer@4802a000 {
184                         compatible = "ti,omap2420-timer";
185                         reg = <0x4802a000 0x400>;
186                         interrupts = <38>;
187                         ti,hwmods = "timer2";
188                 };
190                 timer3: timer@48078000 {
191                         compatible = "ti,omap2420-timer";
192                         reg = <0x48078000 0x400>;
193                         interrupts = <39>;
194                         ti,hwmods = "timer3";
195                 };
197                 timer4: timer@4807a000 {
198                         compatible = "ti,omap2420-timer";
199                         reg = <0x4807a000 0x400>;
200                         interrupts = <40>;
201                         ti,hwmods = "timer4";
202                 };
204                 timer5: timer@4807c000 {
205                         compatible = "ti,omap2420-timer";
206                         reg = <0x4807c000 0x400>;
207                         interrupts = <41>;
208                         ti,hwmods = "timer5";
209                         ti,timer-dsp;
210                 };
212                 timer6: timer@4807e000 {
213                         compatible = "ti,omap2420-timer";
214                         reg = <0x4807e000 0x400>;
215                         interrupts = <42>;
216                         ti,hwmods = "timer6";
217                         ti,timer-dsp;
218                 };
220                 timer7: timer@48080000 {
221                         compatible = "ti,omap2420-timer";
222                         reg = <0x48080000 0x400>;
223                         interrupts = <43>;
224                         ti,hwmods = "timer7";
225                         ti,timer-dsp;
226                 };
228                 timer8: timer@48082000 {
229                         compatible = "ti,omap2420-timer";
230                         reg = <0x48082000 0x400>;
231                         interrupts = <44>;
232                         ti,hwmods = "timer8";
233                         ti,timer-dsp;
234                 };
236                 timer9: timer@48084000 {
237                         compatible = "ti,omap2420-timer";
238                         reg = <0x48084000 0x400>;
239                         interrupts = <45>;
240                         ti,hwmods = "timer9";
241                         ti,timer-pwm;
242                 };
244                 timer10: timer@48086000 {
245                         compatible = "ti,omap2420-timer";
246                         reg = <0x48086000 0x400>;
247                         interrupts = <46>;
248                         ti,hwmods = "timer10";
249                         ti,timer-pwm;
250                 };
252                 timer11: timer@48088000 {
253                         compatible = "ti,omap2420-timer";
254                         reg = <0x48088000 0x400>;
255                         interrupts = <47>;
256                         ti,hwmods = "timer11";
257                         ti,timer-pwm;
258                 };
260                 timer12: timer@4808a000 {
261                         compatible = "ti,omap2420-timer";
262                         reg = <0x4808a000 0x400>;
263                         interrupts = <48>;
264                         ti,hwmods = "timer12";
265                         ti,timer-pwm;
266                 };
268                 dss: dss@48050000 {
269                         compatible = "ti,omap2-dss";
270                         reg = <0x48050000 0x400>;
271                         status = "disabled";
272                         ti,hwmods = "dss_core";
273                         #address-cells = <1>;
274                         #size-cells = <1>;
275                         ranges;
277                         dispc@48050400 {
278                                 compatible = "ti,omap2-dispc";
279                                 reg = <0x48050400 0x400>;
280                                 interrupts = <25>;
281                                 ti,hwmods = "dss_dispc";
282                         };
284                         rfbi: encoder@48050800 {
285                                 compatible = "ti,omap2-rfbi";
286                                 reg = <0x48050800 0x400>;
287                                 status = "disabled";
288                                 ti,hwmods = "dss_rfbi";
289                         };
291                         venc: encoder@48050c00 {
292                                 compatible = "ti,omap2-venc";
293                                 reg = <0x48050c00 0x400>;
294                                 status = "disabled";
295                                 ti,hwmods = "dss_venc";
296                         };
297                 };
298         };