| blob | affa5b6f6da140a946ca59e51c64166368778413 |
1 // SPDX-License-Identifier: GPL-2.0
2 /* The pxa3xx skeleton simply augments the 2xx version */
3 #include "pxa2xx.dtsi"
5 #define MFP_PIN_PXA300(gpio) \
6 ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \
7 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
8 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \
9 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
10 0)
12 #define MFP_PIN_PXA310(gpio) \
13 ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \
14 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
15 (gpio <= 29) ? (0x0400 + 4 * (gpio - 27)) : \
16 (gpio <= 98) ? (0x0418 + 4 * (gpio - 30)) : \
17 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
18 (gpio <= 262) ? 0 : \
19 (gpio <= 268) ? (0x052c + 4 * (gpio - 263)) : \
20 0)
22 #define MFP_PIN_PXA320(gpio) \
23 ((gpio <= 4) ? (0x0124 + 4 * gpio) : \
24 (gpio <= 9) ? (0x028c + 4 * (gpio - 5)) : \
25 (gpio <= 10) ? (0x0458 + 4 * (gpio - 10)) : \
26 (gpio <= 26) ? (0x02a0 + 4 * (gpio - 11)) : \
27 (gpio <= 48) ? (0x0400 + 4 * (gpio - 27)) : \
28 (gpio <= 62) ? (0x045c + 4 * (gpio - 49)) : \
29 (gpio <= 73) ? (0x04b4 + 4 * (gpio - 63)) : \
30 (gpio <= 98) ? (0x04f0 + 4 * (gpio - 74)) : \
31 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
32 0)
34 /*
35 * MFP Alternate functions for pins having a gpio.
36 * Example of use: pinctrl-single,pins = < MFP_PIN_PXA310(21) MFP_AF1 >
37 */
38 #define MFP_AF0 (0 << 0)
39 #define MFP_AF1 (1 << 0)
40 #define MFP_AF2 (2 << 0)
41 #define MFP_AF3 (3 << 0)
42 #define MFP_AF4 (4 << 0)
43 #define MFP_AF5 (5 << 0)
44 #define MFP_AF6 (6 << 0)
46 /*
47 * MFP drive strength functions for pins.
48 * Example of use: pinctrl-single,drive-strength = MFP_DS03X;
49 */
50 #define MFP_DSMSK (0x7 << 10)
51 #define MFP_DS01X < (0x0 << 10) MFP_DSMSK >
52 #define MFP_DS02X < (0x1 << 10) MFP_DSMSK >
53 #define MFP_DS03X < (0x2 << 10) MFP_DSMSK >
54 #define MFP_DS04X < (0x3 << 10) MFP_DSMSK >
55 #define MFP_DS06X < (0x4 << 10) MFP_DSMSK >
56 #define MFP_DS08X < (0x5 << 10) MFP_DSMSK >
57 #define MFP_DS10X < (0x6 << 10) MFP_DSMSK >
58 #define MFP_DS13X < (0x7 << 10) MFP_DSMSK >
60 /*
61 * MFP low power mode for pins.
62 * Example of use:
63 * pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW|MFP_LPM_EDGE_FALL);
64 *
65 * Table that determines the low power modes outputs, with actual settings
66 * used in parentheses for don't-care values. Except for the float output,
67 * the configured driven and pulled levels match, so if there is a need for
68 * non-LPM pulled output, the same configuration could probably be used.
69 *
70 * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel
71 * (bit 7) (bit 8) (bit 14) (bit 13) (bit 15)
72 *
73 * Input 0 X(0) X(0) X(0) 0
74 * Drive 0 0 0 0 X(1) 0
75 * Drive 1 0 1 X(1) 0 0
76 * Pull hi (1) 1 X(1) 1 0 0
77 * Pull lo (0) 1 X(0) 0 1 0
78 * Z (float) 1 X(0) 0 0 0
79 */
80 #define MFP_LPM(x) < (x) MFP_LPM_MSK >
82 #define MFP_LPM_MSK 0xe1f0
83 #define MFP_LPM_INPUT 0x0000
84 #define MFP_LPM_DRIVE_LOW 0x2000
85 #define MFP_LPM_DRIVE_HIGH 0x4100
86 #define MFP_LPM_PULL_LOW 0x2080
87 #define MFP_LPM_PULL_HIGH 0x4180
88 #define MFP_LPM_FLOAT 0x0080
90 #define MFP_LPM_EDGE_NONE 0x0000
91 #define MFP_LPM_EDGE_RISE 0x0010
92 #define MFP_LPM_EDGE_FALL 0x0020
93 #define MFP_LPM_EDGE_BOTH 0x0030
95 / {
96 model = "Marvell PXA3xx familiy SoC";
97 compatible = "marvell,pxa3xx";
99 pxabus {
100 pdma: dma-controller@40000000 {
101 compatible = "marvell,pdma-1.0";
102 reg = <0x40000000 0x10000>;
103 interrupts = <25>;
104 #dma-channels = <32>;
105 #dma-cells = <2>;
106 #dma-requests = <100>;
107 status = "okay";
108 };
110 pwri2c: i2c@40f500c0 {
111 compatible = "mrvl,pwri2c";
112 reg = <0x40f500c0 0x30>;
113 interrupts = <6>;
114 clocks = <&clks CLK_PWRI2C>;
115 #address-cells = <0x1>;
116 #size-cells = <0>;
117 status = "disabled";
118 };
120 nand0: nand@43100000 {
121 compatible = "marvell,pxa3xx-nand";
122 reg = <0x43100000 90>;
123 interrupts = <45>;
124 clocks = <&clks CLK_NAND>;
125 dmas = <&pdma 97 3>;
126 dma-names = "data";
127 #address-cells = <1>;
128 #size-cells = <1>;
129 status = "disabled";
130 };
132 pxairq: interrupt-controller@40d00000 {
133 marvell,intc-priority;
134 marvell,intc-nr-irqs = <56>;
135 };
137 pinctrl: pinctrl@40e10000 {
138 compatible = "pinconf-single";
139 reg = <0x40e10000 0xffff>;
140 #address-cells = <1>;
141 #size-cells = <0>;
142 #pinctrl-cells = <1>;
143 pinctrl-single,register-width = <32>;
144 pinctrl-single,function-mask = <0x7>;
145 };
147 gpio: gpio@40e00000 {
148 compatible = "intel,pxa3xx-gpio";
149 reg = <0x40e00000 0x10000>;
150 clocks = <&clks CLK_GPIO>;
151 interrupt-names = "gpio0", "gpio1", "gpio_mux";
152 interrupts = <8 9 10>;
153 gpio-controller;
154 #gpio-cells = <0x2>;
155 interrupt-controller;
156 #interrupt-cells = <0x2>;
157 };
159 mmc0: mmc@41100000 {
160 compatible = "marvell,pxa-mmc";
161 reg = <0x41100000 0x1000>;
162 interrupts = <23>;
163 clocks = <&clks CLK_MMC>;
164 dmas = <&pdma 21 3
165 &pdma 22 3>;
166 dma-names = "rx", "tx";
167 status = "disabled";
168 };
170 mmc1: mmc@42000000 {
171 compatible = "marvell,pxa-mmc";
172 reg = <0x42000000 0x1000>;
173 interrupts = <41>;
174 clocks = <&clks CLK_MMC1>;
175 dmas = <&pdma 93 3
176 &pdma 94 3>;
177 dma-names = "rx", "tx";
178 status = "disabled";
179 };
181 mmc2: mmc@42500000 {
182 compatible = "marvell,pxa-mmc";
183 reg = <0x42500000 0x1000>;
184 interrupts = <55>;
185 clocks = <&clks CLK_MMC2>;
186 dmas = <&pdma 46 3
187 &pdma 47 3>;
188 dma-names = "rx", "tx";
189 status = "disabled";
190 };
192 usb0: usb@4c000000 {
193 compatible = "marvell,pxa-ohci";
194 reg = <0x4c000000 0x10000>;
195 interrupts = <3>;
196 clocks = <&clks CLK_USBH>;
197 status = "disabled";
198 };
200 pwm0: pwm@40b00000 {
201 compatible = "marvell,pxa270-pwm";
202 reg = <0x40b00000 0x10>;
203 #pwm-cells = <1>;
204 clocks = <&clks CLK_PWM0>;
205 status = "disabled";
206 };
208 pwm1: pwm@40b00010 {
209 compatible = "marvell,pxa270-pwm";
210 reg = <0x40b00010 0x10>;
211 #pwm-cells = <1>;
212 clocks = <&clks CLK_PWM1>;
213 status = "disabled";
214 };
216 pwm2: pwm@40c00000 {
217 compatible = "marvell,pxa270-pwm";
218 reg = <0x40c00000 0x10>;
219 #pwm-cells = <1>;
220 clocks = <&clks CLK_PWM0>;
221 status = "disabled";
222 };
224 pwm3: pwm@40c00010 {
225 compatible = "marvell,pxa270-pwm";
226 reg = <0x40c00010 0x10>;
227 #pwm-cells = <1>;
228 clocks = <&clks CLK_PWM1>;
229 status = "disabled";
230 };
231 };
233 clocks {
234 /*
235 * The muxing of external clocks/internal dividers for osc* clock
236 * sources has been hidden under the carpet by now.
237 */
238 #address-cells = <1>;
239 #size-cells = <1>;
240 ranges;
242 clks: pxa3xx_clks@41300004 {
243 compatible = "marvell,pxa300-clocks";
244 #clock-cells = <1>;
245 status = "okay";
246 };
247 };
249 timer@40a00000 {
250 compatible = "marvell,pxa-timer";
251 reg = <0x40a00000 0x20>;
252 interrupts = <26>;
253 clocks = <&clks CLK_OSTIMER>;
254 status = "okay";
255 };
256 };