| blob | 4ed12a4d9d51382143357585358f20081e216b35 |
1 /*
2 * Device Tree Source for the r7s72100 SoC
3 *
4 * Copyright (C) 2013-14 Renesas Solutions Corp.
5 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
12 #include <dt-bindings/clock/r7s72100-clock.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
16 / {
17 compatible = "renesas,r7s72100";
18 interrupt-parent = <&gic>;
19 #address-cells = <1>;
20 #size-cells = <1>;
22 aliases {
23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 spi0 = &spi0;
28 spi1 = &spi1;
29 spi2 = &spi2;
30 spi3 = &spi3;
31 spi4 = &spi4;
32 };
34 clocks {
35 ranges;
36 #address-cells = <1>;
37 #size-cells = <1>;
39 /* External clocks */
40 extal_clk: extal {
41 #clock-cells = <0>;
42 compatible = "fixed-clock";
43 /* If clk present, value must be set by board */
44 clock-frequency = <0>;
45 };
47 usb_x1_clk: usb_x1 {
48 #clock-cells = <0>;
49 compatible = "fixed-clock";
50 /* If clk present, value must be set by board */
51 clock-frequency = <0>;
52 };
54 rtc_x1_clk: rtc_x1 {
55 #clock-cells = <0>;
56 compatible = "fixed-clock";
57 /* If clk present, value must be set by board to 32678 */
58 clock-frequency = <0>;
59 };
61 rtc_x3_clk: rtc_x3 {
62 #clock-cells = <0>;
63 compatible = "fixed-clock";
64 /* If clk present, value must be set by board to 4000000 */
65 clock-frequency = <0>;
66 };
68 /* Fixed factor clocks */
69 b_clk: b {
70 #clock-cells = <0>;
71 compatible = "fixed-factor-clock";
72 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
73 clock-mult = <1>;
74 clock-div = <3>;
75 };
76 p1_clk: p1 {
77 #clock-cells = <0>;
78 compatible = "fixed-factor-clock";
79 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
80 clock-mult = <1>;
81 clock-div = <6>;
82 };
83 p0_clk: p0 {
84 #clock-cells = <0>;
85 compatible = "fixed-factor-clock";
86 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
87 clock-mult = <1>;
88 clock-div = <12>;
89 };
91 /* Special CPG clocks */
92 cpg_clocks: cpg_clocks@fcfe0000 {
93 #clock-cells = <1>;
94 compatible = "renesas,r7s72100-cpg-clocks",
95 "renesas,rz-cpg-clocks";
96 reg = <0xfcfe0000 0x18>;
97 clocks = <&extal_clk>, <&usb_x1_clk>;
98 clock-output-names = "pll", "i", "g";
99 #power-domain-cells = <0>;
100 };
102 /* MSTP clocks */
103 mstp3_clks: mstp3_clks@fcfe0420 {
104 #clock-cells = <1>;
105 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
106 reg = <0xfcfe0420 4>;
107 clocks = <&p0_clk>;
108 clock-indices = <R7S72100_CLK_MTU2>;
109 clock-output-names = "mtu2";
110 };
112 mstp4_clks: mstp4_clks@fcfe0424 {
113 #clock-cells = <1>;
114 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
115 reg = <0xfcfe0424 4>;
116 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
117 <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
118 clock-indices = <
119 R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
120 R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
121 >;
122 clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
123 };
125 mstp5_clks: mstp5_clks@fcfe0428 {
126 #clock-cells = <1>;
127 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
128 reg = <0xfcfe0428 4>;
129 clocks = <&p0_clk>, <&p0_clk>;
130 clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>;
131 clock-output-names = "ostm0", "ostm1";
132 };
134 mstp6_clks: mstp6_clks@fcfe042c {
135 #clock-cells = <1>;
136 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
137 reg = <0xfcfe042c 4>;
138 clocks = <&p0_clk>;
139 clock-indices = <R7S72100_CLK_RTC>;
140 clock-output-names = "rtc";
141 };
143 mstp7_clks: mstp7_clks@fcfe0430 {
144 #clock-cells = <1>;
145 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
146 reg = <0xfcfe0430 4>;
147 clocks = <&b_clk>, <&p1_clk>, <&p1_clk>;
148 clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>;
149 clock-output-names = "ether", "usb0", "usb1";
150 };
152 mstp8_clks: mstp8_clks@fcfe0434 {
153 #clock-cells = <1>;
154 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
155 reg = <0xfcfe0434 4>;
156 clocks = <&p1_clk>;
157 clock-indices = <R7S72100_CLK_MMCIF>;
158 clock-output-names = "mmcif";
159 };
161 mstp9_clks: mstp9_clks@fcfe0438 {
162 #clock-cells = <1>;
163 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
164 reg = <0xfcfe0438 4>;
165 clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
166 clock-indices = <
167 R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
168 >;
169 clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
170 };
172 mstp10_clks: mstp10_clks@fcfe043c {
173 #clock-cells = <1>;
174 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
175 reg = <0xfcfe043c 4>;
176 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
177 <&p1_clk>;
178 clock-indices = <
179 R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
180 R7S72100_CLK_SPI4
181 >;
182 clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
183 };
184 mstp12_clks: mstp12_clks@fcfe0444 {
185 #clock-cells = <1>;
186 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
187 reg = <0xfcfe0444 4>;
188 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
189 clock-indices = <
190 R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01
191 R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
192 >;
193 clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
194 };
195 };
197 cpus {
198 #address-cells = <1>;
199 #size-cells = <0>;
201 cpu@0 {
202 device_type = "cpu";
203 compatible = "arm,cortex-a9";
204 reg = <0>;
205 clock-frequency = <400000000>;
206 next-level-cache = <&L2>;
207 };
208 };
210 pinctrl: pin-controller@fcfe3000 {
211 compatible = "renesas,r7s72100-ports";
213 reg = <0xfcfe3000 0x4230>;
215 port0: gpio-0 {
216 gpio-controller;
217 #gpio-cells = <2>;
218 gpio-ranges = <&pinctrl 0 0 6>;
219 };
221 port1: gpio-1 {
222 gpio-controller;
223 #gpio-cells = <2>;
224 gpio-ranges = <&pinctrl 0 16 16>;
225 };
227 port2: gpio-2 {
228 gpio-controller;
229 #gpio-cells = <2>;
230 gpio-ranges = <&pinctrl 0 32 16>;
231 };
233 port3: gpio-3 {
234 gpio-controller;
235 #gpio-cells = <2>;
236 gpio-ranges = <&pinctrl 0 48 16>;
237 };
239 port4: gpio-4 {
240 gpio-controller;
241 #gpio-cells = <2>;
242 gpio-ranges = <&pinctrl 0 64 16>;
243 };
245 port5: gpio-5 {
246 gpio-controller;
247 #gpio-cells = <2>;
248 gpio-ranges = <&pinctrl 0 80 11>;
249 };
251 port6: gpio-6 {
252 gpio-controller;
253 #gpio-cells = <2>;
254 gpio-ranges = <&pinctrl 0 96 16>;
255 };
257 port7: gpio-7 {
258 gpio-controller;
259 #gpio-cells = <2>;
260 gpio-ranges = <&pinctrl 0 112 16>;
261 };
263 port8: gpio-8 {
264 gpio-controller;
265 #gpio-cells = <2>;
266 gpio-ranges = <&pinctrl 0 128 16>;
267 };
269 port9: gpio-9 {
270 gpio-controller;
271 #gpio-cells = <2>;
272 gpio-ranges = <&pinctrl 0 144 8>;
273 };
275 port10: gpio-10 {
276 gpio-controller;
277 #gpio-cells = <2>;
278 gpio-ranges = <&pinctrl 0 160 16>;
279 };
281 port11: gpio-11 {
282 gpio-controller;
283 #gpio-cells = <2>;
284 gpio-ranges = <&pinctrl 0 176 16>;
285 };
286 };
288 scif0: serial@e8007000 {
289 compatible = "renesas,scif-r7s72100", "renesas,scif";
290 reg = <0xe8007000 64>;
291 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
296 clock-names = "fck";
297 power-domains = <&cpg_clocks>;
298 status = "disabled";
299 };
301 scif1: serial@e8007800 {
302 compatible = "renesas,scif-r7s72100", "renesas,scif";
303 reg = <0xe8007800 64>;
304 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
309 clock-names = "fck";
310 power-domains = <&cpg_clocks>;
311 status = "disabled";
312 };
314 scif2: serial@e8008000 {
315 compatible = "renesas,scif-r7s72100", "renesas,scif";
316 reg = <0xe8008000 64>;
317 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
322 clock-names = "fck";
323 power-domains = <&cpg_clocks>;
324 status = "disabled";
325 };
327 scif3: serial@e8008800 {
328 compatible = "renesas,scif-r7s72100", "renesas,scif";
329 reg = <0xe8008800 64>;
330 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
335 clock-names = "fck";
336 power-domains = <&cpg_clocks>;
337 status = "disabled";
338 };
340 scif4: serial@e8009000 {
341 compatible = "renesas,scif-r7s72100", "renesas,scif";
342 reg = <0xe8009000 64>;
343 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
348 clock-names = "fck";
349 power-domains = <&cpg_clocks>;
350 status = "disabled";
351 };
353 scif5: serial@e8009800 {
354 compatible = "renesas,scif-r7s72100", "renesas,scif";
355 reg = <0xe8009800 64>;
356 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
361 clock-names = "fck";
362 power-domains = <&cpg_clocks>;
363 status = "disabled";
364 };
366 scif6: serial@e800a000 {
367 compatible = "renesas,scif-r7s72100", "renesas,scif";
368 reg = <0xe800a000 64>;
369 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
370 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
371 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
374 clock-names = "fck";
375 power-domains = <&cpg_clocks>;
376 status = "disabled";
377 };
379 scif7: serial@e800a800 {
380 compatible = "renesas,scif-r7s72100", "renesas,scif";
381 reg = <0xe800a800 64>;
382 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
383 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
384 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
387 clock-names = "fck";
388 power-domains = <&cpg_clocks>;
389 status = "disabled";
390 };
392 spi0: spi@e800c800 {
393 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
394 reg = <0xe800c800 0x24>;
395 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
396 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
397 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
398 interrupt-names = "error", "rx", "tx";
399 clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
400 power-domains = <&cpg_clocks>;
401 num-cs = <1>;
402 #address-cells = <1>;
403 #size-cells = <0>;
404 status = "disabled";
405 };
407 spi1: spi@e800d000 {
408 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
409 reg = <0xe800d000 0x24>;
410 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
411 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
412 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
413 interrupt-names = "error", "rx", "tx";
414 clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
415 power-domains = <&cpg_clocks>;
416 num-cs = <1>;
417 #address-cells = <1>;
418 #size-cells = <0>;
419 status = "disabled";
420 };
422 spi2: spi@e800d800 {
423 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
424 reg = <0xe800d800 0x24>;
425 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
427 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
428 interrupt-names = "error", "rx", "tx";
429 clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
430 power-domains = <&cpg_clocks>;
431 num-cs = <1>;
432 #address-cells = <1>;
433 #size-cells = <0>;
434 status = "disabled";
435 };
437 spi3: spi@e800e000 {
438 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
439 reg = <0xe800e000 0x24>;
440 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
441 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
443 interrupt-names = "error", "rx", "tx";
444 clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
445 power-domains = <&cpg_clocks>;
446 num-cs = <1>;
447 #address-cells = <1>;
448 #size-cells = <0>;
449 status = "disabled";
450 };
452 spi4: spi@e800e800 {
453 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
454 reg = <0xe800e800 0x24>;
455 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
458 interrupt-names = "error", "rx", "tx";
459 clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
460 power-domains = <&cpg_clocks>;
461 num-cs = <1>;
462 #address-cells = <1>;
463 #size-cells = <0>;
464 status = "disabled";
465 };
467 gic: interrupt-controller@e8201000 {
468 compatible = "arm,pl390";
469 #interrupt-cells = <3>;
470 #address-cells = <0>;
471 interrupt-controller;
472 reg = <0xe8201000 0x1000>,
473 <0xe8202000 0x1000>;
474 };
476 L2: cache-controller@3ffff000 {
477 compatible = "arm,pl310-cache";
478 reg = <0x3ffff000 0x1000>;
479 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
480 arm,early-bresp-disable;
481 arm,full-line-zero-disable;
482 cache-unified;
483 cache-level = <2>;
484 };
486 wdt: watchdog@fcfe0000 {
487 compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
488 reg = <0xfcfe0000 0x6>;
489 interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>;
490 clocks = <&p0_clk>;
491 };
493 i2c0: i2c@fcfee000 {
494 #address-cells = <1>;
495 #size-cells = <0>;
496 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
497 reg = <0xfcfee000 0x44>;
498 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
499 <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
500 <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
501 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
502 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
503 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
507 clock-frequency = <100000>;
508 power-domains = <&cpg_clocks>;
509 status = "disabled";
510 };
512 i2c1: i2c@fcfee400 {
513 #address-cells = <1>;
514 #size-cells = <0>;
515 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
516 reg = <0xfcfee400 0x44>;
517 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
518 <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
519 <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
520 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
522 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
526 clock-frequency = <100000>;
527 power-domains = <&cpg_clocks>;
528 status = "disabled";
529 };
531 i2c2: i2c@fcfee800 {
532 #address-cells = <1>;
533 #size-cells = <0>;
534 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
535 reg = <0xfcfee800 0x44>;
536 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
537 <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
538 <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
539 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
542 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
545 clock-frequency = <100000>;
546 power-domains = <&cpg_clocks>;
547 status = "disabled";
548 };
550 i2c3: i2c@fcfeec00 {
551 #address-cells = <1>;
552 #size-cells = <0>;
553 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
554 reg = <0xfcfeec00 0x44>;
555 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
557 <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
558 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
559 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
560 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
563 clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
564 clock-frequency = <100000>;
565 power-domains = <&cpg_clocks>;
566 status = "disabled";
567 };
569 mtu2: timer@fcff0000 {
570 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
571 reg = <0xfcff0000 0x400>;
572 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
573 interrupt-names = "tgi0a";
574 clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
575 clock-names = "fck";
576 power-domains = <&cpg_clocks>;
577 status = "disabled";
578 };
580 ether: ethernet@e8203000 {
581 compatible = "renesas,ether-r7s72100";
582 reg = <0xe8203000 0x800>,
583 <0xe8204800 0x200>;
584 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
585 clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
586 power-domains = <&cpg_clocks>;
587 phy-mode = "mii";
588 #address-cells = <1>;
589 #size-cells = <0>;
590 status = "disabled";
591 };
593 mmcif: mmc@e804c800 {
594 compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
595 reg = <0xe804c800 0x80>;
596 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
597 GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
598 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
599 clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
600 power-domains = <&cpg_clocks>;
601 reg-io-width = <4>;
602 bus-width = <8>;
603 status = "disabled";
604 };
606 sdhi0: sd@e804e000 {
607 compatible = "renesas,sdhi-r7s72100";
608 reg = <0xe804e000 0x100>;
609 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
610 GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
611 GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
614 <&mstp12_clks R7S72100_CLK_SDHI01>;
615 clock-names = "core", "cd";
616 power-domains = <&cpg_clocks>;
617 cap-sd-highspeed;
618 cap-sdio-irq;
619 status = "disabled";
620 };
622 sdhi1: sd@e804e800 {
623 compatible = "renesas,sdhi-r7s72100";
624 reg = <0xe804e800 0x100>;
625 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
626 GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
627 GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
630 <&mstp12_clks R7S72100_CLK_SDHI11>;
631 clock-names = "core", "cd";
632 power-domains = <&cpg_clocks>;
633 cap-sd-highspeed;
634 cap-sdio-irq;
635 status = "disabled";
636 };
638 ostm0: timer@fcfec000 {
639 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
640 reg = <0xfcfec000 0x30>;
641 interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
642 clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
643 power-domains = <&cpg_clocks>;
644 status = "disabled";
645 };
647 ostm1: timer@fcfec400 {
648 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
649 reg = <0xfcfec400 0x30>;
650 interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
651 clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
652 power-domains = <&cpg_clocks>;
653 status = "disabled";
654 };
656 rtc: rtc@fcff1000 {
657 compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";
658 reg = <0xfcff1000 0x2e>;
659 interrupts = <GIC_SPI 276 IRQ_TYPE_EDGE_RISING
660 GIC_SPI 277 IRQ_TYPE_EDGE_RISING
661 GIC_SPI 278 IRQ_TYPE_EDGE_RISING>;
662 interrupt-names = "alarm", "period", "carry";
663 clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>,
664 <&rtc_x3_clk>, <&extal_clk>;
665 clock-names = "fck", "rtc_x1", "rtc_x3", "extal";
666 power-domains = <&cpg_clocks>;
667 status = "disabled";
668 };
669 };