| blob | 14222c72f0e0f7d5ad95a46d68b310df76fff6cc |
1 /*
2 * Device Tree Source for the r8a7743 SoC
3 *
4 * Copyright (C) 2016-2017 Cogent Embedded Inc.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/clock/r8a7743-cpg-mssr.h>
14 #include <dt-bindings/power/r8a7743-sysc.h>
16 / {
17 compatible = "renesas,r8a7743";
18 #address-cells = <2>;
19 #size-cells = <2>;
21 aliases {
22 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 i2c2 = &i2c2;
25 i2c3 = &i2c3;
26 i2c4 = &i2c4;
27 i2c5 = &i2c5;
28 };
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33 enable-method = "renesas,apmu";
35 cpu0: cpu@0 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a15";
38 reg = <0>;
39 clock-frequency = <1500000000>;
40 clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
41 clock-latency = <300000>; /* 300 us */
42 power-domains = <&sysc R8A7743_PD_CA15_CPU0>;
43 next-level-cache = <&L2_CA15>;
45 /* kHz - uV - OPPs unknown yet */
46 operating-points = <1500000 1000000>,
47 <1312500 1000000>,
48 <1125000 1000000>,
49 < 937500 1000000>,
50 < 750000 1000000>,
51 < 375000 1000000>;
52 };
54 cpu1: cpu@1 {
55 device_type = "cpu";
56 compatible = "arm,cortex-a15";
57 reg = <1>;
58 clock-frequency = <1500000000>;
59 power-domains = <&sysc R8A7743_PD_CA15_CPU1>;
60 next-level-cache = <&L2_CA15>;
61 };
63 L2_CA15: cache-controller-0 {
64 compatible = "cache";
65 cache-unified;
66 cache-level = <2>;
67 power-domains = <&sysc R8A7743_PD_CA15_SCU>;
68 };
69 };
71 soc {
72 compatible = "simple-bus";
73 interrupt-parent = <&gic>;
75 #address-cells = <2>;
76 #size-cells = <2>;
77 ranges;
79 apmu@e6152000 {
80 compatible = "renesas,r8a7743-apmu", "renesas,apmu";
81 reg = <0 0xe6152000 0 0x188>;
82 cpus = <&cpu0 &cpu1>;
83 };
85 gic: interrupt-controller@f1001000 {
86 compatible = "arm,gic-400";
87 #interrupt-cells = <3>;
88 #address-cells = <0>;
89 interrupt-controller;
90 reg = <0 0xf1001000 0 0x1000>,
91 <0 0xf1002000 0 0x2000>,
92 <0 0xf1004000 0 0x2000>,
93 <0 0xf1006000 0 0x2000>;
94 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
95 IRQ_TYPE_LEVEL_HIGH)>;
96 clocks = <&cpg CPG_MOD 408>;
97 clock-names = "clk";
98 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
99 resets = <&cpg 408>;
100 };
102 gpio0: gpio@e6050000 {
103 compatible = "renesas,gpio-r8a7743",
104 "renesas,gpio-rcar";
105 reg = <0 0xe6050000 0 0x50>;
106 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
107 #gpio-cells = <2>;
108 gpio-controller;
109 gpio-ranges = <&pfc 0 0 32>;
110 #interrupt-cells = <2>;
111 interrupt-controller;
112 clocks = <&cpg CPG_MOD 912>;
113 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
114 resets = <&cpg 912>;
115 };
117 gpio1: gpio@e6051000 {
118 compatible = "renesas,gpio-r8a7743",
119 "renesas,gpio-rcar";
120 reg = <0 0xe6051000 0 0x50>;
121 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
122 #gpio-cells = <2>;
123 gpio-controller;
124 gpio-ranges = <&pfc 0 32 26>;
125 #interrupt-cells = <2>;
126 interrupt-controller;
127 clocks = <&cpg CPG_MOD 911>;
128 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
129 resets = <&cpg 911>;
130 };
132 gpio2: gpio@e6052000 {
133 compatible = "renesas,gpio-r8a7743",
134 "renesas,gpio-rcar";
135 reg = <0 0xe6052000 0 0x50>;
136 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
137 #gpio-cells = <2>;
138 gpio-controller;
139 gpio-ranges = <&pfc 0 64 32>;
140 #interrupt-cells = <2>;
141 interrupt-controller;
142 clocks = <&cpg CPG_MOD 910>;
143 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
144 resets = <&cpg 910>;
145 };
147 gpio3: gpio@e6053000 {
148 compatible = "renesas,gpio-r8a7743",
149 "renesas,gpio-rcar";
150 reg = <0 0xe6053000 0 0x50>;
151 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
152 #gpio-cells = <2>;
153 gpio-controller;
154 gpio-ranges = <&pfc 0 96 32>;
155 #interrupt-cells = <2>;
156 interrupt-controller;
157 clocks = <&cpg CPG_MOD 909>;
158 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
159 resets = <&cpg 909>;
160 };
162 gpio4: gpio@e6054000 {
163 compatible = "renesas,gpio-r8a7743",
164 "renesas,gpio-rcar";
165 reg = <0 0xe6054000 0 0x50>;
166 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
167 #gpio-cells = <2>;
168 gpio-controller;
169 gpio-ranges = <&pfc 0 128 32>;
170 #interrupt-cells = <2>;
171 interrupt-controller;
172 clocks = <&cpg CPG_MOD 908>;
173 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
174 resets = <&cpg 908>;
175 };
177 gpio5: gpio@e6055000 {
178 compatible = "renesas,gpio-r8a7743",
179 "renesas,gpio-rcar";
180 reg = <0 0xe6055000 0 0x50>;
181 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
182 #gpio-cells = <2>;
183 gpio-controller;
184 gpio-ranges = <&pfc 0 160 32>;
185 #interrupt-cells = <2>;
186 interrupt-controller;
187 clocks = <&cpg CPG_MOD 907>;
188 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
189 resets = <&cpg 907>;
190 };
192 gpio6: gpio@e6055400 {
193 compatible = "renesas,gpio-r8a7743",
194 "renesas,gpio-rcar";
195 reg = <0 0xe6055400 0 0x50>;
196 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
197 #gpio-cells = <2>;
198 gpio-controller;
199 gpio-ranges = <&pfc 0 192 32>;
200 #interrupt-cells = <2>;
201 interrupt-controller;
202 clocks = <&cpg CPG_MOD 905>;
203 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
204 resets = <&cpg 905>;
205 };
207 gpio7: gpio@e6055800 {
208 compatible = "renesas,gpio-r8a7743",
209 "renesas,gpio-rcar";
210 reg = <0 0xe6055800 0 0x50>;
211 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
212 #gpio-cells = <2>;
213 gpio-controller;
214 gpio-ranges = <&pfc 0 224 26>;
215 #interrupt-cells = <2>;
216 interrupt-controller;
217 clocks = <&cpg CPG_MOD 904>;
218 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
219 resets = <&cpg 904>;
220 };
222 irqc: interrupt-controller@e61c0000 {
223 compatible = "renesas,irqc-r8a7743", "renesas,irqc";
224 #interrupt-cells = <2>;
225 interrupt-controller;
226 reg = <0 0xe61c0000 0 0x200>;
227 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&cpg CPG_MOD 407>;
238 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
239 resets = <&cpg 407>;
240 };
242 timer {
243 compatible = "arm,armv7-timer";
244 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
245 IRQ_TYPE_LEVEL_LOW)>,
246 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
247 IRQ_TYPE_LEVEL_LOW)>,
248 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
249 IRQ_TYPE_LEVEL_LOW)>,
250 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
251 IRQ_TYPE_LEVEL_LOW)>;
252 };
254 cpg: clock-controller@e6150000 {
255 compatible = "renesas,r8a7743-cpg-mssr";
256 reg = <0 0xe6150000 0 0x1000>;
257 clocks = <&extal_clk>, <&usb_extal_clk>;
258 clock-names = "extal", "usb_extal";
259 #clock-cells = <2>;
260 #power-domain-cells = <0>;
261 #reset-cells = <1>;
262 };
264 prr: chipid@ff000044 {
265 compatible = "renesas,prr";
266 reg = <0 0xff000044 0 4>;
267 };
269 rst: reset-controller@e6160000 {
270 compatible = "renesas,r8a7743-rst";
271 reg = <0 0xe6160000 0 0x100>;
272 };
274 sysc: system-controller@e6180000 {
275 compatible = "renesas,r8a7743-sysc";
276 reg = <0 0xe6180000 0 0x200>;
277 #power-domain-cells = <1>;
278 };
280 pfc: pin-controller@e6060000 {
281 compatible = "renesas,pfc-r8a7743";
282 reg = <0 0xe6060000 0 0x250>;
283 };
285 dmac0: dma-controller@e6700000 {
286 compatible = "renesas,dmac-r8a7743",
287 "renesas,rcar-dmac";
288 reg = <0 0xe6700000 0 0x20000>;
289 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
290 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
291 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
292 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
293 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
294 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
295 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
296 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
297 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
298 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
299 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
300 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
301 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
302 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
303 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
304 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
305 interrupt-names = "error",
306 "ch0", "ch1", "ch2", "ch3",
307 "ch4", "ch5", "ch6", "ch7",
308 "ch8", "ch9", "ch10", "ch11",
309 "ch12", "ch13", "ch14";
310 clocks = <&cpg CPG_MOD 219>;
311 clock-names = "fck";
312 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
313 resets = <&cpg 219>;
314 #dma-cells = <1>;
315 dma-channels = <15>;
316 };
318 dmac1: dma-controller@e6720000 {
319 compatible = "renesas,dmac-r8a7743",
320 "renesas,rcar-dmac";
321 reg = <0 0xe6720000 0 0x20000>;
322 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
323 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
324 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
325 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
326 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
327 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
328 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
329 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
330 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
331 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
332 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
333 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
334 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
335 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
336 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
337 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
338 interrupt-names = "error",
339 "ch0", "ch1", "ch2", "ch3",
340 "ch4", "ch5", "ch6", "ch7",
341 "ch8", "ch9", "ch10", "ch11",
342 "ch12", "ch13", "ch14";
343 clocks = <&cpg CPG_MOD 218>;
344 clock-names = "fck";
345 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
346 resets = <&cpg 218>;
347 #dma-cells = <1>;
348 dma-channels = <15>;
349 };
351 /* The memory map in the User's Manual maps the cores to bus
352 * numbers
353 */
354 i2c0: i2c@e6508000 {
355 #address-cells = <1>;
356 #size-cells = <0>;
357 compatible = "renesas,i2c-r8a7743",
358 "renesas,rcar-gen2-i2c";
359 reg = <0 0xe6508000 0 0x40>;
360 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&cpg CPG_MOD 931>;
362 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
363 resets = <&cpg 931>;
364 i2c-scl-internal-delay-ns = <6>;
365 status = "disabled";
366 };
368 i2c1: i2c@e6518000 {
369 #address-cells = <1>;
370 #size-cells = <0>;
371 compatible = "renesas,i2c-r8a7743",
372 "renesas,rcar-gen2-i2c";
373 reg = <0 0xe6518000 0 0x40>;
374 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&cpg CPG_MOD 930>;
376 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
377 resets = <&cpg 930>;
378 i2c-scl-internal-delay-ns = <6>;
379 status = "disabled";
380 };
382 i2c2: i2c@e6530000 {
383 #address-cells = <1>;
384 #size-cells = <0>;
385 compatible = "renesas,i2c-r8a7743",
386 "renesas,rcar-gen2-i2c";
387 reg = <0 0xe6530000 0 0x40>;
388 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
389 clocks = <&cpg CPG_MOD 929>;
390 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
391 resets = <&cpg 929>;
392 i2c-scl-internal-delay-ns = <6>;
393 status = "disabled";
394 };
396 i2c3: i2c@e6540000 {
397 #address-cells = <1>;
398 #size-cells = <0>;
399 compatible = "renesas,i2c-r8a7743",
400 "renesas,rcar-gen2-i2c";
401 reg = <0 0xe6540000 0 0x40>;
402 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&cpg CPG_MOD 928>;
404 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
405 resets = <&cpg 928>;
406 i2c-scl-internal-delay-ns = <6>;
407 status = "disabled";
408 };
410 i2c4: i2c@e6520000 {
411 #address-cells = <1>;
412 #size-cells = <0>;
413 compatible = "renesas,i2c-r8a7743",
414 "renesas,rcar-gen2-i2c";
415 reg = <0 0xe6520000 0 0x40>;
416 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&cpg CPG_MOD 927>;
418 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
419 resets = <&cpg 927>;
420 i2c-scl-internal-delay-ns = <6>;
421 status = "disabled";
422 };
424 i2c5: i2c@e6528000 {
425 /* doesn't need pinmux */
426 #address-cells = <1>;
427 #size-cells = <0>;
428 compatible = "renesas,i2c-r8a7743",
429 "renesas,rcar-gen2-i2c";
430 reg = <0 0xe6528000 0 0x40>;
431 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&cpg CPG_MOD 925>;
433 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
434 resets = <&cpg 925>;
435 i2c-scl-internal-delay-ns = <110>;
436 status = "disabled";
437 };
439 scifa0: serial@e6c40000 {
440 compatible = "renesas,scifa-r8a7743",
441 "renesas,rcar-gen2-scifa", "renesas,scifa";
442 reg = <0 0xe6c40000 0 0x40>;
443 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&cpg CPG_MOD 204>;
445 clock-names = "fck";
446 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
447 <&dmac1 0x21>, <&dmac1 0x22>;
448 dma-names = "tx", "rx", "tx", "rx";
449 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
450 resets = <&cpg 204>;
451 status = "disabled";
452 };
454 scifa1: serial@e6c50000 {
455 compatible = "renesas,scifa-r8a7743",
456 "renesas,rcar-gen2-scifa", "renesas,scifa";
457 reg = <0 0xe6c50000 0 0x40>;
458 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&cpg CPG_MOD 203>;
460 clock-names = "fck";
461 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
462 <&dmac1 0x25>, <&dmac1 0x26>;
463 dma-names = "tx", "rx", "tx", "rx";
464 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
465 resets = <&cpg 203>;
466 status = "disabled";
467 };
469 scifa2: serial@e6c60000 {
470 compatible = "renesas,scifa-r8a7743",
471 "renesas,rcar-gen2-scifa", "renesas,scifa";
472 reg = <0 0xe6c60000 0 0x40>;
473 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&cpg CPG_MOD 202>;
475 clock-names = "fck";
476 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
477 <&dmac1 0x27>, <&dmac1 0x28>;
478 dma-names = "tx", "rx", "tx", "rx";
479 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
480 resets = <&cpg 202>;
481 status = "disabled";
482 };
484 scifa3: serial@e6c70000 {
485 compatible = "renesas,scifa-r8a7743",
486 "renesas,rcar-gen2-scifa", "renesas,scifa";
487 reg = <0 0xe6c70000 0 0x40>;
488 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&cpg CPG_MOD 1106>;
490 clock-names = "fck";
491 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
492 <&dmac1 0x1b>, <&dmac1 0x1c>;
493 dma-names = "tx", "rx", "tx", "rx";
494 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
495 resets = <&cpg 1106>;
496 status = "disabled";
497 };
499 scifa4: serial@e6c78000 {
500 compatible = "renesas,scifa-r8a7743",
501 "renesas,rcar-gen2-scifa", "renesas,scifa";
502 reg = <0 0xe6c78000 0 0x40>;
503 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&cpg CPG_MOD 1107>;
505 clock-names = "fck";
506 dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
507 <&dmac1 0x1f>, <&dmac1 0x20>;
508 dma-names = "tx", "rx", "tx", "rx";
509 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
510 resets = <&cpg 1107>;
511 status = "disabled";
512 };
514 scifa5: serial@e6c80000 {
515 compatible = "renesas,scifa-r8a7743",
516 "renesas,rcar-gen2-scifa", "renesas,scifa";
517 reg = <0 0xe6c80000 0 0x40>;
518 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&cpg CPG_MOD 1108>;
520 clock-names = "fck";
521 dmas = <&dmac0 0x23>, <&dmac0 0x24>,
522 <&dmac1 0x23>, <&dmac1 0x24>;
523 dma-names = "tx", "rx", "tx", "rx";
524 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
525 resets = <&cpg 1108>;
526 status = "disabled";
527 };
529 scifb0: serial@e6c20000 {
530 compatible = "renesas,scifb-r8a7743",
531 "renesas,rcar-gen2-scifb", "renesas,scifb";
532 reg = <0 0xe6c20000 0 0x100>;
533 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&cpg CPG_MOD 206>;
535 clock-names = "fck";
536 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
537 <&dmac1 0x3d>, <&dmac1 0x3e>;
538 dma-names = "tx", "rx", "tx", "rx";
539 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
540 resets = <&cpg 206>;
541 status = "disabled";
542 };
544 scifb1: serial@e6c30000 {
545 compatible = "renesas,scifb-r8a7743",
546 "renesas,rcar-gen2-scifb", "renesas,scifb";
547 reg = <0 0xe6c30000 0 0x100>;
548 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
549 clocks = <&cpg CPG_MOD 207>;
550 clock-names = "fck";
551 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
552 <&dmac1 0x19>, <&dmac1 0x1a>;
553 dma-names = "tx", "rx", "tx", "rx";
554 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
555 resets = <&cpg 207>;
556 status = "disabled";
557 };
559 scifb2: serial@e6ce0000 {
560 compatible = "renesas,scifb-r8a7743",
561 "renesas,rcar-gen2-scifb", "renesas,scifb";
562 reg = <0 0xe6ce0000 0 0x100>;
563 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&cpg CPG_MOD 216>;
565 clock-names = "fck";
566 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
567 <&dmac1 0x1d>, <&dmac1 0x1e>;
568 dma-names = "tx", "rx", "tx", "rx";
569 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
570 resets = <&cpg 216>;
571 status = "disabled";
572 };
574 scif0: serial@e6e60000 {
575 compatible = "renesas,scif-r8a7743",
576 "renesas,rcar-gen2-scif", "renesas,scif";
577 reg = <0 0xe6e60000 0 0x40>;
578 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
579 clocks = <&cpg CPG_MOD 721>,
580 <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
581 clock-names = "fck", "brg_int", "scif_clk";
582 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
583 <&dmac1 0x29>, <&dmac1 0x2a>;
584 dma-names = "tx", "rx", "tx", "rx";
585 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
586 resets = <&cpg 721>;
587 status = "disabled";
588 };
590 scif1: serial@e6e68000 {
591 compatible = "renesas,scif-r8a7743",
592 "renesas,rcar-gen2-scif", "renesas,scif";
593 reg = <0 0xe6e68000 0 0x40>;
594 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&cpg CPG_MOD 720>,
596 <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
597 clock-names = "fck", "brg_int", "scif_clk";
598 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
599 <&dmac1 0x2d>, <&dmac1 0x2e>;
600 dma-names = "tx", "rx", "tx", "rx";
601 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
602 resets = <&cpg 720>;
603 status = "disabled";
604 };
606 scif2: serial@e6e58000 {
607 compatible = "renesas,scif-r8a7743",
608 "renesas,rcar-gen2-scif", "renesas,scif";
609 reg = <0 0xe6e58000 0 0x40>;
610 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
611 clocks = <&cpg CPG_MOD 719>,
612 <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
613 clock-names = "fck", "brg_int", "scif_clk";
614 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
615 <&dmac1 0x2b>, <&dmac1 0x2c>;
616 dma-names = "tx", "rx", "tx", "rx";
617 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
618 resets = <&cpg 719>;
619 status = "disabled";
620 };
622 scif3: serial@e6ea8000 {
623 compatible = "renesas,scif-r8a7743",
624 "renesas,rcar-gen2-scif", "renesas,scif";
625 reg = <0 0xe6ea8000 0 0x40>;
626 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
627 clocks = <&cpg CPG_MOD 718>,
628 <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
629 clock-names = "fck", "brg_int", "scif_clk";
630 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
631 <&dmac1 0x2f>, <&dmac1 0x30>;
632 dma-names = "tx", "rx", "tx", "rx";
633 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
634 resets = <&cpg 718>;
635 status = "disabled";
636 };
638 scif4: serial@e6ee0000 {
639 compatible = "renesas,scif-r8a7743",
640 "renesas,rcar-gen2-scif", "renesas,scif";
641 reg = <0 0xe6ee0000 0 0x40>;
642 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
643 clocks = <&cpg CPG_MOD 715>,
644 <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
645 clock-names = "fck", "brg_int", "scif_clk";
646 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
647 <&dmac1 0xfb>, <&dmac1 0xfc>;
648 dma-names = "tx", "rx", "tx", "rx";
649 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
650 resets = <&cpg 715>;
651 status = "disabled";
652 };
654 scif5: serial@e6ee8000 {
655 compatible = "renesas,scif-r8a7743",
656 "renesas,rcar-gen2-scif", "renesas,scif";
657 reg = <0 0xe6ee8000 0 0x40>;
658 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
659 clocks = <&cpg CPG_MOD 714>,
660 <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
661 clock-names = "fck", "brg_int", "scif_clk";
662 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
663 <&dmac1 0xfd>, <&dmac1 0xfe>;
664 dma-names = "tx", "rx", "tx", "rx";
665 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
666 resets = <&cpg 714>;
667 status = "disabled";
668 };
670 hscif0: serial@e62c0000 {
671 compatible = "renesas,hscif-r8a7743",
672 "renesas,rcar-gen2-hscif", "renesas,hscif";
673 reg = <0 0xe62c0000 0 0x60>;
674 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&cpg CPG_MOD 717>,
676 <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
677 clock-names = "fck", "brg_int", "scif_clk";
678 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
679 <&dmac1 0x39>, <&dmac1 0x3a>;
680 dma-names = "tx", "rx", "tx", "rx";
681 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
682 resets = <&cpg 717>;
683 status = "disabled";
684 };
686 hscif1: serial@e62c8000 {
687 compatible = "renesas,hscif-r8a7743",
688 "renesas,rcar-gen2-hscif", "renesas,hscif";
689 reg = <0 0xe62c8000 0 0x60>;
690 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&cpg CPG_MOD 716>,
692 <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
693 clock-names = "fck", "brg_int", "scif_clk";
694 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
695 <&dmac1 0x4d>, <&dmac1 0x4e>;
696 dma-names = "tx", "rx", "tx", "rx";
697 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
698 resets = <&cpg 716>;
699 status = "disabled";
700 };
702 hscif2: serial@e62d0000 {
703 compatible = "renesas,hscif-r8a7743",
704 "renesas,rcar-gen2-hscif", "renesas,hscif";
705 reg = <0 0xe62d0000 0 0x60>;
706 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
707 clocks = <&cpg CPG_MOD 713>,
708 <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
709 clock-names = "fck", "brg_int", "scif_clk";
710 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
711 <&dmac1 0x3b>, <&dmac1 0x3c>;
712 dma-names = "tx", "rx", "tx", "rx";
713 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
714 resets = <&cpg 713>;
715 status = "disabled";
716 };
718 icram2: sram@e6300000 {
719 compatible = "mmio-sram";
720 reg = <0 0xe6300000 0 0x40000>;
721 };
723 icram0: sram@e63a0000 {
724 compatible = "mmio-sram";
725 reg = <0 0xe63a0000 0 0x12000>;
726 };
728 icram1: sram@e63c0000 {
729 compatible = "mmio-sram";
730 reg = <0 0xe63c0000 0 0x1000>;
731 #address-cells = <1>;
732 #size-cells = <1>;
733 ranges = <0 0 0xe63c0000 0x1000>;
735 smp-sram@0 {
736 compatible = "renesas,smp-sram";
737 reg = <0 0x10>;
738 };
739 };
741 ether: ethernet@ee700000 {
742 compatible = "renesas,ether-r8a7743";
743 reg = <0 0xee700000 0 0x400>;
744 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
745 clocks = <&cpg CPG_MOD 813>;
746 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
747 resets = <&cpg 813>;
748 phy-mode = "rmii";
749 #address-cells = <1>;
750 #size-cells = <0>;
751 status = "disabled";
752 };
754 avb: ethernet@e6800000 {
755 compatible = "renesas,etheravb-r8a7743",
756 "renesas,etheravb-rcar-gen2";
757 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
758 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&cpg CPG_MOD 812>;
760 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
761 resets = <&cpg 812>;
762 #address-cells = <1>;
763 #size-cells = <0>;
764 status = "disabled";
765 };
767 mmcif0: mmc@ee200000 {
768 compatible = "renesas,mmcif-r8a7743",
769 "renesas,sh-mmcif";
770 reg = <0 0xee200000 0 0x80>;
771 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
772 clocks = <&cpg CPG_MOD 315>;
773 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
774 <&dmac1 0xd1>, <&dmac1 0xd2>;
775 dma-names = "tx", "rx", "tx", "rx";
776 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
777 resets = <&cpg 315>;
778 reg-io-width = <4>;
779 max-frequency = <97500000>;
780 status = "disabled";
781 };
782 };
784 /* External root clock */
785 extal_clk: extal {
786 compatible = "fixed-clock";
787 #clock-cells = <0>;
788 /* This value must be overridden by the board. */
789 clock-frequency = <0>;
790 };
792 /* External USB clock - can be overridden by the board */
793 usb_extal_clk: usb_extal {
794 compatible = "fixed-clock";
795 #clock-cells = <0>;
796 clock-frequency = <48000000>;
797 };
799 /* External SCIF clock */
800 scif_clk: scif {
801 compatible = "fixed-clock";
802 #clock-cells = <0>;
803 /* This value must be overridden by the board. */
804 clock-frequency = <0>;
805 };
806 };