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mm: fix exec activate_mm vs TLB shootdown and lazy tlb switching race
[linux/fpc-iii.git] / arch / arm / common / sa1111.c
blob4ecd5120fce7b773ae6057282fa1d09a1b7c934d
1 /*
2 * linux/arch/arm/common/sa1111.c
3 *
4 * SA1111 support
5 *
6 * Original code by John Dorsey
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This file contains all generic SA1111 support.
13 *
14 * All initialization functions provided here are intended to be called
15 * from machine specific code with proper arguments when required.
16 */
17 #include <linux/module.h>
18 #include <linux/gpio/driver.h>
19 #include <linux/init.h>
20 #include <linux/irq.h>
21 #include <linux/kernel.h>
22 #include <linux/delay.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include <linux/spinlock.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/clk.h>
30 #include <linux/io.h>
31
32 #include <mach/hardware.h>
33 #include <asm/mach/irq.h>
34 #include <asm/mach-types.h>
35 #include <asm/sizes.h>
36
37 #include <asm/hardware/sa1111.h>
38
39 /* SA1111 IRQs */
40 #define IRQ_GPAIN0 (0)
41 #define IRQ_GPAIN1 (1)
42 #define IRQ_GPAIN2 (2)
43 #define IRQ_GPAIN3 (3)
44 #define IRQ_GPBIN0 (4)
45 #define IRQ_GPBIN1 (5)
46 #define IRQ_GPBIN2 (6)
47 #define IRQ_GPBIN3 (7)
48 #define IRQ_GPBIN4 (8)
49 #define IRQ_GPBIN5 (9)
50 #define IRQ_GPCIN0 (10)
51 #define IRQ_GPCIN1 (11)
52 #define IRQ_GPCIN2 (12)
53 #define IRQ_GPCIN3 (13)
54 #define IRQ_GPCIN4 (14)
55 #define IRQ_GPCIN5 (15)
56 #define IRQ_GPCIN6 (16)
57 #define IRQ_GPCIN7 (17)
58 #define IRQ_MSTXINT (18)
59 #define IRQ_MSRXINT (19)
60 #define IRQ_MSSTOPERRINT (20)
61 #define IRQ_TPTXINT (21)
62 #define IRQ_TPRXINT (22)
63 #define IRQ_TPSTOPERRINT (23)
64 #define SSPXMTINT (24)
65 #define SSPRCVINT (25)
66 #define SSPROR (26)
67 #define AUDXMTDMADONEA (32)
68 #define AUDRCVDMADONEA (33)
69 #define AUDXMTDMADONEB (34)
70 #define AUDRCVDMADONEB (35)
71 #define AUDTFSR (36)
72 #define AUDRFSR (37)
73 #define AUDTUR (38)
74 #define AUDROR (39)
75 #define AUDDTS (40)
76 #define AUDRDD (41)
77 #define AUDSTO (42)
78 #define IRQ_USBPWR (43)
79 #define IRQ_HCIM (44)
80 #define IRQ_HCIBUFFACC (45)
81 #define IRQ_HCIRMTWKP (46)
82 #define IRQ_NHCIMFCIR (47)
83 #define IRQ_USB_PORT_RESUME (48)
84 #define IRQ_S0_READY_NINT (49)
85 #define IRQ_S1_READY_NINT (50)
86 #define IRQ_S0_CD_VALID (51)
87 #define IRQ_S1_CD_VALID (52)
88 #define IRQ_S0_BVD1_STSCHG (53)
89 #define IRQ_S1_BVD1_STSCHG (54)
90 #define SA1111_IRQ_NR (55)
91
92 extern void sa1110_mb_enable(void);
93 extern void sa1110_mb_disable(void);
94
95 /*
96 * We keep the following data for the overall SA1111. Note that the
97 * struct device and struct resource are "fake"; they should be supplied
98 * by the bus above us. However, in the interests of getting all SA1111
99 * drivers converted over to the device model, we provide this as an
100 * anchor point for all the other drivers.
101 */
102 struct sa1111 {
103 struct device *dev;
104 struct clk *clk;
105 unsigned long phys;
106 int irq;
107 int irq_base; /* base for cascaded on-chip IRQs */
108 spinlock_t lock;
109 void __iomem *base;
110 struct sa1111_platform_data *pdata;
111 struct gpio_chip gc;
112 #ifdef CONFIG_PM
113 void *saved_state;
114 #endif
115 };
116
117 /*
118 * We _really_ need to eliminate this. Its only users
119 * are the PWM and DMA checking code.
120 */
121 static struct sa1111 *g_sa1111;
122
123 struct sa1111_dev_info {
124 unsigned long offset;
125 unsigned long skpcr_mask;
126 bool dma;
127 unsigned int devid;
128 unsigned int irq[6];
129 };
130
131 static struct sa1111_dev_info sa1111_devices[] = {
132 {
133 .offset = SA1111_USB,
134 .skpcr_mask = SKPCR_UCLKEN,
135 .dma = true,
136 .devid = SA1111_DEVID_USB,
137 .irq = {
138 IRQ_USBPWR,
139 IRQ_HCIM,
140 IRQ_HCIBUFFACC,
141 IRQ_HCIRMTWKP,
142 IRQ_NHCIMFCIR,
143 IRQ_USB_PORT_RESUME
144 },
145 },
146 {
147 .offset = 0x0600,
148 .skpcr_mask = SKPCR_I2SCLKEN | SKPCR_L3CLKEN,
149 .dma = true,
150 .devid = SA1111_DEVID_SAC,
151 .irq = {
152 AUDXMTDMADONEA,
153 AUDXMTDMADONEB,
154 AUDRCVDMADONEA,
155 AUDRCVDMADONEB
156 },
157 },
158 {
159 .offset = 0x0800,
160 .skpcr_mask = SKPCR_SCLKEN,
161 .devid = SA1111_DEVID_SSP,
162 },
163 {
164 .offset = SA1111_KBD,
165 .skpcr_mask = SKPCR_PTCLKEN,
166 .devid = SA1111_DEVID_PS2_KBD,
167 .irq = {
168 IRQ_TPRXINT,
169 IRQ_TPTXINT
170 },
171 },
172 {
173 .offset = SA1111_MSE,
174 .skpcr_mask = SKPCR_PMCLKEN,
175 .devid = SA1111_DEVID_PS2_MSE,
176 .irq = {
177 IRQ_MSRXINT,
178 IRQ_MSTXINT
179 },
180 },
181 {
182 .offset = 0x1800,
183 .skpcr_mask = 0,
184 .devid = SA1111_DEVID_PCMCIA,
185 .irq = {
186 IRQ_S0_READY_NINT,
187 IRQ_S0_CD_VALID,
188 IRQ_S0_BVD1_STSCHG,
189 IRQ_S1_READY_NINT,
190 IRQ_S1_CD_VALID,
191 IRQ_S1_BVD1_STSCHG,
192 },
193 },
194 };
195
196 /*
197 * SA1111 interrupt support. Since clearing an IRQ while there are
198 * active IRQs causes the interrupt output to pulse, the upper levels
199 * will call us again if there are more interrupts to process.
200 */
201 static void sa1111_irq_handler(struct irq_desc *desc)
202 {
203 unsigned int stat0, stat1, i;
204 struct sa1111 *sachip = irq_desc_get_handler_data(desc);
205 void __iomem *mapbase = sachip->base + SA1111_INTC;
206
207 stat0 = sa1111_readl(mapbase + SA1111_INTSTATCLR0);
208 stat1 = sa1111_readl(mapbase + SA1111_INTSTATCLR1);
209
210 sa1111_writel(stat0, mapbase + SA1111_INTSTATCLR0);
211
212 desc->irq_data.chip->irq_ack(&desc->irq_data);
213
214 sa1111_writel(stat1, mapbase + SA1111_INTSTATCLR1);
215
216 if (stat0 == 0 && stat1 == 0) {
217 do_bad_IRQ(desc);
218 return;
219 }
220
221 for (i = 0; stat0; i++, stat0 >>= 1)
222 if (stat0 & 1)
223 generic_handle_irq(i + sachip->irq_base);
224
225 for (i = 32; stat1; i++, stat1 >>= 1)
226 if (stat1 & 1)
227 generic_handle_irq(i + sachip->irq_base);
228
229 /* For level-based interrupts */
230 desc->irq_data.chip->irq_unmask(&desc->irq_data);
231 }
232
233 #define SA1111_IRQMASK_LO(x) (1 << (x - sachip->irq_base))
234 #define SA1111_IRQMASK_HI(x) (1 << (x - sachip->irq_base - 32))
235
236 static u32 sa1111_irqmask(struct irq_data *d)
237 {
238 struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
239
240 return BIT((d->irq - sachip->irq_base) & 31);
241 }
242
243 static int sa1111_irqbank(struct irq_data *d)
244 {
245 struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
246
247 return ((d->irq - sachip->irq_base) / 32) * 4;
248 }
249
250 static void sa1111_ack_irq(struct irq_data *d)
251 {
252 }
253
254 static void sa1111_mask_irq(struct irq_data *d)
255 {
256 struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
257 void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
258 u32 ie;
259
260 ie = sa1111_readl(mapbase + SA1111_INTEN0);
261 ie &= ~sa1111_irqmask(d);
262 sa1111_writel(ie, mapbase + SA1111_INTEN0);
263 }
264
265 static void sa1111_unmask_irq(struct irq_data *d)
266 {
267 struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
268 void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
269 u32 ie;
270
271 ie = sa1111_readl(mapbase + SA1111_INTEN0);
272 ie |= sa1111_irqmask(d);
273 sa1111_writel(ie, mapbase + SA1111_INTEN0);
274 }
275
276 /*
277 * Attempt to re-trigger the interrupt. The SA1111 contains a register
278 * (INTSET) which claims to do this. However, in practice no amount of
279 * manipulation of INTEN and INTSET guarantees that the interrupt will
280 * be triggered. In fact, its very difficult, if not impossible to get
281 * INTSET to re-trigger the interrupt.
282 */
283 static int sa1111_retrigger_irq(struct irq_data *d)
284 {
285 struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
286 void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
287 u32 ip, mask = sa1111_irqmask(d);
288 int i;
289
290 ip = sa1111_readl(mapbase + SA1111_INTPOL0);
291 for (i = 0; i < 8; i++) {
292 sa1111_writel(ip ^ mask, mapbase + SA1111_INTPOL0);
293 sa1111_writel(ip, mapbase + SA1111_INTPOL0);
294 if (sa1111_readl(mapbase + SA1111_INTSTATCLR0) & mask)
295 break;
296 }
297
298 if (i == 8)
299 pr_err("Danger Will Robinson: failed to re-trigger IRQ%d\n",
300 d->irq);
301 return i == 8 ? -1 : 0;
302 }
303
304 static int sa1111_type_irq(struct irq_data *d, unsigned int flags)
305 {
306 struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
307 void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
308 u32 ip, mask = sa1111_irqmask(d);
309
310 if (flags == IRQ_TYPE_PROBE)
311 return 0;
312
313 if ((!(flags & IRQ_TYPE_EDGE_RISING) ^ !(flags & IRQ_TYPE_EDGE_FALLING)) == 0)
314 return -EINVAL;
315
316 ip = sa1111_readl(mapbase + SA1111_INTPOL0);
317 if (flags & IRQ_TYPE_EDGE_RISING)
318 ip &= ~mask;
319 else
320 ip |= mask;
321 sa1111_writel(ip, mapbase + SA1111_INTPOL0);
322 sa1111_writel(ip, mapbase + SA1111_WAKEPOL0);
323
324 return 0;
325 }
326
327 static int sa1111_wake_irq(struct irq_data *d, unsigned int on)
328 {
329 struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
330 void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
331 u32 we, mask = sa1111_irqmask(d);
332
333 we = sa1111_readl(mapbase + SA1111_WAKEEN0);
334 if (on)
335 we |= mask;
336 else
337 we &= ~mask;
338 sa1111_writel(we, mapbase + SA1111_WAKEEN0);
339
340 return 0;
341 }
342
343 static struct irq_chip sa1111_irq_chip = {
344 .name = "SA1111",
345 .irq_ack = sa1111_ack_irq,
346 .irq_mask = sa1111_mask_irq,
347 .irq_unmask = sa1111_unmask_irq,
348 .irq_retrigger = sa1111_retrigger_irq,
349 .irq_set_type = sa1111_type_irq,
350 .irq_set_wake = sa1111_wake_irq,
351 };
352
353 static int sa1111_setup_irq(struct sa1111 *sachip, unsigned irq_base)
354 {
355 void __iomem *irqbase = sachip->base + SA1111_INTC;
356 unsigned i, irq;
357 int ret;
358
359 /*
360 * We're guaranteed that this region hasn't been taken.
361 */
362 request_mem_region(sachip->phys + SA1111_INTC, 512, "irq");
363
364 ret = irq_alloc_descs(-1, irq_base, SA1111_IRQ_NR, -1);
365 if (ret <= 0) {
366 dev_err(sachip->dev, "unable to allocate %u irqs: %d\n",
367 SA1111_IRQ_NR, ret);
368 if (ret == 0)
369 ret = -EINVAL;
370 return ret;
371 }
372
373 sachip->irq_base = ret;
374
375 /* disable all IRQs */
376 sa1111_writel(0, irqbase + SA1111_INTEN0);
377 sa1111_writel(0, irqbase + SA1111_INTEN1);
378 sa1111_writel(0, irqbase + SA1111_WAKEEN0);
379 sa1111_writel(0, irqbase + SA1111_WAKEEN1);
380
381 /*
382 * detect on rising edge. Note: Feb 2001 Errata for SA1111
383 * specifies that S0ReadyInt and S1ReadyInt should be '1'.
384 */
385 sa1111_writel(0, irqbase + SA1111_INTPOL0);
386 sa1111_writel(BIT(IRQ_S0_READY_NINT & 31) |
387 BIT(IRQ_S1_READY_NINT & 31),
388 irqbase + SA1111_INTPOL1);
389
390 /* clear all IRQs */
391 sa1111_writel(~0, irqbase + SA1111_INTSTATCLR0);
392 sa1111_writel(~0, irqbase + SA1111_INTSTATCLR1);
393
394 for (i = IRQ_GPAIN0; i <= SSPROR; i++) {
395 irq = sachip->irq_base + i;
396 irq_set_chip_and_handler(irq, &sa1111_irq_chip, handle_edge_irq);
397 irq_set_chip_data(irq, sachip);
398 irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
399 }
400
401 for (i = AUDXMTDMADONEA; i <= IRQ_S1_BVD1_STSCHG; i++) {
402 irq = sachip->irq_base + i;
403 irq_set_chip_and_handler(irq, &sa1111_irq_chip, handle_edge_irq);
404 irq_set_chip_data(irq, sachip);
405 irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
406 }
407
408 /*
409 * Register SA1111 interrupt
410 */
411 irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING);
412 irq_set_chained_handler_and_data(sachip->irq, sa1111_irq_handler,
413 sachip);
414
415 dev_info(sachip->dev, "Providing IRQ%u-%u\n",
416 sachip->irq_base, sachip->irq_base + SA1111_IRQ_NR - 1);
417
418 return 0;
419 }
420
421 static void sa1111_remove_irq(struct sa1111 *sachip)
422 {
423 void __iomem *irqbase = sachip->base + SA1111_INTC;
424
425 /* disable all IRQs */
426 sa1111_writel(0, irqbase + SA1111_INTEN0);
427 sa1111_writel(0, irqbase + SA1111_INTEN1);
428 sa1111_writel(0, irqbase + SA1111_WAKEEN0);
429 sa1111_writel(0, irqbase + SA1111_WAKEEN1);
430
431 if (sachip->irq != NO_IRQ) {
432 irq_set_chained_handler_and_data(sachip->irq, NULL, NULL);
433 irq_free_descs(sachip->irq_base, SA1111_IRQ_NR);
434
435 release_mem_region(sachip->phys + SA1111_INTC, 512);
436 }
437 }
438
439 enum {
440 SA1111_GPIO_PXDDR = (SA1111_GPIO_PADDR - SA1111_GPIO_PADDR),
441 SA1111_GPIO_PXDRR = (SA1111_GPIO_PADRR - SA1111_GPIO_PADDR),
442 SA1111_GPIO_PXDWR = (SA1111_GPIO_PADWR - SA1111_GPIO_PADDR),
443 SA1111_GPIO_PXSDR = (SA1111_GPIO_PASDR - SA1111_GPIO_PADDR),
444 SA1111_GPIO_PXSSR = (SA1111_GPIO_PASSR - SA1111_GPIO_PADDR),
445 };
446
447 static struct sa1111 *gc_to_sa1111(struct gpio_chip *gc)
448 {
449 return container_of(gc, struct sa1111, gc);
450 }
451
452 static void __iomem *sa1111_gpio_map_reg(struct sa1111 *sachip, unsigned offset)
453 {
454 void __iomem *reg = sachip->base + SA1111_GPIO;
455
456 if (offset < 4)
457 return reg + SA1111_GPIO_PADDR;
458 if (offset < 10)
459 return reg + SA1111_GPIO_PBDDR;
460 if (offset < 18)
461 return reg + SA1111_GPIO_PCDDR;
462 return NULL;
463 }
464
465 static u32 sa1111_gpio_map_bit(unsigned offset)
466 {
467 if (offset < 4)
468 return BIT(offset);
469 if (offset < 10)
470 return BIT(offset - 4);
471 if (offset < 18)
472 return BIT(offset - 10);
473 return 0;
474 }
475
476 static void sa1111_gpio_modify(void __iomem *reg, u32 mask, u32 set)
477 {
478 u32 val;
479
480 val = readl_relaxed(reg);
481 val &= ~mask;
482 val |= mask & set;
483 writel_relaxed(val, reg);
484 }
485
486 static int sa1111_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
487 {
488 struct sa1111 *sachip = gc_to_sa1111(gc);
489 void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
490 u32 mask = sa1111_gpio_map_bit(offset);
491
492 return !!(readl_relaxed(reg + SA1111_GPIO_PXDDR) & mask);
493 }
494
495 static int sa1111_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
496 {
497 struct sa1111 *sachip = gc_to_sa1111(gc);
498 unsigned long flags;
499 void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
500 u32 mask = sa1111_gpio_map_bit(offset);
501
502 spin_lock_irqsave(&sachip->lock, flags);
503 sa1111_gpio_modify(reg + SA1111_GPIO_PXDDR, mask, mask);
504 sa1111_gpio_modify(reg + SA1111_GPIO_PXSDR, mask, mask);
505 spin_unlock_irqrestore(&sachip->lock, flags);
506
507 return 0;
508 }
509
510 static int sa1111_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
511 int value)
512 {
513 struct sa1111 *sachip = gc_to_sa1111(gc);
514 unsigned long flags;
515 void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
516 u32 mask = sa1111_gpio_map_bit(offset);
517
518 spin_lock_irqsave(&sachip->lock, flags);
519 sa1111_gpio_modify(reg + SA1111_GPIO_PXDWR, mask, value ? mask : 0);
520 sa1111_gpio_modify(reg + SA1111_GPIO_PXSSR, mask, value ? mask : 0);
521 sa1111_gpio_modify(reg + SA1111_GPIO_PXDDR, mask, 0);
522 sa1111_gpio_modify(reg + SA1111_GPIO_PXSDR, mask, 0);
523 spin_unlock_irqrestore(&sachip->lock, flags);
524
525 return 0;
526 }
527
528 static int sa1111_gpio_get(struct gpio_chip *gc, unsigned offset)
529 {
530 struct sa1111 *sachip = gc_to_sa1111(gc);
531 void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
532 u32 mask = sa1111_gpio_map_bit(offset);
533
534 return !!(readl_relaxed(reg + SA1111_GPIO_PXDRR) & mask);
535 }
536
537 static void sa1111_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
538 {
539 struct sa1111 *sachip = gc_to_sa1111(gc);
540 unsigned long flags;
541 void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
542 u32 mask = sa1111_gpio_map_bit(offset);
543
544 spin_lock_irqsave(&sachip->lock, flags);
545 sa1111_gpio_modify(reg + SA1111_GPIO_PXDWR, mask, value ? mask : 0);
546 sa1111_gpio_modify(reg + SA1111_GPIO_PXSSR, mask, value ? mask : 0);
547 spin_unlock_irqrestore(&sachip->lock, flags);
548 }
549
550 static void sa1111_gpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
551 unsigned long *bits)
552 {
553 struct sa1111 *sachip = gc_to_sa1111(gc);
554 unsigned long flags;
555 void __iomem *reg = sachip->base + SA1111_GPIO;
556 u32 msk, val;
557
558 msk = *mask;
559 val = *bits;
560
561 spin_lock_irqsave(&sachip->lock, flags);
562 sa1111_gpio_modify(reg + SA1111_GPIO_PADWR, msk & 15, val);
563 sa1111_gpio_modify(reg + SA1111_GPIO_PASSR, msk & 15, val);
564 sa1111_gpio_modify(reg + SA1111_GPIO_PBDWR, (msk >> 4) & 255, val >> 4);
565 sa1111_gpio_modify(reg + SA1111_GPIO_PBSSR, (msk >> 4) & 255, val >> 4);
566 sa1111_gpio_modify(reg + SA1111_GPIO_PCDWR, (msk >> 12) & 255, val >> 12);
567 sa1111_gpio_modify(reg + SA1111_GPIO_PCSSR, (msk >> 12) & 255, val >> 12);
568 spin_unlock_irqrestore(&sachip->lock, flags);
569 }
570
571 static int sa1111_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
572 {
573 struct sa1111 *sachip = gc_to_sa1111(gc);
574
575 return sachip->irq_base + offset;
576 }
577
578 static int sa1111_setup_gpios(struct sa1111 *sachip)
579 {
580 sachip->gc.label = "sa1111";
581 sachip->gc.parent = sachip->dev;
582 sachip->gc.owner = THIS_MODULE;
583 sachip->gc.get_direction = sa1111_gpio_get_direction;
584 sachip->gc.direction_input = sa1111_gpio_direction_input;
585 sachip->gc.direction_output = sa1111_gpio_direction_output;
586 sachip->gc.get = sa1111_gpio_get;
587 sachip->gc.set = sa1111_gpio_set;
588 sachip->gc.set_multiple = sa1111_gpio_set_multiple;
589 sachip->gc.to_irq = sa1111_gpio_to_irq;
590 sachip->gc.base = -1;
591 sachip->gc.ngpio = 18;
592
593 return devm_gpiochip_add_data(sachip->dev, &sachip->gc, sachip);
594 }
595
596 /*
597 * Bring the SA1111 out of reset. This requires a set procedure:
598 * 1. nRESET asserted (by hardware)
599 * 2. CLK turned on from SA1110
600 * 3. nRESET deasserted
601 * 4. VCO turned on, PLL_BYPASS turned off
602 * 5. Wait lock time, then assert RCLKEn
603 * 7. PCR set to allow clocking of individual functions
604 *
605 * Until we've done this, the only registers we can access are:
606 * SBI_SKCR
607 * SBI_SMCR
608 * SBI_SKID
609 */
610 static void sa1111_wake(struct sa1111 *sachip)
611 {
612 unsigned long flags, r;
613
614 spin_lock_irqsave(&sachip->lock, flags);
615
616 clk_enable(sachip->clk);
617
618 /*
619 * Turn VCO on, and disable PLL Bypass.
620 */
621 r = sa1111_readl(sachip->base + SA1111_SKCR);
622 r &= ~SKCR_VCO_OFF;
623 sa1111_writel(r, sachip->base + SA1111_SKCR);
624 r |= SKCR_PLL_BYPASS | SKCR_OE_EN;
625 sa1111_writel(r, sachip->base + SA1111_SKCR);
626
627 /*
628 * Wait lock time. SA1111 manual _doesn't_
629 * specify a figure for this! We choose 100us.
630 */
631 udelay(100);
632
633 /*
634 * Enable RCLK. We also ensure that RDYEN is set.
635 */
636 r |= SKCR_RCLKEN | SKCR_RDYEN;
637 sa1111_writel(r, sachip->base + SA1111_SKCR);
638
639 /*
640 * Wait 14 RCLK cycles for the chip to finish coming out
641 * of reset. (RCLK=24MHz). This is 590ns.
642 */
643 udelay(1);
644
645 /*
646 * Ensure all clocks are initially off.
647 */
648 sa1111_writel(0, sachip->base + SA1111_SKPCR);
649
650 spin_unlock_irqrestore(&sachip->lock, flags);
651 }
652
653 #ifdef CONFIG_ARCH_SA1100
654
655 static u32 sa1111_dma_mask[] = {
656 ~0,
657 ~(1 << 20),
658 ~(1 << 23),
659 ~(1 << 24),
660 ~(1 << 25),
661 ~(1 << 20),
662 ~(1 << 20),
663 0,
664 };
665
666 /*
667 * Configure the SA1111 shared memory controller.
668 */
669 void
670 sa1111_configure_smc(struct sa1111 *sachip, int sdram, unsigned int drac,
671 unsigned int cas_latency)
672 {
673 unsigned int smcr = SMCR_DTIM | SMCR_MBGE | FInsrt(drac, SMCR_DRAC);
674
675 if (cas_latency == 3)
676 smcr |= SMCR_CLAT;
677
678 sa1111_writel(smcr, sachip->base + SA1111_SMCR);
679
680 /*
681 * Now clear the bits in the DMA mask to work around the SA1111
682 * DMA erratum (Intel StrongARM SA-1111 Microprocessor Companion
683 * Chip Specification Update, June 2000, Erratum #7).
684 */
685 if (sachip->dev->dma_mask)
686 *sachip->dev->dma_mask &= sa1111_dma_mask[drac >> 2];
687
688 sachip->dev->coherent_dma_mask &= sa1111_dma_mask[drac >> 2];
689 }
690 #endif
691
692 static void sa1111_dev_release(struct device *_dev)
693 {
694 struct sa1111_dev *dev = to_sa1111_device(_dev);
695
696 kfree(dev);
697 }
698
699 static int
700 sa1111_init_one_child(struct sa1111 *sachip, struct resource *parent,
701 struct sa1111_dev_info *info)
702 {
703 struct sa1111_dev *dev;
704 unsigned i;
705 int ret;
706
707 dev = kzalloc(sizeof(struct sa1111_dev), GFP_KERNEL);
708 if (!dev) {
709 ret = -ENOMEM;
710 goto err_alloc;
711 }
712
713 device_initialize(&dev->dev);
714 dev_set_name(&dev->dev, "%4.4lx", info->offset);
715 dev->devid = info->devid;
716 dev->dev.parent = sachip->dev;
717 dev->dev.bus = &sa1111_bus_type;
718 dev->dev.release = sa1111_dev_release;
719 dev->res.start = sachip->phys + info->offset;
720 dev->res.end = dev->res.start + 511;
721 dev->res.name = dev_name(&dev->dev);
722 dev->res.flags = IORESOURCE_MEM;
723 dev->mapbase = sachip->base + info->offset;
724 dev->skpcr_mask = info->skpcr_mask;
725
726 for (i = 0; i < ARRAY_SIZE(info->irq); i++)
727 dev->irq[i] = sachip->irq_base + info->irq[i];
728
729 /*
730 * If the parent device has a DMA mask associated with it, and
731 * this child supports DMA, propagate it down to the children.
732 */
733 if (info->dma && sachip->dev->dma_mask) {
734 dev->dma_mask = *sachip->dev->dma_mask;
735 dev->dev.dma_mask = &dev->dma_mask;
736 dev->dev.coherent_dma_mask = sachip->dev->coherent_dma_mask;
737 }
738
739 ret = request_resource(parent, &dev->res);
740 if (ret) {
741 dev_err(sachip->dev, "failed to allocate resource for %s\n",
742 dev->res.name);
743 goto err_resource;
744 }
745
746 ret = device_add(&dev->dev);
747 if (ret)
748 goto err_add;
749 return 0;
750
751 err_add:
752 release_resource(&dev->res);
753 err_resource:
754 put_device(&dev->dev);
755 err_alloc:
756 return ret;
757 }
758
759 /**
760 * sa1111_probe - probe for a single SA1111 chip.
761 * @phys_addr: physical address of device.
762 *
763 * Probe for a SA1111 chip. This must be called
764 * before any other SA1111-specific code.
765 *
766 * Returns:
767 * %-ENODEV device not found.
768 * %-EBUSY physical address already marked in-use.
769 * %-EINVAL no platform data passed
770 * %0 successful.
771 */
772 static int __sa1111_probe(struct device *me, struct resource *mem, int irq)
773 {
774 struct sa1111_platform_data *pd = me->platform_data;
775 struct sa1111 *sachip;
776 unsigned long id;
777 unsigned int has_devs;
778 int i, ret = -ENODEV;
779
780 if (!pd)
781 return -EINVAL;
782
783 sachip = devm_kzalloc(me, sizeof(struct sa1111), GFP_KERNEL);
784 if (!sachip)
785 return -ENOMEM;
786
787 sachip->clk = devm_clk_get(me, "SA1111_CLK");
788 if (IS_ERR(sachip->clk))
789 return PTR_ERR(sachip->clk);
790
791 ret = clk_prepare(sachip->clk);
792 if (ret)
793 return ret;
794
795 spin_lock_init(&sachip->lock);
796
797 sachip->dev = me;
798 dev_set_drvdata(sachip->dev, sachip);
799
800 sachip->pdata = pd;
801 sachip->phys = mem->start;
802 sachip->irq = irq;
803
804 /*
805 * Map the whole region. This also maps the
806 * registers for our children.
807 */
808 sachip->base = ioremap(mem->start, PAGE_SIZE * 2);
809 if (!sachip->base) {
810 ret = -ENOMEM;
811 goto err_clk_unprep;
812 }
813
814 /*
815 * Probe for the chip. Only touch the SBI registers.
816 */
817 id = sa1111_readl(sachip->base + SA1111_SKID);
818 if ((id & SKID_ID_MASK) != SKID_SA1111_ID) {
819 printk(KERN_DEBUG "SA1111 not detected: ID = %08lx\n", id);
820 ret = -ENODEV;
821 goto err_unmap;
822 }
823
824 pr_info("SA1111 Microprocessor Companion Chip: silicon revision %lx, metal revision %lx\n",
825 (id & SKID_SIREV_MASK) >> 4, id & SKID_MTREV_MASK);
826
827 /*
828 * We found it. Wake the chip up, and initialise.
829 */
830 sa1111_wake(sachip);
831
832 /*
833 * The interrupt controller must be initialised before any
834 * other device to ensure that the interrupts are available.
835 */
836 if (sachip->irq != NO_IRQ) {
837 ret = sa1111_setup_irq(sachip, pd->irq_base);
838 if (ret)
839 goto err_clk;
840 }
841
842 /* Setup the GPIOs - should really be done after the IRQ setup */
843 ret = sa1111_setup_gpios(sachip);
844 if (ret)
845 goto err_irq;
846
847 #ifdef CONFIG_ARCH_SA1100
848 {
849 unsigned int val;
850
851 /*
852 * The SDRAM configuration of the SA1110 and the SA1111 must
853 * match. This is very important to ensure that SA1111 accesses
854 * don't corrupt the SDRAM. Note that this ungates the SA1111's
855 * MBGNT signal, so we must have called sa1110_mb_disable()
856 * beforehand.
857 */
858 sa1111_configure_smc(sachip, 1,
859 FExtr(MDCNFG, MDCNFG_SA1110_DRAC0),
860 FExtr(MDCNFG, MDCNFG_SA1110_TDL0));
861
862 /*
863 * We only need to turn on DCLK whenever we want to use the
864 * DMA. It can otherwise be held firmly in the off position.
865 * (currently, we always enable it.)
866 */
867 val = sa1111_readl(sachip->base + SA1111_SKPCR);
868 sa1111_writel(val | SKPCR_DCLKEN, sachip->base + SA1111_SKPCR);
869
870 /*
871 * Enable the SA1110 memory bus request and grant signals.
872 */
873 sa1110_mb_enable();
874 }
875 #endif
876
877 g_sa1111 = sachip;
878
879 has_devs = ~0;
880 if (pd)
881 has_devs &= ~pd->disable_devs;
882
883 for (i = 0; i < ARRAY_SIZE(sa1111_devices); i++)
884 if (sa1111_devices[i].devid & has_devs)
885 sa1111_init_one_child(sachip, mem, &sa1111_devices[i]);
886
887 return 0;
888
889 err_irq:
890 sa1111_remove_irq(sachip);
891 err_clk:
892 clk_disable(sachip->clk);
893 err_unmap:
894 iounmap(sachip->base);
895 err_clk_unprep:
896 clk_unprepare(sachip->clk);
897 return ret;
898 }
899
900 static int sa1111_remove_one(struct device *dev, void *data)
901 {
902 struct sa1111_dev *sadev = to_sa1111_device(dev);
903 if (dev->bus != &sa1111_bus_type)
904 return 0;
905 device_del(&sadev->dev);
906 release_resource(&sadev->res);
907 put_device(&sadev->dev);
908 return 0;
909 }
910
911 static void __sa1111_remove(struct sa1111 *sachip)
912 {
913 device_for_each_child(sachip->dev, NULL, sa1111_remove_one);
914
915 sa1111_remove_irq(sachip);
916
917 clk_disable(sachip->clk);
918 clk_unprepare(sachip->clk);
919
920 iounmap(sachip->base);
921 }
922
923 struct sa1111_save_data {
924 unsigned int skcr;
925 unsigned int skpcr;
926 unsigned int skcdr;
927 unsigned char skaud;
928 unsigned char skpwm0;
929 unsigned char skpwm1;
930
931 /*
932 * Interrupt controller
933 */
934 unsigned int intpol0;
935 unsigned int intpol1;
936 unsigned int inten0;
937 unsigned int inten1;
938 unsigned int wakepol0;
939 unsigned int wakepol1;
940 unsigned int wakeen0;
941 unsigned int wakeen1;
942 };
943
944 #ifdef CONFIG_PM
945
946 static int sa1111_suspend_noirq(struct device *dev)
947 {
948 struct sa1111 *sachip = dev_get_drvdata(dev);
949 struct sa1111_save_data *save;
950 unsigned long flags;
951 unsigned int val;
952 void __iomem *base;
953
954 save = kmalloc(sizeof(struct sa1111_save_data), GFP_KERNEL);
955 if (!save)
956 return -ENOMEM;
957 sachip->saved_state = save;
958
959 spin_lock_irqsave(&sachip->lock, flags);
960
961 /*
962 * Save state.
963 */
964 base = sachip->base;
965 save->skcr = sa1111_readl(base + SA1111_SKCR);
966 save->skpcr = sa1111_readl(base + SA1111_SKPCR);
967 save->skcdr = sa1111_readl(base + SA1111_SKCDR);
968 save->skaud = sa1111_readl(base + SA1111_SKAUD);
969 save->skpwm0 = sa1111_readl(base + SA1111_SKPWM0);
970 save->skpwm1 = sa1111_readl(base + SA1111_SKPWM1);
971
972 sa1111_writel(0, sachip->base + SA1111_SKPWM0);
973 sa1111_writel(0, sachip->base + SA1111_SKPWM1);
974
975 base = sachip->base + SA1111_INTC;
976 save->intpol0 = sa1111_readl(base + SA1111_INTPOL0);
977 save->intpol1 = sa1111_readl(base + SA1111_INTPOL1);
978 save->inten0 = sa1111_readl(base + SA1111_INTEN0);
979 save->inten1 = sa1111_readl(base + SA1111_INTEN1);
980 save->wakepol0 = sa1111_readl(base + SA1111_WAKEPOL0);
981 save->wakepol1 = sa1111_readl(base + SA1111_WAKEPOL1);
982 save->wakeen0 = sa1111_readl(base + SA1111_WAKEEN0);
983 save->wakeen1 = sa1111_readl(base + SA1111_WAKEEN1);
984
985 /*
986 * Disable.
987 */
988 val = sa1111_readl(sachip->base + SA1111_SKCR);
989 sa1111_writel(val | SKCR_SLEEP, sachip->base + SA1111_SKCR);
990
991 clk_disable(sachip->clk);
992
993 spin_unlock_irqrestore(&sachip->lock, flags);
994
995 #ifdef CONFIG_ARCH_SA1100
996 sa1110_mb_disable();
997 #endif
998
999 return 0;
1000 }
1001
1002 /*
1003 * sa1111_resume - Restore the SA1111 device state.
1004 * @dev: device to restore
1005 *
1006 * Restore the general state of the SA1111; clock control and
1007 * interrupt controller. Other parts of the SA1111 must be
1008 * restored by their respective drivers, and must be called
1009 * via LDM after this function.
1010 */
1011 static int sa1111_resume_noirq(struct device *dev)
1012 {
1013 struct sa1111 *sachip = dev_get_drvdata(dev);
1014 struct sa1111_save_data *save;
1015 unsigned long flags, id;
1016 void __iomem *base;
1017
1018 save = sachip->saved_state;
1019 if (!save)
1020 return 0;
1021
1022 /*
1023 * Ensure that the SA1111 is still here.
1024 * FIXME: shouldn't do this here.
1025 */
1026 id = sa1111_readl(sachip->base + SA1111_SKID);
1027 if ((id & SKID_ID_MASK) != SKID_SA1111_ID) {
1028 __sa1111_remove(sachip);
1029 dev_set_drvdata(dev, NULL);
1030 kfree(save);
1031 return 0;
1032 }
1033
1034 /*
1035 * First of all, wake up the chip.
1036 */
1037 sa1111_wake(sachip);
1038
1039 #ifdef CONFIG_ARCH_SA1100
1040 /* Enable the memory bus request/grant signals */
1041 sa1110_mb_enable();
1042 #endif
1043
1044 /*
1045 * Only lock for write ops. Also, sa1111_wake must be called with
1046 * released spinlock!
1047 */
1048 spin_lock_irqsave(&sachip->lock, flags);
1049
1050 sa1111_writel(0, sachip->base + SA1111_INTC + SA1111_INTEN0);
1051 sa1111_writel(0, sachip->base + SA1111_INTC + SA1111_INTEN1);
1052
1053 base = sachip->base;
1054 sa1111_writel(save->skcr, base + SA1111_SKCR);
1055 sa1111_writel(save->skpcr, base + SA1111_SKPCR);
1056 sa1111_writel(save->skcdr, base + SA1111_SKCDR);
1057 sa1111_writel(save->skaud, base + SA1111_SKAUD);
1058 sa1111_writel(save->skpwm0, base + SA1111_SKPWM0);
1059 sa1111_writel(save->skpwm1, base + SA1111_SKPWM1);
1060
1061 base = sachip->base + SA1111_INTC;
1062 sa1111_writel(save->intpol0, base + SA1111_INTPOL0);
1063 sa1111_writel(save->intpol1, base + SA1111_INTPOL1);
1064 sa1111_writel(save->inten0, base + SA1111_INTEN0);
1065 sa1111_writel(save->inten1, base + SA1111_INTEN1);
1066 sa1111_writel(save->wakepol0, base + SA1111_WAKEPOL0);
1067 sa1111_writel(save->wakepol1, base + SA1111_WAKEPOL1);
1068 sa1111_writel(save->wakeen0, base + SA1111_WAKEEN0);
1069 sa1111_writel(save->wakeen1, base + SA1111_WAKEEN1);
1070
1071 spin_unlock_irqrestore(&sachip->lock, flags);
1072
1073 sachip->saved_state = NULL;
1074 kfree(save);
1075
1076 return 0;
1077 }
1078
1079 #else
1080 #define sa1111_suspend_noirq NULL
1081 #define sa1111_resume_noirq NULL
1082 #endif
1083
1084 static int sa1111_probe(struct platform_device *pdev)
1085 {
1086 struct resource *mem;
1087 int irq;
1088
1089 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1090 if (!mem)
1091 return -EINVAL;
1092 irq = platform_get_irq(pdev, 0);
1093 if (irq < 0)
1094 return irq;
1095
1096 return __sa1111_probe(&pdev->dev, mem, irq);
1097 }
1098
1099 static int sa1111_remove(struct platform_device *pdev)
1100 {
1101 struct sa1111 *sachip = platform_get_drvdata(pdev);
1102
1103 if (sachip) {
1104 #ifdef CONFIG_PM
1105 kfree(sachip->saved_state);
1106 sachip->saved_state = NULL;
1107 #endif
1108 __sa1111_remove(sachip);
1109 platform_set_drvdata(pdev, NULL);
1110 }
1111
1112 return 0;
1113 }
1114
1115 static struct dev_pm_ops sa1111_pm_ops = {
1116 .suspend_noirq = sa1111_suspend_noirq,
1117 .resume_noirq = sa1111_resume_noirq,
1118 };
1119
1120 /*
1121 * Not sure if this should be on the system bus or not yet.
1122 * We really want some way to register a system device at
1123 * the per-machine level, and then have this driver pick
1124 * up the registered devices.
1125 *
1126 * We also need to handle the SDRAM configuration for
1127 * PXA250/SA1110 machine classes.
1128 */
1129 static struct platform_driver sa1111_device_driver = {
1130 .probe = sa1111_probe,
1131 .remove = sa1111_remove,
1132 .driver = {
1133 .name = "sa1111",
1134 .pm = &sa1111_pm_ops,
1135 },
1136 };
1137
1138 /*
1139 * Get the parent device driver (us) structure
1140 * from a child function device
1141 */
1142 static inline struct sa1111 *sa1111_chip_driver(struct sa1111_dev *sadev)
1143 {
1144 return (struct sa1111 *)dev_get_drvdata(sadev->dev.parent);
1145 }
1146
1147 /*
1148 * The bits in the opdiv field are non-linear.
1149 */
1150 static unsigned char opdiv_table[] = { 1, 4, 2, 8 };
1151
1152 static unsigned int __sa1111_pll_clock(struct sa1111 *sachip)
1153 {
1154 unsigned int skcdr, fbdiv, ipdiv, opdiv;
1155
1156 skcdr = sa1111_readl(sachip->base + SA1111_SKCDR);
1157
1158 fbdiv = (skcdr & 0x007f) + 2;
1159 ipdiv = ((skcdr & 0x0f80) >> 7) + 2;
1160 opdiv = opdiv_table[(skcdr & 0x3000) >> 12];
1161
1162 return 3686400 * fbdiv / (ipdiv * opdiv);
1163 }
1164
1165 /**
1166 * sa1111_pll_clock - return the current PLL clock frequency.
1167 * @sadev: SA1111 function block
1168 *
1169 * BUG: we should look at SKCR. We also blindly believe that
1170 * the chip is being fed with the 3.6864MHz clock.
1171 *
1172 * Returns the PLL clock in Hz.
1173 */
1174 unsigned int sa1111_pll_clock(struct sa1111_dev *sadev)
1175 {
1176 struct sa1111 *sachip = sa1111_chip_driver(sadev);
1177
1178 return __sa1111_pll_clock(sachip);
1179 }
1180 EXPORT_SYMBOL(sa1111_pll_clock);
1181
1182 /**
1183 * sa1111_select_audio_mode - select I2S or AC link mode
1184 * @sadev: SA1111 function block
1185 * @mode: One of %SA1111_AUDIO_ACLINK or %SA1111_AUDIO_I2S
1186 *
1187 * Frob the SKCR to select AC Link mode or I2S mode for
1188 * the audio block.
1189 */
1190 void sa1111_select_audio_mode(struct sa1111_dev *sadev, int mode)
1191 {
1192 struct sa1111 *sachip = sa1111_chip_driver(sadev);
1193 unsigned long flags;
1194 unsigned int val;
1195
1196 spin_lock_irqsave(&sachip->lock, flags);
1197
1198 val = sa1111_readl(sachip->base + SA1111_SKCR);
1199 if (mode == SA1111_AUDIO_I2S) {
1200 val &= ~SKCR_SELAC;
1201 } else {
1202 val |= SKCR_SELAC;
1203 }
1204 sa1111_writel(val, sachip->base + SA1111_SKCR);
1205
1206 spin_unlock_irqrestore(&sachip->lock, flags);
1207 }
1208 EXPORT_SYMBOL(sa1111_select_audio_mode);
1209
1210 /**
1211 * sa1111_set_audio_rate - set the audio sample rate
1212 * @sadev: SA1111 SAC function block
1213 * @rate: sample rate to select
1214 */
1215 int sa1111_set_audio_rate(struct sa1111_dev *sadev, int rate)
1216 {
1217 struct sa1111 *sachip = sa1111_chip_driver(sadev);
1218 unsigned int div;
1219
1220 if (sadev->devid != SA1111_DEVID_SAC)
1221 return -EINVAL;
1222
1223 div = (__sa1111_pll_clock(sachip) / 256 + rate / 2) / rate;
1224 if (div == 0)
1225 div = 1;
1226 if (div > 128)
1227 div = 128;
1228
1229 sa1111_writel(div - 1, sachip->base + SA1111_SKAUD);
1230
1231 return 0;
1232 }
1233 EXPORT_SYMBOL(sa1111_set_audio_rate);
1234
1235 /**
1236 * sa1111_get_audio_rate - get the audio sample rate
1237 * @sadev: SA1111 SAC function block device
1238 */
1239 int sa1111_get_audio_rate(struct sa1111_dev *sadev)
1240 {
1241 struct sa1111 *sachip = sa1111_chip_driver(sadev);
1242 unsigned long div;
1243
1244 if (sadev->devid != SA1111_DEVID_SAC)
1245 return -EINVAL;
1246
1247 div = sa1111_readl(sachip->base + SA1111_SKAUD) + 1;
1248
1249 return __sa1111_pll_clock(sachip) / (256 * div);
1250 }
1251 EXPORT_SYMBOL(sa1111_get_audio_rate);
1252
1253 void sa1111_set_io_dir(struct sa1111_dev *sadev,
1254 unsigned int bits, unsigned int dir,
1255 unsigned int sleep_dir)
1256 {
1257 struct sa1111 *sachip = sa1111_chip_driver(sadev);
1258 unsigned long flags;
1259 unsigned int val;
1260 void __iomem *gpio = sachip->base + SA1111_GPIO;
1261
1262 #define MODIFY_BITS(port, mask, dir) \
1263 if (mask) { \
1264 val = sa1111_readl(port); \
1265 val &= ~(mask); \
1266 val |= (dir) & (mask); \
1267 sa1111_writel(val, port); \
1268 }
1269
1270 spin_lock_irqsave(&sachip->lock, flags);
1271 MODIFY_BITS(gpio + SA1111_GPIO_PADDR, bits & 15, dir);
1272 MODIFY_BITS(gpio + SA1111_GPIO_PBDDR, (bits >> 8) & 255, dir >> 8);
1273 MODIFY_BITS(gpio + SA1111_GPIO_PCDDR, (bits >> 16) & 255, dir >> 16);
1274
1275 MODIFY_BITS(gpio + SA1111_GPIO_PASDR, bits & 15, sleep_dir);
1276 MODIFY_BITS(gpio + SA1111_GPIO_PBSDR, (bits >> 8) & 255, sleep_dir >> 8);
1277 MODIFY_BITS(gpio + SA1111_GPIO_PCSDR, (bits >> 16) & 255, sleep_dir >> 16);
1278 spin_unlock_irqrestore(&sachip->lock, flags);
1279 }
1280 EXPORT_SYMBOL(sa1111_set_io_dir);
1281
1282 void sa1111_set_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v)
1283 {
1284 struct sa1111 *sachip = sa1111_chip_driver(sadev);
1285 unsigned long flags;
1286 unsigned int val;
1287 void __iomem *gpio = sachip->base + SA1111_GPIO;
1288
1289 spin_lock_irqsave(&sachip->lock, flags);
1290 MODIFY_BITS(gpio + SA1111_GPIO_PADWR, bits & 15, v);
1291 MODIFY_BITS(gpio + SA1111_GPIO_PBDWR, (bits >> 8) & 255, v >> 8);
1292 MODIFY_BITS(gpio + SA1111_GPIO_PCDWR, (bits >> 16) & 255, v >> 16);
1293 spin_unlock_irqrestore(&sachip->lock, flags);
1294 }
1295 EXPORT_SYMBOL(sa1111_set_io);
1296
1297 void sa1111_set_sleep_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v)
1298 {
1299 struct sa1111 *sachip = sa1111_chip_driver(sadev);
1300 unsigned long flags;
1301 unsigned int val;
1302 void __iomem *gpio = sachip->base + SA1111_GPIO;
1303
1304 spin_lock_irqsave(&sachip->lock, flags);
1305 MODIFY_BITS(gpio + SA1111_GPIO_PASSR, bits & 15, v);
1306 MODIFY_BITS(gpio + SA1111_GPIO_PBSSR, (bits >> 8) & 255, v >> 8);
1307 MODIFY_BITS(gpio + SA1111_GPIO_PCSSR, (bits >> 16) & 255, v >> 16);
1308 spin_unlock_irqrestore(&sachip->lock, flags);
1309 }
1310 EXPORT_SYMBOL(sa1111_set_sleep_io);
1311
1312 /*
1313 * Individual device operations.
1314 */
1315
1316 /**
1317 * sa1111_enable_device - enable an on-chip SA1111 function block
1318 * @sadev: SA1111 function block device to enable
1319 */
1320 int sa1111_enable_device(struct sa1111_dev *sadev)
1321 {
1322 struct sa1111 *sachip = sa1111_chip_driver(sadev);
1323 unsigned long flags;
1324 unsigned int val;
1325 int ret = 0;
1326
1327 if (sachip->pdata && sachip->pdata->enable)
1328 ret = sachip->pdata->enable(sachip->pdata->data, sadev->devid);
1329
1330 if (ret == 0) {
1331 spin_lock_irqsave(&sachip->lock, flags);
1332 val = sa1111_readl(sachip->base + SA1111_SKPCR);
1333 sa1111_writel(val | sadev->skpcr_mask, sachip->base + SA1111_SKPCR);
1334 spin_unlock_irqrestore(&sachip->lock, flags);
1335 }
1336 return ret;
1337 }
1338 EXPORT_SYMBOL(sa1111_enable_device);
1339
1340 /**
1341 * sa1111_disable_device - disable an on-chip SA1111 function block
1342 * @sadev: SA1111 function block device to disable
1343 */
1344 void sa1111_disable_device(struct sa1111_dev *sadev)
1345 {
1346 struct sa1111 *sachip = sa1111_chip_driver(sadev);
1347 unsigned long flags;
1348 unsigned int val;
1349
1350 spin_lock_irqsave(&sachip->lock, flags);
1351 val = sa1111_readl(sachip->base + SA1111_SKPCR);
1352 sa1111_writel(val & ~sadev->skpcr_mask, sachip->base + SA1111_SKPCR);
1353 spin_unlock_irqrestore(&sachip->lock, flags);
1354
1355 if (sachip->pdata && sachip->pdata->disable)
1356 sachip->pdata->disable(sachip->pdata->data, sadev->devid);
1357 }
1358 EXPORT_SYMBOL(sa1111_disable_device);
1359
1360 int sa1111_get_irq(struct sa1111_dev *sadev, unsigned num)
1361 {
1362 if (num >= ARRAY_SIZE(sadev->irq))
1363 return -EINVAL;
1364 return sadev->irq[num];
1365 }
1366 EXPORT_SYMBOL_GPL(sa1111_get_irq);
1367
1368 /*
1369 * SA1111 "Register Access Bus."
1370 *
1371 * We model this as a regular bus type, and hang devices directly
1372 * off this.
1373 */
1374 static int sa1111_match(struct device *_dev, struct device_driver *_drv)
1375 {
1376 struct sa1111_dev *dev = to_sa1111_device(_dev);
1377 struct sa1111_driver *drv = SA1111_DRV(_drv);
1378
1379 return !!(dev->devid & drv->devid);
1380 }
1381
1382 static int sa1111_bus_suspend(struct device *dev, pm_message_t state)
1383 {
1384 struct sa1111_dev *sadev = to_sa1111_device(dev);
1385 struct sa1111_driver *drv = SA1111_DRV(dev->driver);
1386 int ret = 0;
1387
1388 if (drv && drv->suspend)
1389 ret = drv->suspend(sadev, state);
1390 return ret;
1391 }
1392
1393 static int sa1111_bus_resume(struct device *dev)
1394 {
1395 struct sa1111_dev *sadev = to_sa1111_device(dev);
1396 struct sa1111_driver *drv = SA1111_DRV(dev->driver);
1397 int ret = 0;
1398
1399 if (drv && drv->resume)
1400 ret = drv->resume(sadev);
1401 return ret;
1402 }
1403
1404 static void sa1111_bus_shutdown(struct device *dev)
1405 {
1406 struct sa1111_driver *drv = SA1111_DRV(dev->driver);
1407
1408 if (drv && drv->shutdown)
1409 drv->shutdown(to_sa1111_device(dev));
1410 }
1411
1412 static int sa1111_bus_probe(struct device *dev)
1413 {
1414 struct sa1111_dev *sadev = to_sa1111_device(dev);
1415 struct sa1111_driver *drv = SA1111_DRV(dev->driver);
1416 int ret = -ENODEV;
1417
1418 if (drv->probe)
1419 ret = drv->probe(sadev);
1420 return ret;
1421 }
1422
1423 static int sa1111_bus_remove(struct device *dev)
1424 {
1425 struct sa1111_dev *sadev = to_sa1111_device(dev);
1426 struct sa1111_driver *drv = SA1111_DRV(dev->driver);
1427 int ret = 0;
1428
1429 if (drv->remove)
1430 ret = drv->remove(sadev);
1431 return ret;
1432 }
1433
1434 struct bus_type sa1111_bus_type = {
1435 .name = "sa1111-rab",
1436 .match = sa1111_match,
1437 .probe = sa1111_bus_probe,
1438 .remove = sa1111_bus_remove,
1439 .suspend = sa1111_bus_suspend,
1440 .resume = sa1111_bus_resume,
1441 .shutdown = sa1111_bus_shutdown,
1442 };
1443 EXPORT_SYMBOL(sa1111_bus_type);
1444
1445 int sa1111_driver_register(struct sa1111_driver *driver)
1446 {
1447 driver->drv.bus = &sa1111_bus_type;
1448 return driver_register(&driver->drv);
1449 }
1450 EXPORT_SYMBOL(sa1111_driver_register);
1451
1452 void sa1111_driver_unregister(struct sa1111_driver *driver)
1453 {
1454 driver_unregister(&driver->drv);
1455 }
1456 EXPORT_SYMBOL(sa1111_driver_unregister);
1457
1458 #ifdef CONFIG_DMABOUNCE
1459 /*
1460 * According to the "Intel StrongARM SA-1111 Microprocessor Companion
1461 * Chip Specification Update" (June 2000), erratum #7, there is a
1462 * significant bug in the SA1111 SDRAM shared memory controller. If
1463 * an access to a region of memory above 1MB relative to the bank base,
1464 * it is important that address bit 10 _NOT_ be asserted. Depending
1465 * on the configuration of the RAM, bit 10 may correspond to one
1466 * of several different (processor-relative) address bits.
1467 *
1468 * This routine only identifies whether or not a given DMA address
1469 * is susceptible to the bug.
1470 *
1471 * This should only get called for sa1111_device types due to the
1472 * way we configure our device dma_masks.
1473 */
1474 static int sa1111_needs_bounce(struct device *dev, dma_addr_t addr, size_t size)
1475 {
1476 /*
1477 * Section 4.6 of the "Intel StrongARM SA-1111 Development Module
1478 * User's Guide" mentions that jumpers R51 and R52 control the
1479 * target of SA-1111 DMA (either SDRAM bank 0 on Assabet, or
1480 * SDRAM bank 1 on Neponset). The default configuration selects
1481 * Assabet, so any address in bank 1 is necessarily invalid.
1482 */
1483 return (machine_is_assabet() || machine_is_pfs168()) &&
1484 (addr >= 0xc8000000 || (addr + size) >= 0xc8000000);
1485 }
1486
1487 static int sa1111_notifier_call(struct notifier_block *n, unsigned long action,
1488 void *data)
1489 {
1490 struct sa1111_dev *dev = to_sa1111_device(data);
1491
1492 switch (action) {
1493 case BUS_NOTIFY_ADD_DEVICE:
1494 if (dev->dev.dma_mask && dev->dma_mask < 0xffffffffUL) {
1495 int ret = dmabounce_register_dev(&dev->dev, 1024, 4096,
1496 sa1111_needs_bounce);
1497 if (ret)
1498 dev_err(&dev->dev, "failed to register with dmabounce: %d\n", ret);
1499 }
1500 break;
1501
1502 case BUS_NOTIFY_DEL_DEVICE:
1503 if (dev->dev.dma_mask && dev->dma_mask < 0xffffffffUL)
1504 dmabounce_unregister_dev(&dev->dev);
1505 break;
1506 }
1507 return NOTIFY_OK;
1508 }
1509
1510 static struct notifier_block sa1111_bus_notifier = {
1511 .notifier_call = sa1111_notifier_call,
1512 };
1513 #endif
1514
1515 static int __init sa1111_init(void)
1516 {
1517 int ret = bus_register(&sa1111_bus_type);
1518 #ifdef CONFIG_DMABOUNCE
1519 if (ret == 0)
1520 bus_register_notifier(&sa1111_bus_type, &sa1111_bus_notifier);
1521 #endif
1522 if (ret == 0)
1523 platform_driver_register(&sa1111_device_driver);
1524 return ret;
1525 }
1526
1527 static void __exit sa1111_exit(void)
1528 {
1529 platform_driver_unregister(&sa1111_device_driver);
1530 #ifdef CONFIG_DMABOUNCE
1531 bus_unregister_notifier(&sa1111_bus_type, &sa1111_bus_notifier);
1532 #endif
1533 bus_unregister(&sa1111_bus_type);
1534 }
1535
1536 subsys_initcall(sa1111_init);
1537 module_exit(sa1111_exit);
1538
1539 MODULE_DESCRIPTION("Intel Corporation SA1111 core driver");
1540 MODULE_LICENSE("GPL");
Linux with added FPC-III support