mm: fix exec activate_mm vs TLB shootdown and lazy tlb switching race
[linux/fpc-iii.git] / arch / arm / kernel / hw_breakpoint.c
blobe61697fb7efea6b67cd20981ed6642624e292efa
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
15 * Copyright (C) 2009, 2010 ARM Limited
17 * Author: Will Deacon <will.deacon@arm.com>
21 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
22 * using the CPU's debug registers.
24 #define pr_fmt(fmt) "hw-breakpoint: " fmt
26 #include <linux/errno.h>
27 #include <linux/hardirq.h>
28 #include <linux/perf_event.h>
29 #include <linux/hw_breakpoint.h>
30 #include <linux/smp.h>
31 #include <linux/cpu_pm.h>
32 #include <linux/coresight.h>
34 #include <asm/cacheflush.h>
35 #include <asm/cputype.h>
36 #include <asm/current.h>
37 #include <asm/hw_breakpoint.h>
38 #include <asm/traps.h>
40 /* Breakpoint currently in use for each BRP. */
41 static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]);
43 /* Watchpoint currently in use for each WRP. */
44 static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]);
46 /* Number of BRP/WRP registers on this CPU. */
47 static int core_num_brps;
48 static int core_num_wrps;
50 /* Debug architecture version. */
51 static u8 debug_arch;
53 /* Does debug architecture support OS Save and Restore? */
54 static bool has_ossr;
56 /* Maximum supported watchpoint length. */
57 static u8 max_watchpoint_len;
59 #define READ_WB_REG_CASE(OP2, M, VAL) \
60 case ((OP2 << 4) + M): \
61 ARM_DBG_READ(c0, c ## M, OP2, VAL); \
62 break
64 #define WRITE_WB_REG_CASE(OP2, M, VAL) \
65 case ((OP2 << 4) + M): \
66 ARM_DBG_WRITE(c0, c ## M, OP2, VAL); \
67 break
69 #define GEN_READ_WB_REG_CASES(OP2, VAL) \
70 READ_WB_REG_CASE(OP2, 0, VAL); \
71 READ_WB_REG_CASE(OP2, 1, VAL); \
72 READ_WB_REG_CASE(OP2, 2, VAL); \
73 READ_WB_REG_CASE(OP2, 3, VAL); \
74 READ_WB_REG_CASE(OP2, 4, VAL); \
75 READ_WB_REG_CASE(OP2, 5, VAL); \
76 READ_WB_REG_CASE(OP2, 6, VAL); \
77 READ_WB_REG_CASE(OP2, 7, VAL); \
78 READ_WB_REG_CASE(OP2, 8, VAL); \
79 READ_WB_REG_CASE(OP2, 9, VAL); \
80 READ_WB_REG_CASE(OP2, 10, VAL); \
81 READ_WB_REG_CASE(OP2, 11, VAL); \
82 READ_WB_REG_CASE(OP2, 12, VAL); \
83 READ_WB_REG_CASE(OP2, 13, VAL); \
84 READ_WB_REG_CASE(OP2, 14, VAL); \
85 READ_WB_REG_CASE(OP2, 15, VAL)
87 #define GEN_WRITE_WB_REG_CASES(OP2, VAL) \
88 WRITE_WB_REG_CASE(OP2, 0, VAL); \
89 WRITE_WB_REG_CASE(OP2, 1, VAL); \
90 WRITE_WB_REG_CASE(OP2, 2, VAL); \
91 WRITE_WB_REG_CASE(OP2, 3, VAL); \
92 WRITE_WB_REG_CASE(OP2, 4, VAL); \
93 WRITE_WB_REG_CASE(OP2, 5, VAL); \
94 WRITE_WB_REG_CASE(OP2, 6, VAL); \
95 WRITE_WB_REG_CASE(OP2, 7, VAL); \
96 WRITE_WB_REG_CASE(OP2, 8, VAL); \
97 WRITE_WB_REG_CASE(OP2, 9, VAL); \
98 WRITE_WB_REG_CASE(OP2, 10, VAL); \
99 WRITE_WB_REG_CASE(OP2, 11, VAL); \
100 WRITE_WB_REG_CASE(OP2, 12, VAL); \
101 WRITE_WB_REG_CASE(OP2, 13, VAL); \
102 WRITE_WB_REG_CASE(OP2, 14, VAL); \
103 WRITE_WB_REG_CASE(OP2, 15, VAL)
105 static u32 read_wb_reg(int n)
107 u32 val = 0;
109 switch (n) {
110 GEN_READ_WB_REG_CASES(ARM_OP2_BVR, val);
111 GEN_READ_WB_REG_CASES(ARM_OP2_BCR, val);
112 GEN_READ_WB_REG_CASES(ARM_OP2_WVR, val);
113 GEN_READ_WB_REG_CASES(ARM_OP2_WCR, val);
114 default:
115 pr_warn("attempt to read from unknown breakpoint register %d\n",
119 return val;
122 static void write_wb_reg(int n, u32 val)
124 switch (n) {
125 GEN_WRITE_WB_REG_CASES(ARM_OP2_BVR, val);
126 GEN_WRITE_WB_REG_CASES(ARM_OP2_BCR, val);
127 GEN_WRITE_WB_REG_CASES(ARM_OP2_WVR, val);
128 GEN_WRITE_WB_REG_CASES(ARM_OP2_WCR, val);
129 default:
130 pr_warn("attempt to write to unknown breakpoint register %d\n",
133 isb();
136 /* Determine debug architecture. */
137 static u8 get_debug_arch(void)
139 u32 didr;
141 /* Do we implement the extended CPUID interface? */
142 if (((read_cpuid_id() >> 16) & 0xf) != 0xf) {
143 pr_warn_once("CPUID feature registers not supported. "
144 "Assuming v6 debug is present.\n");
145 return ARM_DEBUG_ARCH_V6;
148 ARM_DBG_READ(c0, c0, 0, didr);
149 return (didr >> 16) & 0xf;
152 u8 arch_get_debug_arch(void)
154 return debug_arch;
157 static int debug_arch_supported(void)
159 u8 arch = get_debug_arch();
161 /* We don't support the memory-mapped interface. */
162 return (arch >= ARM_DEBUG_ARCH_V6 && arch <= ARM_DEBUG_ARCH_V7_ECP14) ||
163 arch >= ARM_DEBUG_ARCH_V7_1;
166 /* Can we determine the watchpoint access type from the fsr? */
167 static int debug_exception_updates_fsr(void)
169 return get_debug_arch() >= ARM_DEBUG_ARCH_V8;
172 /* Determine number of WRP registers available. */
173 static int get_num_wrp_resources(void)
175 u32 didr;
176 ARM_DBG_READ(c0, c0, 0, didr);
177 return ((didr >> 28) & 0xf) + 1;
180 /* Determine number of BRP registers available. */
181 static int get_num_brp_resources(void)
183 u32 didr;
184 ARM_DBG_READ(c0, c0, 0, didr);
185 return ((didr >> 24) & 0xf) + 1;
188 /* Does this core support mismatch breakpoints? */
189 static int core_has_mismatch_brps(void)
191 return (get_debug_arch() >= ARM_DEBUG_ARCH_V7_ECP14 &&
192 get_num_brp_resources() > 1);
195 /* Determine number of usable WRPs available. */
196 static int get_num_wrps(void)
199 * On debug architectures prior to 7.1, when a watchpoint fires, the
200 * only way to work out which watchpoint it was is by disassembling
201 * the faulting instruction and working out the address of the memory
202 * access.
204 * Furthermore, we can only do this if the watchpoint was precise
205 * since imprecise watchpoints prevent us from calculating register
206 * based addresses.
208 * Providing we have more than 1 breakpoint register, we only report
209 * a single watchpoint register for the time being. This way, we always
210 * know which watchpoint fired. In the future we can either add a
211 * disassembler and address generation emulator, or we can insert a
212 * check to see if the DFAR is set on watchpoint exception entry
213 * [the ARM ARM states that the DFAR is UNKNOWN, but experience shows
214 * that it is set on some implementations].
216 if (get_debug_arch() < ARM_DEBUG_ARCH_V7_1)
217 return 1;
219 return get_num_wrp_resources();
222 /* Determine number of usable BRPs available. */
223 static int get_num_brps(void)
225 int brps = get_num_brp_resources();
226 return core_has_mismatch_brps() ? brps - 1 : brps;
230 * In order to access the breakpoint/watchpoint control registers,
231 * we must be running in debug monitor mode. Unfortunately, we can
232 * be put into halting debug mode at any time by an external debugger
233 * but there is nothing we can do to prevent that.
235 static int monitor_mode_enabled(void)
237 u32 dscr;
238 ARM_DBG_READ(c0, c1, 0, dscr);
239 return !!(dscr & ARM_DSCR_MDBGEN);
242 static int enable_monitor_mode(void)
244 u32 dscr;
245 ARM_DBG_READ(c0, c1, 0, dscr);
247 /* If monitor mode is already enabled, just return. */
248 if (dscr & ARM_DSCR_MDBGEN)
249 goto out;
251 /* Write to the corresponding DSCR. */
252 switch (get_debug_arch()) {
253 case ARM_DEBUG_ARCH_V6:
254 case ARM_DEBUG_ARCH_V6_1:
255 ARM_DBG_WRITE(c0, c1, 0, (dscr | ARM_DSCR_MDBGEN));
256 break;
257 case ARM_DEBUG_ARCH_V7_ECP14:
258 case ARM_DEBUG_ARCH_V7_1:
259 case ARM_DEBUG_ARCH_V8:
260 ARM_DBG_WRITE(c0, c2, 2, (dscr | ARM_DSCR_MDBGEN));
261 isb();
262 break;
263 default:
264 return -ENODEV;
267 /* Check that the write made it through. */
268 ARM_DBG_READ(c0, c1, 0, dscr);
269 if (!(dscr & ARM_DSCR_MDBGEN)) {
270 pr_warn_once("Failed to enable monitor mode on CPU %d.\n",
271 smp_processor_id());
272 return -EPERM;
275 out:
276 return 0;
279 int hw_breakpoint_slots(int type)
281 if (!debug_arch_supported())
282 return 0;
285 * We can be called early, so don't rely on
286 * our static variables being initialised.
288 switch (type) {
289 case TYPE_INST:
290 return get_num_brps();
291 case TYPE_DATA:
292 return get_num_wrps();
293 default:
294 pr_warn("unknown slot type: %d\n", type);
295 return 0;
300 * Check if 8-bit byte-address select is available.
301 * This clobbers WRP 0.
303 static u8 get_max_wp_len(void)
305 u32 ctrl_reg;
306 struct arch_hw_breakpoint_ctrl ctrl;
307 u8 size = 4;
309 if (debug_arch < ARM_DEBUG_ARCH_V7_ECP14)
310 goto out;
312 memset(&ctrl, 0, sizeof(ctrl));
313 ctrl.len = ARM_BREAKPOINT_LEN_8;
314 ctrl_reg = encode_ctrl_reg(ctrl);
316 write_wb_reg(ARM_BASE_WVR, 0);
317 write_wb_reg(ARM_BASE_WCR, ctrl_reg);
318 if ((read_wb_reg(ARM_BASE_WCR) & ctrl_reg) == ctrl_reg)
319 size = 8;
321 out:
322 return size;
325 u8 arch_get_max_wp_len(void)
327 return max_watchpoint_len;
331 * Install a perf counter breakpoint.
333 int arch_install_hw_breakpoint(struct perf_event *bp)
335 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
336 struct perf_event **slot, **slots;
337 int i, max_slots, ctrl_base, val_base;
338 u32 addr, ctrl;
340 addr = info->address;
341 ctrl = encode_ctrl_reg(info->ctrl) | 0x1;
343 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
344 /* Breakpoint */
345 ctrl_base = ARM_BASE_BCR;
346 val_base = ARM_BASE_BVR;
347 slots = this_cpu_ptr(bp_on_reg);
348 max_slots = core_num_brps;
349 } else {
350 /* Watchpoint */
351 ctrl_base = ARM_BASE_WCR;
352 val_base = ARM_BASE_WVR;
353 slots = this_cpu_ptr(wp_on_reg);
354 max_slots = core_num_wrps;
357 for (i = 0; i < max_slots; ++i) {
358 slot = &slots[i];
360 if (!*slot) {
361 *slot = bp;
362 break;
366 if (i == max_slots) {
367 pr_warn("Can't find any breakpoint slot\n");
368 return -EBUSY;
371 /* Override the breakpoint data with the step data. */
372 if (info->step_ctrl.enabled) {
373 addr = info->trigger & ~0x3;
374 ctrl = encode_ctrl_reg(info->step_ctrl);
375 if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE) {
376 i = 0;
377 ctrl_base = ARM_BASE_BCR + core_num_brps;
378 val_base = ARM_BASE_BVR + core_num_brps;
382 /* Setup the address register. */
383 write_wb_reg(val_base + i, addr);
385 /* Setup the control register. */
386 write_wb_reg(ctrl_base + i, ctrl);
387 return 0;
390 void arch_uninstall_hw_breakpoint(struct perf_event *bp)
392 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
393 struct perf_event **slot, **slots;
394 int i, max_slots, base;
396 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
397 /* Breakpoint */
398 base = ARM_BASE_BCR;
399 slots = this_cpu_ptr(bp_on_reg);
400 max_slots = core_num_brps;
401 } else {
402 /* Watchpoint */
403 base = ARM_BASE_WCR;
404 slots = this_cpu_ptr(wp_on_reg);
405 max_slots = core_num_wrps;
408 /* Remove the breakpoint. */
409 for (i = 0; i < max_slots; ++i) {
410 slot = &slots[i];
412 if (*slot == bp) {
413 *slot = NULL;
414 break;
418 if (i == max_slots) {
419 pr_warn("Can't find any breakpoint slot\n");
420 return;
423 /* Ensure that we disable the mismatch breakpoint. */
424 if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE &&
425 info->step_ctrl.enabled) {
426 i = 0;
427 base = ARM_BASE_BCR + core_num_brps;
430 /* Reset the control register. */
431 write_wb_reg(base + i, 0);
434 static int get_hbp_len(u8 hbp_len)
436 unsigned int len_in_bytes = 0;
438 switch (hbp_len) {
439 case ARM_BREAKPOINT_LEN_1:
440 len_in_bytes = 1;
441 break;
442 case ARM_BREAKPOINT_LEN_2:
443 len_in_bytes = 2;
444 break;
445 case ARM_BREAKPOINT_LEN_4:
446 len_in_bytes = 4;
447 break;
448 case ARM_BREAKPOINT_LEN_8:
449 len_in_bytes = 8;
450 break;
453 return len_in_bytes;
457 * Check whether bp virtual address is in kernel space.
459 int arch_check_bp_in_kernelspace(struct perf_event *bp)
461 unsigned int len;
462 unsigned long va;
463 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
465 va = info->address;
466 len = get_hbp_len(info->ctrl.len);
468 return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
472 * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl.
473 * Hopefully this will disappear when ptrace can bypass the conversion
474 * to generic breakpoint descriptions.
476 int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
477 int *gen_len, int *gen_type)
479 /* Type */
480 switch (ctrl.type) {
481 case ARM_BREAKPOINT_EXECUTE:
482 *gen_type = HW_BREAKPOINT_X;
483 break;
484 case ARM_BREAKPOINT_LOAD:
485 *gen_type = HW_BREAKPOINT_R;
486 break;
487 case ARM_BREAKPOINT_STORE:
488 *gen_type = HW_BREAKPOINT_W;
489 break;
490 case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE:
491 *gen_type = HW_BREAKPOINT_RW;
492 break;
493 default:
494 return -EINVAL;
497 /* Len */
498 switch (ctrl.len) {
499 case ARM_BREAKPOINT_LEN_1:
500 *gen_len = HW_BREAKPOINT_LEN_1;
501 break;
502 case ARM_BREAKPOINT_LEN_2:
503 *gen_len = HW_BREAKPOINT_LEN_2;
504 break;
505 case ARM_BREAKPOINT_LEN_4:
506 *gen_len = HW_BREAKPOINT_LEN_4;
507 break;
508 case ARM_BREAKPOINT_LEN_8:
509 *gen_len = HW_BREAKPOINT_LEN_8;
510 break;
511 default:
512 return -EINVAL;
515 return 0;
519 * Construct an arch_hw_breakpoint from a perf_event.
521 static int arch_build_bp_info(struct perf_event *bp)
523 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
525 /* Type */
526 switch (bp->attr.bp_type) {
527 case HW_BREAKPOINT_X:
528 info->ctrl.type = ARM_BREAKPOINT_EXECUTE;
529 break;
530 case HW_BREAKPOINT_R:
531 info->ctrl.type = ARM_BREAKPOINT_LOAD;
532 break;
533 case HW_BREAKPOINT_W:
534 info->ctrl.type = ARM_BREAKPOINT_STORE;
535 break;
536 case HW_BREAKPOINT_RW:
537 info->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE;
538 break;
539 default:
540 return -EINVAL;
543 /* Len */
544 switch (bp->attr.bp_len) {
545 case HW_BREAKPOINT_LEN_1:
546 info->ctrl.len = ARM_BREAKPOINT_LEN_1;
547 break;
548 case HW_BREAKPOINT_LEN_2:
549 info->ctrl.len = ARM_BREAKPOINT_LEN_2;
550 break;
551 case HW_BREAKPOINT_LEN_4:
552 info->ctrl.len = ARM_BREAKPOINT_LEN_4;
553 break;
554 case HW_BREAKPOINT_LEN_8:
555 info->ctrl.len = ARM_BREAKPOINT_LEN_8;
556 if ((info->ctrl.type != ARM_BREAKPOINT_EXECUTE)
557 && max_watchpoint_len >= 8)
558 break;
559 default:
560 return -EINVAL;
564 * Breakpoints must be of length 2 (thumb) or 4 (ARM) bytes.
565 * Watchpoints can be of length 1, 2, 4 or 8 bytes if supported
566 * by the hardware and must be aligned to the appropriate number of
567 * bytes.
569 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE &&
570 info->ctrl.len != ARM_BREAKPOINT_LEN_2 &&
571 info->ctrl.len != ARM_BREAKPOINT_LEN_4)
572 return -EINVAL;
574 /* Address */
575 info->address = bp->attr.bp_addr;
577 /* Privilege */
578 info->ctrl.privilege = ARM_BREAKPOINT_USER;
579 if (arch_check_bp_in_kernelspace(bp))
580 info->ctrl.privilege |= ARM_BREAKPOINT_PRIV;
582 /* Enabled? */
583 info->ctrl.enabled = !bp->attr.disabled;
585 /* Mismatch */
586 info->ctrl.mismatch = 0;
588 return 0;
592 * Validate the arch-specific HW Breakpoint register settings.
594 int arch_validate_hwbkpt_settings(struct perf_event *bp)
596 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
597 int ret = 0;
598 u32 offset, alignment_mask = 0x3;
600 /* Ensure that we are in monitor debug mode. */
601 if (!monitor_mode_enabled())
602 return -ENODEV;
604 /* Build the arch_hw_breakpoint. */
605 ret = arch_build_bp_info(bp);
606 if (ret)
607 goto out;
609 /* Check address alignment. */
610 if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
611 alignment_mask = 0x7;
612 offset = info->address & alignment_mask;
613 switch (offset) {
614 case 0:
615 /* Aligned */
616 break;
617 case 1:
618 case 2:
619 /* Allow halfword watchpoints and breakpoints. */
620 if (info->ctrl.len == ARM_BREAKPOINT_LEN_2)
621 break;
622 case 3:
623 /* Allow single byte watchpoint. */
624 if (info->ctrl.len == ARM_BREAKPOINT_LEN_1)
625 break;
626 default:
627 ret = -EINVAL;
628 goto out;
631 info->address &= ~alignment_mask;
632 info->ctrl.len <<= offset;
634 if (is_default_overflow_handler(bp)) {
636 * Mismatch breakpoints are required for single-stepping
637 * breakpoints.
639 if (!core_has_mismatch_brps())
640 return -EINVAL;
642 /* We don't allow mismatch breakpoints in kernel space. */
643 if (arch_check_bp_in_kernelspace(bp))
644 return -EPERM;
647 * Per-cpu breakpoints are not supported by our stepping
648 * mechanism.
650 if (!bp->hw.target)
651 return -EINVAL;
654 * We only support specific access types if the fsr
655 * reports them.
657 if (!debug_exception_updates_fsr() &&
658 (info->ctrl.type == ARM_BREAKPOINT_LOAD ||
659 info->ctrl.type == ARM_BREAKPOINT_STORE))
660 return -EINVAL;
663 out:
664 return ret;
668 * Enable/disable single-stepping over the breakpoint bp at address addr.
670 static void enable_single_step(struct perf_event *bp, u32 addr)
672 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
674 arch_uninstall_hw_breakpoint(bp);
675 info->step_ctrl.mismatch = 1;
676 info->step_ctrl.len = ARM_BREAKPOINT_LEN_4;
677 info->step_ctrl.type = ARM_BREAKPOINT_EXECUTE;
678 info->step_ctrl.privilege = info->ctrl.privilege;
679 info->step_ctrl.enabled = 1;
680 info->trigger = addr;
681 arch_install_hw_breakpoint(bp);
684 static void disable_single_step(struct perf_event *bp)
686 arch_uninstall_hw_breakpoint(bp);
687 counter_arch_bp(bp)->step_ctrl.enabled = 0;
688 arch_install_hw_breakpoint(bp);
692 * Arm32 hardware does not always report a watchpoint hit address that matches
693 * one of the watchpoints set. It can also report an address "near" the
694 * watchpoint if a single instruction access both watched and unwatched
695 * addresses. There is no straight-forward way, short of disassembling the
696 * offending instruction, to map that address back to the watchpoint. This
697 * function computes the distance of the memory access from the watchpoint as a
698 * heuristic for the likelyhood that a given access triggered the watchpoint.
700 * See this same function in the arm64 platform code, which has the same
701 * problem.
703 * The function returns the distance of the address from the bytes watched by
704 * the watchpoint. In case of an exact match, it returns 0.
706 static u32 get_distance_from_watchpoint(unsigned long addr, u32 val,
707 struct arch_hw_breakpoint_ctrl *ctrl)
709 u32 wp_low, wp_high;
710 u32 lens, lene;
712 lens = __ffs(ctrl->len);
713 lene = __fls(ctrl->len);
715 wp_low = val + lens;
716 wp_high = val + lene;
717 if (addr < wp_low)
718 return wp_low - addr;
719 else if (addr > wp_high)
720 return addr - wp_high;
721 else
722 return 0;
725 static int watchpoint_fault_on_uaccess(struct pt_regs *regs,
726 struct arch_hw_breakpoint *info)
728 return !user_mode(regs) && info->ctrl.privilege == ARM_BREAKPOINT_USER;
731 static void watchpoint_handler(unsigned long addr, unsigned int fsr,
732 struct pt_regs *regs)
734 int i, access, closest_match = 0;
735 u32 min_dist = -1, dist;
736 u32 val, ctrl_reg;
737 struct perf_event *wp, **slots;
738 struct arch_hw_breakpoint *info;
739 struct arch_hw_breakpoint_ctrl ctrl;
741 slots = this_cpu_ptr(wp_on_reg);
744 * Find all watchpoints that match the reported address. If no exact
745 * match is found. Attribute the hit to the closest watchpoint.
747 rcu_read_lock();
748 for (i = 0; i < core_num_wrps; ++i) {
749 wp = slots[i];
750 if (wp == NULL)
751 continue;
754 * The DFAR is an unknown value on debug architectures prior
755 * to 7.1. Since we only allow a single watchpoint on these
756 * older CPUs, we can set the trigger to the lowest possible
757 * faulting address.
759 if (debug_arch < ARM_DEBUG_ARCH_V7_1) {
760 BUG_ON(i > 0);
761 info = counter_arch_bp(wp);
762 info->trigger = wp->attr.bp_addr;
763 } else {
764 /* Check that the access type matches. */
765 if (debug_exception_updates_fsr()) {
766 access = (fsr & ARM_FSR_ACCESS_MASK) ?
767 HW_BREAKPOINT_W : HW_BREAKPOINT_R;
768 if (!(access & hw_breakpoint_type(wp)))
769 continue;
772 val = read_wb_reg(ARM_BASE_WVR + i);
773 ctrl_reg = read_wb_reg(ARM_BASE_WCR + i);
774 decode_ctrl_reg(ctrl_reg, &ctrl);
775 dist = get_distance_from_watchpoint(addr, val, &ctrl);
776 if (dist < min_dist) {
777 min_dist = dist;
778 closest_match = i;
780 /* Is this an exact match? */
781 if (dist != 0)
782 continue;
784 /* We have a winner. */
785 info = counter_arch_bp(wp);
786 info->trigger = addr;
789 pr_debug("watchpoint fired: address = 0x%x\n", info->trigger);
792 * If we triggered a user watchpoint from a uaccess routine,
793 * then handle the stepping ourselves since userspace really
794 * can't help us with this.
796 if (watchpoint_fault_on_uaccess(regs, info))
797 goto step;
799 perf_bp_event(wp, regs);
802 * Defer stepping to the overflow handler if one is installed.
803 * Otherwise, insert a temporary mismatch breakpoint so that
804 * we can single-step over the watchpoint trigger.
806 if (!is_default_overflow_handler(wp))
807 continue;
808 step:
809 enable_single_step(wp, instruction_pointer(regs));
812 if (min_dist > 0 && min_dist != -1) {
813 /* No exact match found. */
814 wp = slots[closest_match];
815 info = counter_arch_bp(wp);
816 info->trigger = addr;
817 pr_debug("watchpoint fired: address = 0x%x\n", info->trigger);
818 perf_bp_event(wp, regs);
819 if (is_default_overflow_handler(wp))
820 enable_single_step(wp, instruction_pointer(regs));
823 rcu_read_unlock();
826 static void watchpoint_single_step_handler(unsigned long pc)
828 int i;
829 struct perf_event *wp, **slots;
830 struct arch_hw_breakpoint *info;
832 slots = this_cpu_ptr(wp_on_reg);
834 for (i = 0; i < core_num_wrps; ++i) {
835 rcu_read_lock();
837 wp = slots[i];
839 if (wp == NULL)
840 goto unlock;
842 info = counter_arch_bp(wp);
843 if (!info->step_ctrl.enabled)
844 goto unlock;
847 * Restore the original watchpoint if we've completed the
848 * single-step.
850 if (info->trigger != pc)
851 disable_single_step(wp);
853 unlock:
854 rcu_read_unlock();
858 static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs)
860 int i;
861 u32 ctrl_reg, val, addr;
862 struct perf_event *bp, **slots;
863 struct arch_hw_breakpoint *info;
864 struct arch_hw_breakpoint_ctrl ctrl;
866 slots = this_cpu_ptr(bp_on_reg);
868 /* The exception entry code places the amended lr in the PC. */
869 addr = regs->ARM_pc;
871 /* Check the currently installed breakpoints first. */
872 for (i = 0; i < core_num_brps; ++i) {
873 rcu_read_lock();
875 bp = slots[i];
877 if (bp == NULL)
878 goto unlock;
880 info = counter_arch_bp(bp);
882 /* Check if the breakpoint value matches. */
883 val = read_wb_reg(ARM_BASE_BVR + i);
884 if (val != (addr & ~0x3))
885 goto mismatch;
887 /* Possible match, check the byte address select to confirm. */
888 ctrl_reg = read_wb_reg(ARM_BASE_BCR + i);
889 decode_ctrl_reg(ctrl_reg, &ctrl);
890 if ((1 << (addr & 0x3)) & ctrl.len) {
891 info->trigger = addr;
892 pr_debug("breakpoint fired: address = 0x%x\n", addr);
893 perf_bp_event(bp, regs);
894 if (!bp->overflow_handler)
895 enable_single_step(bp, addr);
896 goto unlock;
899 mismatch:
900 /* If we're stepping a breakpoint, it can now be restored. */
901 if (info->step_ctrl.enabled)
902 disable_single_step(bp);
903 unlock:
904 rcu_read_unlock();
907 /* Handle any pending watchpoint single-step breakpoints. */
908 watchpoint_single_step_handler(addr);
912 * Called from either the Data Abort Handler [watchpoint] or the
913 * Prefetch Abort Handler [breakpoint] with interrupts disabled.
915 static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
916 struct pt_regs *regs)
918 int ret = 0;
919 u32 dscr;
921 preempt_disable();
923 if (interrupts_enabled(regs))
924 local_irq_enable();
926 /* We only handle watchpoints and hardware breakpoints. */
927 ARM_DBG_READ(c0, c1, 0, dscr);
929 /* Perform perf callbacks. */
930 switch (ARM_DSCR_MOE(dscr)) {
931 case ARM_ENTRY_BREAKPOINT:
932 breakpoint_handler(addr, regs);
933 break;
934 case ARM_ENTRY_ASYNC_WATCHPOINT:
935 WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n");
936 case ARM_ENTRY_SYNC_WATCHPOINT:
937 watchpoint_handler(addr, fsr, regs);
938 break;
939 default:
940 ret = 1; /* Unhandled fault. */
943 preempt_enable();
945 return ret;
949 * One-time initialisation.
951 static cpumask_t debug_err_mask;
953 static int debug_reg_trap(struct pt_regs *regs, unsigned int instr)
955 int cpu = smp_processor_id();
957 pr_warn("Debug register access (0x%x) caused undefined instruction on CPU %d\n",
958 instr, cpu);
960 /* Set the error flag for this CPU and skip the faulting instruction. */
961 cpumask_set_cpu(cpu, &debug_err_mask);
962 instruction_pointer(regs) += 4;
963 return 0;
966 static struct undef_hook debug_reg_hook = {
967 .instr_mask = 0x0fe80f10,
968 .instr_val = 0x0e000e10,
969 .fn = debug_reg_trap,
972 /* Does this core support OS Save and Restore? */
973 static bool core_has_os_save_restore(void)
975 u32 oslsr;
977 switch (get_debug_arch()) {
978 case ARM_DEBUG_ARCH_V7_1:
979 return true;
980 case ARM_DEBUG_ARCH_V7_ECP14:
981 ARM_DBG_READ(c1, c1, 4, oslsr);
982 if (oslsr & ARM_OSLSR_OSLM0)
983 return true;
984 default:
985 return false;
989 static void reset_ctrl_regs(unsigned int cpu)
991 int i, raw_num_brps, err = 0;
992 u32 val;
995 * v7 debug contains save and restore registers so that debug state
996 * can be maintained across low-power modes without leaving the debug
997 * logic powered up. It is IMPLEMENTATION DEFINED whether we can access
998 * the debug registers out of reset, so we must unlock the OS Lock
999 * Access Register to avoid taking undefined instruction exceptions
1000 * later on.
1002 switch (debug_arch) {
1003 case ARM_DEBUG_ARCH_V6:
1004 case ARM_DEBUG_ARCH_V6_1:
1005 /* ARMv6 cores clear the registers out of reset. */
1006 goto out_mdbgen;
1007 case ARM_DEBUG_ARCH_V7_ECP14:
1009 * Ensure sticky power-down is clear (i.e. debug logic is
1010 * powered up).
1012 ARM_DBG_READ(c1, c5, 4, val);
1013 if ((val & 0x1) == 0)
1014 err = -EPERM;
1016 if (!has_ossr)
1017 goto clear_vcr;
1018 break;
1019 case ARM_DEBUG_ARCH_V7_1:
1021 * Ensure the OS double lock is clear.
1023 ARM_DBG_READ(c1, c3, 4, val);
1024 if ((val & 0x1) == 1)
1025 err = -EPERM;
1026 break;
1029 if (err) {
1030 pr_warn_once("CPU %d debug is powered down!\n", cpu);
1031 cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
1032 return;
1036 * Unconditionally clear the OS lock by writing a value
1037 * other than CS_LAR_KEY to the access register.
1039 ARM_DBG_WRITE(c1, c0, 4, ~CORESIGHT_UNLOCK);
1040 isb();
1043 * Clear any configured vector-catch events before
1044 * enabling monitor mode.
1046 clear_vcr:
1047 ARM_DBG_WRITE(c0, c7, 0, 0);
1048 isb();
1050 if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
1051 pr_warn_once("CPU %d failed to disable vector catch\n", cpu);
1052 return;
1056 * The control/value register pairs are UNKNOWN out of reset so
1057 * clear them to avoid spurious debug events.
1059 raw_num_brps = get_num_brp_resources();
1060 for (i = 0; i < raw_num_brps; ++i) {
1061 write_wb_reg(ARM_BASE_BCR + i, 0UL);
1062 write_wb_reg(ARM_BASE_BVR + i, 0UL);
1065 for (i = 0; i < core_num_wrps; ++i) {
1066 write_wb_reg(ARM_BASE_WCR + i, 0UL);
1067 write_wb_reg(ARM_BASE_WVR + i, 0UL);
1070 if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
1071 pr_warn_once("CPU %d failed to clear debug register pairs\n", cpu);
1072 return;
1076 * Have a crack at enabling monitor mode. We don't actually need
1077 * it yet, but reporting an error early is useful if it fails.
1079 out_mdbgen:
1080 if (enable_monitor_mode())
1081 cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
1084 static int dbg_reset_online(unsigned int cpu)
1086 local_irq_disable();
1087 reset_ctrl_regs(cpu);
1088 local_irq_enable();
1089 return 0;
1092 #ifdef CONFIG_CPU_PM
1093 static int dbg_cpu_pm_notify(struct notifier_block *self, unsigned long action,
1094 void *v)
1096 if (action == CPU_PM_EXIT)
1097 reset_ctrl_regs(smp_processor_id());
1099 return NOTIFY_OK;
1102 static struct notifier_block dbg_cpu_pm_nb = {
1103 .notifier_call = dbg_cpu_pm_notify,
1106 static void __init pm_init(void)
1108 cpu_pm_register_notifier(&dbg_cpu_pm_nb);
1110 #else
1111 static inline void pm_init(void)
1114 #endif
1116 static int __init arch_hw_breakpoint_init(void)
1118 int ret;
1120 debug_arch = get_debug_arch();
1122 if (!debug_arch_supported()) {
1123 pr_info("debug architecture 0x%x unsupported.\n", debug_arch);
1124 return 0;
1128 * Scorpion CPUs (at least those in APQ8060) seem to set DBGPRSR.SPD
1129 * whenever a WFI is issued, even if the core is not powered down, in
1130 * violation of the architecture. When DBGPRSR.SPD is set, accesses to
1131 * breakpoint and watchpoint registers are treated as undefined, so
1132 * this results in boot time and runtime failures when these are
1133 * accessed and we unexpectedly take a trap.
1135 * It's not clear if/how this can be worked around, so we blacklist
1136 * Scorpion CPUs to avoid these issues.
1138 if (read_cpuid_part() == ARM_CPU_PART_SCORPION) {
1139 pr_info("Scorpion CPU detected. Hardware breakpoints and watchpoints disabled\n");
1140 return 0;
1143 has_ossr = core_has_os_save_restore();
1145 /* Determine how many BRPs/WRPs are available. */
1146 core_num_brps = get_num_brps();
1147 core_num_wrps = get_num_wrps();
1150 * We need to tread carefully here because DBGSWENABLE may be
1151 * driven low on this core and there isn't an architected way to
1152 * determine that.
1154 cpus_read_lock();
1155 register_undef_hook(&debug_reg_hook);
1158 * Register CPU notifier which resets the breakpoint resources. We
1159 * assume that a halting debugger will leave the world in a nice state
1160 * for us.
1162 ret = cpuhp_setup_state_cpuslocked(CPUHP_AP_ONLINE_DYN,
1163 "arm/hw_breakpoint:online",
1164 dbg_reset_online, NULL);
1165 unregister_undef_hook(&debug_reg_hook);
1166 if (WARN_ON(ret < 0) || !cpumask_empty(&debug_err_mask)) {
1167 core_num_brps = 0;
1168 core_num_wrps = 0;
1169 if (ret > 0)
1170 cpuhp_remove_state_nocalls_cpuslocked(ret);
1171 cpus_read_unlock();
1172 return 0;
1175 pr_info("found %d " "%s" "breakpoint and %d watchpoint registers.\n",
1176 core_num_brps, core_has_mismatch_brps() ? "(+1 reserved) " :
1177 "", core_num_wrps);
1179 /* Work out the maximum supported watchpoint length. */
1180 max_watchpoint_len = get_max_wp_len();
1181 pr_info("maximum watchpoint size is %u bytes.\n",
1182 max_watchpoint_len);
1184 /* Register debug fault handler. */
1185 hook_fault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP,
1186 TRAP_HWBKPT, "watchpoint debug exception");
1187 hook_ifault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP,
1188 TRAP_HWBKPT, "breakpoint debug exception");
1189 cpus_read_unlock();
1191 /* Register PM notifiers. */
1192 pm_init();
1193 return 0;
1195 arch_initcall(arch_hw_breakpoint_init);
1197 void hw_breakpoint_pmu_read(struct perf_event *bp)
1202 * Dummy function to register with die_notifier.
1204 int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
1205 unsigned long val, void *data)
1207 return NOTIFY_DONE;