2 * iop13xx IRQ handling / support functions
3 * Copyright (c) 2005-2006, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/list.h>
22 #include <linux/sysctl.h>
23 #include <linux/uaccess.h>
24 #include <asm/mach/irq.h>
26 #include <mach/hardware.h>
27 #include <mach/irqs.h>
30 /* INTCTL0 CP6 R0 Page 4
32 static u32
read_intctl_0(void)
35 asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val
));
38 static void write_intctl_0(u32 val
)
40 asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val
));
43 /* INTCTL1 CP6 R1 Page 4
45 static u32
read_intctl_1(void)
48 asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val
));
51 static void write_intctl_1(u32 val
)
53 asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val
));
56 /* INTCTL2 CP6 R2 Page 4
58 static u32
read_intctl_2(void)
61 asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val
));
64 static void write_intctl_2(u32 val
)
66 asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val
));
69 /* INTCTL3 CP6 R3 Page 4
71 static u32
read_intctl_3(void)
74 asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val
));
77 static void write_intctl_3(u32 val
)
79 asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val
));
82 /* INTSTR0 CP6 R0 Page 5
84 static void write_intstr_0(u32 val
)
86 asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val
));
89 /* INTSTR1 CP6 R1 Page 5
91 static void write_intstr_1(u32 val
)
93 asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val
));
96 /* INTSTR2 CP6 R2 Page 5
98 static void write_intstr_2(u32 val
)
100 asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val
));
103 /* INTSTR3 CP6 R3 Page 5
105 static void write_intstr_3(u32 val
)
107 asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val
));
110 /* INTBASE CP6 R0 Page 2
112 static void write_intbase(u32 val
)
114 asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val
));
117 /* INTSIZE CP6 R2 Page 2
119 static void write_intsize(u32 val
)
121 asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val
));
124 /* 0 = Interrupt Masked and 1 = Interrupt not masked */
126 iop13xx_irq_mask0 (struct irq_data
*d
)
128 write_intctl_0(read_intctl_0() & ~(1 << (d
->irq
- 0)));
132 iop13xx_irq_mask1 (struct irq_data
*d
)
134 write_intctl_1(read_intctl_1() & ~(1 << (d
->irq
- 32)));
138 iop13xx_irq_mask2 (struct irq_data
*d
)
140 write_intctl_2(read_intctl_2() & ~(1 << (d
->irq
- 64)));
144 iop13xx_irq_mask3 (struct irq_data
*d
)
146 write_intctl_3(read_intctl_3() & ~(1 << (d
->irq
- 96)));
150 iop13xx_irq_unmask0(struct irq_data
*d
)
152 write_intctl_0(read_intctl_0() | (1 << (d
->irq
- 0)));
156 iop13xx_irq_unmask1(struct irq_data
*d
)
158 write_intctl_1(read_intctl_1() | (1 << (d
->irq
- 32)));
162 iop13xx_irq_unmask2(struct irq_data
*d
)
164 write_intctl_2(read_intctl_2() | (1 << (d
->irq
- 64)));
168 iop13xx_irq_unmask3(struct irq_data
*d
)
170 write_intctl_3(read_intctl_3() | (1 << (d
->irq
- 96)));
173 static struct irq_chip iop13xx_irqchip1
= {
175 .irq_ack
= iop13xx_irq_mask0
,
176 .irq_mask
= iop13xx_irq_mask0
,
177 .irq_unmask
= iop13xx_irq_unmask0
,
180 static struct irq_chip iop13xx_irqchip2
= {
182 .irq_ack
= iop13xx_irq_mask1
,
183 .irq_mask
= iop13xx_irq_mask1
,
184 .irq_unmask
= iop13xx_irq_unmask1
,
187 static struct irq_chip iop13xx_irqchip3
= {
189 .irq_ack
= iop13xx_irq_mask2
,
190 .irq_mask
= iop13xx_irq_mask2
,
191 .irq_unmask
= iop13xx_irq_unmask2
,
194 static struct irq_chip iop13xx_irqchip4
= {
196 .irq_ack
= iop13xx_irq_mask3
,
197 .irq_mask
= iop13xx_irq_mask3
,
198 .irq_unmask
= iop13xx_irq_unmask3
,
201 extern void iop_init_cp6_handler(void);
203 void __init
iop13xx_init_irq(void)
207 iop_init_cp6_handler();
209 /* disable all interrupts */
215 /* treat all as IRQ */
221 /* initialize the interrupt vector generator */
222 write_intbase(INTBASE
);
223 write_intsize(INTSIZE_4
);
225 for(i
= 0; i
<= IRQ_IOP13XX_HPI
; i
++) {
227 irq_set_chip(i
, &iop13xx_irqchip1
);
229 irq_set_chip(i
, &iop13xx_irqchip2
);
231 irq_set_chip(i
, &iop13xx_irqchip3
);
233 irq_set_chip(i
, &iop13xx_irqchip4
);
235 irq_set_handler(i
, handle_level_irq
);
236 irq_clear_status_flags(i
, IRQ_NOREQUEST
| IRQ_NOPROBE
);