arch/arm/mach-omap2/display.c

   1 /*
   2  * OMAP2plus display device setup / initialization.
   3  *
   4  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   5  *      Senthilvadivu Guruswamy
   6  *      Sumit Semwal
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  13  * kind, whether express or implied; without even the implied warranty
  14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/string.h>
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/io.h>
  23 #include <linux/clk.h>
  24 #include <linux/err.h>
  25 #include <linux/delay.h>
  26 #include <linux/of.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/slab.h>
  29 #include <linux/mfd/syscon.h>
  30 #include <linux/regmap.h>
  31
  32 #include <linux/platform_data/omapdss.h>
  33 #include "omap_hwmod.h"
  34 #include "omap_device.h"
  35 #include "omap-pm.h"
  36 #include "common.h"
  37
  38 #include "soc.h"
  39 #include "iomap.h"
  40 #include "control.h"
  41 #include "display.h"
  42 #include "prm.h"
  43
  44 #define DISPC_CONTROL           0x0040
  45 #define DISPC_CONTROL2          0x0238
  46 #define DISPC_CONTROL3          0x0848
  47 #define DISPC_IRQSTATUS         0x0018
  48
  49 #define DSS_CONTROL             0x40
  50 #define DSS_SDI_CONTROL         0x44
  51 #define DSS_PLL_CONTROL         0x48
  52
  53 #define LCD_EN_MASK             (0x1 << 0)
  54 #define DIGIT_EN_MASK           (0x1 << 1)
  55
  56 #define FRAMEDONE_IRQ_SHIFT     0
  57 #define EVSYNC_EVEN_IRQ_SHIFT   2
  58 #define EVSYNC_ODD_IRQ_SHIFT    3
  59 #define FRAMEDONE2_IRQ_SHIFT    22
  60 #define FRAMEDONE3_IRQ_SHIFT    30
  61 #define FRAMEDONETV_IRQ_SHIFT   24
  62
  63 /*
  64  * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
  65  *     reset before deciding that something has gone wrong
  66  */
  67 #define FRAMEDONE_IRQ_TIMEOUT           100
  68
  69 #if defined(CONFIG_FB_OMAP2)
  70 static struct platform_device omap_display_device = {
  71         .name          = "omapdss",
  72         .id            = -1,
  73         .dev            = {
  74                 .platform_data = NULL,
  75         },
  76 };
  77
  78 #define OMAP4_DSIPHY_SYSCON_OFFSET              0x78
  79
  80 static struct regmap *omap4_dsi_mux_syscon;
  81
  82 static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
  83 {
  84         u32 enable_mask, enable_shift;
  85         u32 pipd_mask, pipd_shift;
  86         u32 reg;
  87         int ret;
  88
  89         if (dsi_id == 0) {
  90                 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
  91                 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
  92                 pipd_mask = OMAP4_DSI1_PIPD_MASK;
  93                 pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
  94         } else if (dsi_id == 1) {
  95                 enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
  96                 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
  97                 pipd_mask = OMAP4_DSI2_PIPD_MASK;
  98                 pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
  99         } else {
 100                 return -ENODEV;
 101         }
 102
 103         ret = regmap_read(omap4_dsi_mux_syscon,
 104                                           OMAP4_DSIPHY_SYSCON_OFFSET,
 105                                           &reg);
 106         if (ret)
 107                 return ret;
 108
 109         reg &= ~enable_mask;
 110         reg &= ~pipd_mask;
 111
 112         reg |= (lanes << enable_shift) & enable_mask;
 113         reg |= (lanes << pipd_shift) & pipd_mask;
 114
 115         regmap_write(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, reg);
 116
 117         return 0;
 118 }
 119
 120 static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
 121 {
 122         if (cpu_is_omap44xx())
 123                 return omap4_dsi_mux_pads(dsi_id, lane_mask);
 124
 125         return 0;
 126 }
 127
 128 static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
 129 {
 130         if (cpu_is_omap44xx())
 131                 omap4_dsi_mux_pads(dsi_id, 0);
 132 }
 133
 134 static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
 135 {
 136         return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
 137 }
 138
 139 static enum omapdss_version __init omap_display_get_version(void)
 140 {
 141         if (cpu_is_omap24xx())
 142                 return OMAPDSS_VER_OMAP24xx;
 143         else if (cpu_is_omap3630())
 144                 return OMAPDSS_VER_OMAP3630;
 145         else if (cpu_is_omap34xx()) {
 146                 if (soc_is_am35xx()) {
 147                         return OMAPDSS_VER_AM35xx;
 148                 } else {
 149                         if (omap_rev() < OMAP3430_REV_ES3_0)
 150                                 return OMAPDSS_VER_OMAP34xx_ES1;
 151                         else
 152                                 return OMAPDSS_VER_OMAP34xx_ES3;
 153                 }
 154         } else if (omap_rev() == OMAP4430_REV_ES1_0)
 155                 return OMAPDSS_VER_OMAP4430_ES1;
 156         else if (omap_rev() == OMAP4430_REV_ES2_0 ||
 157                         omap_rev() == OMAP4430_REV_ES2_1 ||
 158                         omap_rev() == OMAP4430_REV_ES2_2)
 159                 return OMAPDSS_VER_OMAP4430_ES2;
 160         else if (cpu_is_omap44xx())
 161                 return OMAPDSS_VER_OMAP4;
 162         else if (soc_is_omap54xx())
 163                 return OMAPDSS_VER_OMAP5;
 164         else if (soc_is_am43xx())
 165                 return OMAPDSS_VER_AM43xx;
 166         else if (soc_is_dra7xx())
 167                 return OMAPDSS_VER_DRA7xx;
 168         else
 169                 return OMAPDSS_VER_UNKNOWN;
 170 }
 171
 172 static int __init omapdss_init_fbdev(void)
 173 {
 174         static struct omap_dss_board_info board_data = {
 175                 .dsi_enable_pads = omap_dsi_enable_pads,
 176                 .dsi_disable_pads = omap_dsi_disable_pads,
 177                 .set_min_bus_tput = omap_dss_set_min_bus_tput,
 178         };
 179         struct device_node *node;
 180         int r;
 181
 182         board_data.version = omap_display_get_version();
 183         if (board_data.version == OMAPDSS_VER_UNKNOWN) {
 184                 pr_err("DSS not supported on this SoC\n");
 185                 return -ENODEV;
 186         }
 187
 188         omap_display_device.dev.platform_data = &board_data;
 189
 190         r = platform_device_register(&omap_display_device);
 191         if (r < 0) {
 192                 pr_err("Unable to register omapdss device\n");
 193                 return r;
 194         }
 195
 196         /* create vrfb device */
 197         r = omap_init_vrfb();
 198         if (r < 0) {
 199                 pr_err("Unable to register omapvrfb device\n");
 200                 return r;
 201         }
 202
 203         /* create FB device */
 204         r = omap_init_fb();
 205         if (r < 0) {
 206                 pr_err("Unable to register omapfb device\n");
 207                 return r;
 208         }
 209
 210         /* create V4L2 display device */
 211         r = omap_init_vout();
 212         if (r < 0) {
 213                 pr_err("Unable to register omap_vout device\n");
 214                 return r;
 215         }
 216
 217         /* add DSI info for omap4 */
 218         node = of_find_node_by_name(NULL, "omap4_padconf_global");
 219         if (node)
 220                 omap4_dsi_mux_syscon = syscon_node_to_regmap(node);
 221
 222         return 0;
 223 }
 224 #else
 225 static inline int omapdss_init_fbdev(void)
 226 {
 227         return 0;
 228 }
 229 #endif /* CONFIG_FB_OMAP2 */
 230
 231 static void dispc_disable_outputs(void)
 232 {
 233         u32 v, irq_mask = 0;
 234         bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
 235         int i;
 236         struct omap_dss_dispc_dev_attr *da;
 237         struct omap_hwmod *oh;
 238
 239         oh = omap_hwmod_lookup("dss_dispc");
 240         if (!oh) {
 241                 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
 242                 return;
 243         }
 244
 245         if (!oh->dev_attr) {
 246                 pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
 247                 return;
 248         }
 249
 250         da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
 251
 252         /* store value of LCDENABLE and DIGITENABLE bits */
 253         v = omap_hwmod_read(oh, DISPC_CONTROL);
 254         lcd_en = v & LCD_EN_MASK;
 255         digit_en = v & DIGIT_EN_MASK;
 256
 257         /* store value of LCDENABLE for LCD2 */
 258         if (da->manager_count > 2) {
 259                 v = omap_hwmod_read(oh, DISPC_CONTROL2);
 260                 lcd2_en = v & LCD_EN_MASK;
 261         }
 262
 263         /* store value of LCDENABLE for LCD3 */
 264         if (da->manager_count > 3) {
 265                 v = omap_hwmod_read(oh, DISPC_CONTROL3);
 266                 lcd3_en = v & LCD_EN_MASK;
 267         }
 268
 269         if (!(lcd_en | digit_en | lcd2_en | lcd3_en))
 270                 return; /* no managers currently enabled */
 271
 272         /*
 273          * If any manager was enabled, we need to disable it before
 274          * DSS clocks are disabled or DISPC module is reset
 275          */
 276         if (lcd_en)
 277                 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
 278
 279         if (digit_en) {
 280                 if (da->has_framedonetv_irq) {
 281                         irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
 282                 } else {
 283                         irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
 284                                 1 << EVSYNC_ODD_IRQ_SHIFT;
 285                 }
 286         }
 287
 288         if (lcd2_en)
 289                 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
 290         if (lcd3_en)
 291                 irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT;
 292
 293         /*
 294          * clear any previous FRAMEDONE, FRAMEDONETV,
 295          * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
 296          */
 297         omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
 298
 299         /* disable LCD and TV managers */
 300         v = omap_hwmod_read(oh, DISPC_CONTROL);
 301         v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
 302         omap_hwmod_write(v, oh, DISPC_CONTROL);
 303
 304         /* disable LCD2 manager */
 305         if (da->manager_count > 2) {
 306                 v = omap_hwmod_read(oh, DISPC_CONTROL2);
 307                 v &= ~LCD_EN_MASK;
 308                 omap_hwmod_write(v, oh, DISPC_CONTROL2);
 309         }
 310
 311         /* disable LCD3 manager */
 312         if (da->manager_count > 3) {
 313                 v = omap_hwmod_read(oh, DISPC_CONTROL3);
 314                 v &= ~LCD_EN_MASK;
 315                 omap_hwmod_write(v, oh, DISPC_CONTROL3);
 316         }
 317
 318         i = 0;
 319         while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
 320                irq_mask) {
 321                 i++;
 322                 if (i > FRAMEDONE_IRQ_TIMEOUT) {
 323                         pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
 324                         break;
 325                 }
 326                 mdelay(1);
 327         }
 328 }
 329
 330 int omap_dss_reset(struct omap_hwmod *oh)
 331 {
 332         struct omap_hwmod_opt_clk *oc;
 333         int c = 0;
 334         int i, r;
 335
 336         if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
 337                 pr_err("dss_core: hwmod data doesn't contain reset data\n");
 338                 return -EINVAL;
 339         }
 340
 341         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
 342                 if (oc->_clk)
 343                         clk_prepare_enable(oc->_clk);
 344
 345         dispc_disable_outputs();
 346
 347         /* clear SDI registers */
 348         if (cpu_is_omap3430()) {
 349                 omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
 350                 omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
 351         }
 352
 353         /*
 354          * clear DSS_CONTROL register to switch DSS clock sources to
 355          * PRCM clock, if any
 356          */
 357         omap_hwmod_write(0x0, oh, DSS_CONTROL);
 358
 359         omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
 360                                 & SYSS_RESETDONE_MASK),
 361                         MAX_MODULE_SOFTRESET_WAIT, c);
 362
 363         if (c == MAX_MODULE_SOFTRESET_WAIT)
 364                 pr_warn("dss_core: waiting for reset to finish failed\n");
 365         else
 366                 pr_debug("dss_core: softreset done\n");
 367
 368         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
 369                 if (oc->_clk)
 370                         clk_disable_unprepare(oc->_clk);
 371
 372         r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
 373
 374         return r;
 375 }
 376
 377 static const char * const omapdss_compat_names[] __initconst = {
 378         "ti,omap2-dss",
 379         "ti,omap3-dss",
 380         "ti,omap4-dss",
 381         "ti,omap5-dss",
 382         "ti,dra7-dss",
 383 };
 384
 385 static struct device_node * __init omapdss_find_dss_of_node(void)
 386 {
 387         struct device_node *node;
 388         int i;
 389
 390         for (i = 0; i < ARRAY_SIZE(omapdss_compat_names); ++i) {
 391                 node = of_find_compatible_node(NULL, NULL,
 392                         omapdss_compat_names[i]);
 393                 if (node)
 394                         return node;
 395         }
 396
 397         return NULL;
 398 }
 399
 400 int __init omapdss_init_of(void)
 401 {
 402         int r;
 403         struct device_node *node;
 404         struct platform_device *pdev;
 405
 406         /* only create dss helper devices if dss is enabled in the .dts */
 407
 408         node = omapdss_find_dss_of_node();
 409         if (!node)
 410                 return 0;
 411
 412         if (!of_device_is_available(node))
 413                 return 0;
 414
 415         pdev = of_find_device_by_node(node);
 416
 417         if (!pdev) {
 418                 pr_err("Unable to find DSS platform device\n");
 419                 return -ENODEV;
 420         }
 421
 422         r = of_platform_populate(node, NULL, NULL, &pdev->dev);
 423         if (r) {
 424                 pr_err("Unable to populate DSS submodule devices\n");
 425                 return r;
 426         }
 427
 428         return omapdss_init_fbdev();
 429 }