arch/arm/mach-omap2/omap4-common.c

   1 /*
   2  * OMAP4 specific common source file.
   3  *
   4  * Copyright (C) 2010 Texas Instruments, Inc.
   5  * Author:
   6  *      Santosh Shilimkar <santosh.shilimkar@ti.com>
   7  *
   8  *
   9  * This program is free software,you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/io.h>
  17 #include <linux/irq.h>
  18 #include <linux/irqchip.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/memblock.h>
  21 #include <linux/of_irq.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/export.h>
  24 #include <linux/irqchip/arm-gic.h>
  25 #include <linux/of_address.h>
  26 #include <linux/reboot.h>
  27 #include <linux/genalloc.h>
  28
  29 #include <asm/hardware/cache-l2x0.h>
  30 #include <asm/mach/map.h>
  31 #include <asm/memblock.h>
  32 #include <asm/smp_twd.h>
  33
  34 #include "omap-wakeupgen.h"
  35 #include "soc.h"
  36 #include "iomap.h"
  37 #include "common.h"
  38 #include "prminst44xx.h"
  39 #include "prcm_mpu44xx.h"
  40 #include "omap4-sar-layout.h"
  41 #include "omap-secure.h"
  42 #include "sram.h"
  43
  44 #ifdef CONFIG_CACHE_L2X0
  45 static void __iomem *l2cache_base;
  46 #endif
  47
  48 static void __iomem *sar_ram_base;
  49 static void __iomem *gic_dist_base_addr;
  50 static void __iomem *twd_base;
  51
  52 #define IRQ_LOCALTIMER          29
  53
  54 #ifdef CONFIG_OMAP_INTERCONNECT_BARRIER
  55
  56 /* Used to implement memory barrier on DRAM path */
  57 #define OMAP4_DRAM_BARRIER_VA                   0xfe600000
  58
  59 static void __iomem *dram_sync, *sram_sync;
  60 static phys_addr_t dram_sync_paddr;
  61 static u32 dram_sync_size;
  62
  63 /*
  64  * The OMAP4 bus structure contains asynchronous bridges which can buffer
  65  * data writes from the MPU. These asynchronous bridges can be found on
  66  * paths between the MPU to EMIF, and the MPU to L3 interconnects.
  67  *
  68  * We need to be careful about re-ordering which can happen as a result
  69  * of different accesses being performed via different paths, and
  70  * therefore different asynchronous bridges.
  71  */
  72
  73 /*
  74  * OMAP4 interconnect barrier which is called for each mb() and wmb().
  75  * This is to ensure that normal paths to DRAM (normal memory, cacheable
  76  * accesses) are properly synchronised with writes to DMA coherent memory
  77  * (normal memory, uncacheable) and device writes.
  78  *
  79  * The mb() and wmb() barriers only operate only on the MPU->MA->EMIF
  80  * path, as we need to ensure that data is visible to other system
  81  * masters prior to writes to those system masters being seen.
  82  *
  83  * Note: the SRAM path is not synchronised via mb() and wmb().
  84  */
  85 static void omap4_mb(void)
  86 {
  87         if (dram_sync)
  88                 writel_relaxed(0, dram_sync);
  89 }
  90
  91 /*
  92  * OMAP4 Errata i688 - asynchronous bridge corruption when entering WFI.
  93  *
  94  * If a data is stalled inside asynchronous bridge because of back
  95  * pressure, it may be accepted multiple times, creating pointer
  96  * misalignment that will corrupt next transfers on that data path until
  97  * next reset of the system. No recovery procedure once the issue is hit,
  98  * the path remains consistently broken.
  99  *
 100  * Async bridges can be found on paths between MPU to EMIF and MPU to L3
 101  * interconnects.
 102  *
 103  * This situation can happen only when the idle is initiated by a Master
 104  * Request Disconnection (which is trigged by software when executing WFI
 105  * on the CPU).
 106  *
 107  * The work-around for this errata needs all the initiators connected
 108  * through an async bridge to ensure that data path is properly drained
 109  * before issuing WFI. This condition will be met if one Strongly ordered
 110  * access is performed to the target right before executing the WFI.
 111  *
 112  * In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
 113  * IO barrier ensure that there is no synchronisation loss on initiators
 114  * operating on both interconnect port simultaneously.
 115  *
 116  * This is a stronger version of the OMAP4 memory barrier below, and
 117  * operates on both the MPU->MA->EMIF path but also the MPU->OCP path
 118  * as well, and is necessary prior to executing a WFI.
 119  */
 120 void omap_interconnect_sync(void)
 121 {
 122         if (dram_sync && sram_sync) {
 123                 writel_relaxed(readl_relaxed(dram_sync), dram_sync);
 124                 writel_relaxed(readl_relaxed(sram_sync), sram_sync);
 125                 isb();
 126         }
 127 }
 128
 129 static int __init omap4_sram_init(void)
 130 {
 131         struct device_node *np;
 132         struct gen_pool *sram_pool;
 133
 134         if (!soc_is_omap44xx() && !soc_is_omap54xx())
 135                 return 0;
 136
 137         np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
 138         if (!np)
 139                 pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
 140                         __func__);
 141         sram_pool = of_gen_pool_get(np, "sram", 0);
 142         if (!sram_pool)
 143                 pr_warn("%s:Unable to get sram pool needed to handle errata I688\n",
 144                         __func__);
 145         else
 146                 sram_sync = (void *)gen_pool_alloc(sram_pool, PAGE_SIZE);
 147
 148         return 0;
 149 }
 150 omap_arch_initcall(omap4_sram_init);
 151
 152 /* Steal one page physical memory for barrier implementation */
 153 void __init omap_barrier_reserve_memblock(void)
 154 {
 155         dram_sync_size = ALIGN(PAGE_SIZE, SZ_1M);
 156         dram_sync_paddr = arm_memblock_steal(dram_sync_size, SZ_1M);
 157 }
 158
 159 void __init omap_barriers_init(void)
 160 {
 161         struct map_desc dram_io_desc[1];
 162
 163         dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
 164         dram_io_desc[0].pfn = __phys_to_pfn(dram_sync_paddr);
 165         dram_io_desc[0].length = dram_sync_size;
 166         dram_io_desc[0].type = MT_MEMORY_RW_SO;
 167         iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
 168         dram_sync = (void __iomem *) dram_io_desc[0].virtual;
 169
 170         pr_info("OMAP4: Map %pa to %p for dram barrier\n",
 171                 &dram_sync_paddr, dram_sync);
 172
 173         soc_mb = omap4_mb;
 174 }
 175
 176 #endif
 177
 178 void gic_dist_disable(void)
 179 {
 180         if (gic_dist_base_addr)
 181                 writel_relaxed(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
 182 }
 183
 184 void gic_dist_enable(void)
 185 {
 186         if (gic_dist_base_addr)
 187                 writel_relaxed(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
 188 }
 189
 190 bool gic_dist_disabled(void)
 191 {
 192         return !(readl_relaxed(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
 193 }
 194
 195 void gic_timer_retrigger(void)
 196 {
 197         u32 twd_int = readl_relaxed(twd_base + TWD_TIMER_INTSTAT);
 198         u32 gic_int = readl_relaxed(gic_dist_base_addr + GIC_DIST_PENDING_SET);
 199         u32 twd_ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL);
 200
 201         if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
 202                 /*
 203                  * The local timer interrupt got lost while the distributor was
 204                  * disabled.  Ack the pending interrupt, and retrigger it.
 205                  */
 206                 pr_warn("%s: lost localtimer interrupt\n", __func__);
 207                 writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT);
 208                 if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
 209                         writel_relaxed(1, twd_base + TWD_TIMER_COUNTER);
 210                         twd_ctrl |= TWD_TIMER_CONTROL_ENABLE;
 211                         writel_relaxed(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
 212                 }
 213         }
 214 }
 215
 216 #ifdef CONFIG_CACHE_L2X0
 217
 218 void __iomem *omap4_get_l2cache_base(void)
 219 {
 220         return l2cache_base;
 221 }
 222
 223 void omap4_l2c310_write_sec(unsigned long val, unsigned reg)
 224 {
 225         unsigned smc_op;
 226
 227         switch (reg) {
 228         case L2X0_CTRL:
 229                 smc_op = OMAP4_MON_L2X0_CTRL_INDEX;
 230                 break;
 231
 232         case L2X0_AUX_CTRL:
 233                 smc_op = OMAP4_MON_L2X0_AUXCTRL_INDEX;
 234                 break;
 235
 236         case L2X0_DEBUG_CTRL:
 237                 smc_op = OMAP4_MON_L2X0_DBG_CTRL_INDEX;
 238                 break;
 239
 240         case L310_PREFETCH_CTRL:
 241                 smc_op = OMAP4_MON_L2X0_PREFETCH_INDEX;
 242                 break;
 243
 244         case L310_POWER_CTRL:
 245                 pr_info_once("OMAP L2C310: ROM does not support power control setting\n");
 246                 return;
 247
 248         default:
 249                 WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg);
 250                 return;
 251         }
 252
 253         omap_smc1(smc_op, val);
 254 }
 255
 256 int __init omap_l2_cache_init(void)
 257 {
 258         /* Static mapping, never released */
 259         l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
 260         if (WARN_ON(!l2cache_base))
 261                 return -ENOMEM;
 262         return 0;
 263 }
 264 #endif
 265
 266 void __iomem *omap4_get_sar_ram_base(void)
 267 {
 268         return sar_ram_base;
 269 }
 270
 271 /*
 272  * SAR RAM used to save and restore the HW context in low power modes.
 273  * Note that we need to initialize this very early for kexec. See
 274  * omap4_mpuss_early_init().
 275  */
 276 void __init omap4_sar_ram_init(void)
 277 {
 278         unsigned long sar_base;
 279
 280         /*
 281          * To avoid code running on other OMAPs in
 282          * multi-omap builds
 283          */
 284         if (cpu_is_omap44xx())
 285                 sar_base = OMAP44XX_SAR_RAM_BASE;
 286         else if (soc_is_omap54xx())
 287                 sar_base = OMAP54XX_SAR_RAM_BASE;
 288         else
 289                 return;
 290
 291         /* Static mapping, never released */
 292         sar_ram_base = ioremap(sar_base, SZ_16K);
 293         if (WARN_ON(!sar_ram_base))
 294                 return;
 295 }
 296
 297 static const struct of_device_id intc_match[] = {
 298         { .compatible = "ti,omap4-wugen-mpu", },
 299         { .compatible = "ti,omap5-wugen-mpu", },
 300         { },
 301 };
 302
 303 static struct device_node *intc_node;
 304
 305 unsigned int omap4_xlate_irq(unsigned int hwirq)
 306 {
 307         struct of_phandle_args irq_data;
 308         unsigned int irq;
 309
 310         if (!intc_node)
 311                 intc_node = of_find_matching_node(NULL, intc_match);
 312
 313         if (WARN_ON(!intc_node))
 314                 return hwirq;
 315
 316         irq_data.np = intc_node;
 317         irq_data.args_count = 3;
 318         irq_data.args[0] = 0;
 319         irq_data.args[1] = hwirq - OMAP44XX_IRQ_GIC_START;
 320         irq_data.args[2] = IRQ_TYPE_LEVEL_HIGH;
 321
 322         irq = irq_create_of_mapping(&irq_data);
 323         if (WARN_ON(!irq))
 324                 irq = hwirq;
 325
 326         return irq;
 327 }
 328
 329 void __init omap_gic_of_init(void)
 330 {
 331         struct device_node *np;
 332
 333         intc_node = of_find_matching_node(NULL, intc_match);
 334         if (WARN_ON(!intc_node)) {
 335                 pr_err("No WUGEN found in DT, system will misbehave.\n");
 336                 pr_err("UPDATE YOUR DEVICE TREE!\n");
 337         }
 338
 339         /* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
 340         if (!cpu_is_omap446x())
 341                 goto skip_errata_init;
 342
 343         np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
 344         gic_dist_base_addr = of_iomap(np, 0);
 345         WARN_ON(!gic_dist_base_addr);
 346
 347         np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
 348         twd_base = of_iomap(np, 0);
 349         WARN_ON(!twd_base);
 350
 351 skip_errata_init:
 352         irqchip_init();
 353 }