arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c

   1 /*
   2  * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
   3  *
   4  * Copyright (C) 2011 Nokia Corporation
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/dmaengine.h>
  14 #include <linux/omap-dma.h>
  15
  16 #include "omap_hwmod.h"
  17 #include "hdq1w.h"
  18
  19 #include "omap_hwmod_common_data.h"
  20
  21 /* UART */
  22
  23 static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
  24         .rev_offs       = 0x50,
  25         .sysc_offs      = 0x54,
  26         .syss_offs      = 0x58,
  27         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
  28                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  29                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  30         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  31         .sysc_fields    = &omap_hwmod_sysc_type1,
  32 };
  33
  34 struct omap_hwmod_class omap2_uart_class = {
  35         .name   = "uart",
  36         .sysc   = &omap2_uart_sysc,
  37 };
  38
  39 /*
  40  * 'venc' class
  41  * video encoder
  42  */
  43
  44 struct omap_hwmod_class omap2_venc_hwmod_class = {
  45         .name = "venc",
  46 };
  47
  48 /*
  49  * omap_hwmod class data
  50  */
  51
  52 struct omap_hwmod_class l3_hwmod_class = {
  53         .name = "l3",
  54 };
  55
  56 struct omap_hwmod_class l4_hwmod_class = {
  57         .name = "l4",
  58 };
  59
  60 struct omap_hwmod_class mpu_hwmod_class = {
  61         .name = "mpu",
  62 };
  63
  64 struct omap_hwmod_class iva_hwmod_class = {
  65         .name = "iva",
  66 };
  67
  68 /* Common MPU IRQ line data */
  69
  70 struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
  71         { .irq = 25 + OMAP_INTC_START, },
  72         { .irq = -1, },
  73 };
  74
  75 struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
  76         { .name = "0", .irq = 12 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ0 */
  77         { .name = "1", .irq = 13 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ1 */
  78         { .name = "2", .irq = 14 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ2 */
  79         { .name = "3", .irq = 15 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ3 */
  80         { .irq = -1, },
  81 };
  82
  83 struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = {
  84         .rev_offs       = 0x0,
  85         .sysc_offs      = 0x14,
  86         .syss_offs      = 0x18,
  87         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
  88                            SYSS_HAS_RESET_STATUS),
  89         .sysc_fields    = &omap_hwmod_sysc_type1,
  90 };
  91
  92 struct omap_hwmod_class omap2_hdq1w_class = {
  93         .name   = "hdq1w",
  94         .sysc   = &omap2_hdq1w_sysc,
  95         .reset  = &omap_hdq1w_reset,
  96 };