mm: fix exec activate_mm vs TLB shootdown and lazy tlb switching race
[linux/fpc-iii.git] / arch / arm / mach-omap2 / omap_hwmod_2xxx_interconnect_data.c
blob9b30b6b471ae3bb274aa32be7cc625af96ca80dd
1 /*
2 * omap_hwmod_2xxx_interconnect_data.c - common interconnect data for OMAP2xxx
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Paul Walmsley
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * XXX handle crossbar/shared link difference for L3?
12 * XXX these should be marked initdata for multi-OMAP kernels
14 #include <asm/sizes.h>
16 #include "omap_hwmod.h"
17 #include "l3_2xxx.h"
18 #include "l4_2xxx.h"
19 #include "serial.h"
21 #include "omap_hwmod_common_data.h"
24 * Common interconnect data
27 /* L3 -> L4_CORE interface */
28 struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core = {
29 .master = &omap2xxx_l3_main_hwmod,
30 .slave = &omap2xxx_l4_core_hwmod,
31 .user = OCP_USER_MPU | OCP_USER_SDMA,
34 /* MPU -> L3 interface */
35 struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main = {
36 .master = &omap2xxx_mpu_hwmod,
37 .slave = &omap2xxx_l3_main_hwmod,
38 .user = OCP_USER_MPU,
41 /* DSS -> l3 */
42 struct omap_hwmod_ocp_if omap2xxx_dss__l3 = {
43 .master = &omap2xxx_dss_core_hwmod,
44 .slave = &omap2xxx_l3_main_hwmod,
45 .fw = {
46 .omap2 = {
47 .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
48 .flags = OMAP_FIREWALL_L3,
51 .user = OCP_USER_MPU | OCP_USER_SDMA,
54 /* L4_CORE -> L4_WKUP interface */
55 struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup = {
56 .master = &omap2xxx_l4_core_hwmod,
57 .slave = &omap2xxx_l4_wkup_hwmod,
58 .user = OCP_USER_MPU | OCP_USER_SDMA,
61 /* L4 CORE -> UART1 interface */
62 struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
63 .master = &omap2xxx_l4_core_hwmod,
64 .slave = &omap2xxx_uart1_hwmod,
65 .clk = "uart1_ick",
66 .user = OCP_USER_MPU | OCP_USER_SDMA,
69 /* L4 CORE -> UART2 interface */
70 struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
71 .master = &omap2xxx_l4_core_hwmod,
72 .slave = &omap2xxx_uart2_hwmod,
73 .clk = "uart2_ick",
74 .user = OCP_USER_MPU | OCP_USER_SDMA,
77 /* L4 PER -> UART3 interface */
78 struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
79 .master = &omap2xxx_l4_core_hwmod,
80 .slave = &omap2xxx_uart3_hwmod,
81 .clk = "uart3_ick",
82 .user = OCP_USER_MPU | OCP_USER_SDMA,
85 /* l4 core -> mcspi1 interface */
86 struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = {
87 .master = &omap2xxx_l4_core_hwmod,
88 .slave = &omap2xxx_mcspi1_hwmod,
89 .clk = "mcspi1_ick",
90 .user = OCP_USER_MPU | OCP_USER_SDMA,
93 /* l4 core -> mcspi2 interface */
94 struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = {
95 .master = &omap2xxx_l4_core_hwmod,
96 .slave = &omap2xxx_mcspi2_hwmod,
97 .clk = "mcspi2_ick",
98 .user = OCP_USER_MPU | OCP_USER_SDMA,
101 /* l4_core -> timer2 */
102 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = {
103 .master = &omap2xxx_l4_core_hwmod,
104 .slave = &omap2xxx_timer2_hwmod,
105 .clk = "gpt2_ick",
106 .user = OCP_USER_MPU | OCP_USER_SDMA,
109 /* l4_core -> timer3 */
110 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
111 .master = &omap2xxx_l4_core_hwmod,
112 .slave = &omap2xxx_timer3_hwmod,
113 .clk = "gpt3_ick",
114 .user = OCP_USER_MPU | OCP_USER_SDMA,
117 /* l4_core -> timer4 */
118 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = {
119 .master = &omap2xxx_l4_core_hwmod,
120 .slave = &omap2xxx_timer4_hwmod,
121 .clk = "gpt4_ick",
122 .user = OCP_USER_MPU | OCP_USER_SDMA,
125 /* l4_core -> timer5 */
126 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = {
127 .master = &omap2xxx_l4_core_hwmod,
128 .slave = &omap2xxx_timer5_hwmod,
129 .clk = "gpt5_ick",
130 .user = OCP_USER_MPU | OCP_USER_SDMA,
133 /* l4_core -> timer6 */
134 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = {
135 .master = &omap2xxx_l4_core_hwmod,
136 .slave = &omap2xxx_timer6_hwmod,
137 .clk = "gpt6_ick",
138 .user = OCP_USER_MPU | OCP_USER_SDMA,
141 /* l4_core -> timer7 */
142 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = {
143 .master = &omap2xxx_l4_core_hwmod,
144 .slave = &omap2xxx_timer7_hwmod,
145 .clk = "gpt7_ick",
146 .user = OCP_USER_MPU | OCP_USER_SDMA,
149 /* l4_core -> timer8 */
150 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = {
151 .master = &omap2xxx_l4_core_hwmod,
152 .slave = &omap2xxx_timer8_hwmod,
153 .clk = "gpt8_ick",
154 .user = OCP_USER_MPU | OCP_USER_SDMA,
157 /* l4_core -> timer9 */
158 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = {
159 .master = &omap2xxx_l4_core_hwmod,
160 .slave = &omap2xxx_timer9_hwmod,
161 .clk = "gpt9_ick",
162 .user = OCP_USER_MPU | OCP_USER_SDMA,
165 /* l4_core -> timer10 */
166 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = {
167 .master = &omap2xxx_l4_core_hwmod,
168 .slave = &omap2xxx_timer10_hwmod,
169 .clk = "gpt10_ick",
170 .user = OCP_USER_MPU | OCP_USER_SDMA,
173 /* l4_core -> timer11 */
174 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = {
175 .master = &omap2xxx_l4_core_hwmod,
176 .slave = &omap2xxx_timer11_hwmod,
177 .clk = "gpt11_ick",
178 .user = OCP_USER_MPU | OCP_USER_SDMA,
181 /* l4_core -> timer12 */
182 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = {
183 .master = &omap2xxx_l4_core_hwmod,
184 .slave = &omap2xxx_timer12_hwmod,
185 .clk = "gpt12_ick",
186 .user = OCP_USER_MPU | OCP_USER_SDMA,
189 /* l4_core -> dss */
190 struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
191 .master = &omap2xxx_l4_core_hwmod,
192 .slave = &omap2xxx_dss_core_hwmod,
193 .clk = "dss_ick",
194 .fw = {
195 .omap2 = {
196 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
197 .flags = OMAP_FIREWALL_L4,
200 .user = OCP_USER_MPU | OCP_USER_SDMA,
203 /* l4_core -> dss_dispc */
204 struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
205 .master = &omap2xxx_l4_core_hwmod,
206 .slave = &omap2xxx_dss_dispc_hwmod,
207 .clk = "dss_ick",
208 .fw = {
209 .omap2 = {
210 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
211 .flags = OMAP_FIREWALL_L4,
214 .user = OCP_USER_MPU | OCP_USER_SDMA,
217 /* l4_core -> dss_rfbi */
218 struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
219 .master = &omap2xxx_l4_core_hwmod,
220 .slave = &omap2xxx_dss_rfbi_hwmod,
221 .clk = "dss_ick",
222 .fw = {
223 .omap2 = {
224 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
225 .flags = OMAP_FIREWALL_L4,
228 .user = OCP_USER_MPU | OCP_USER_SDMA,
231 /* l4_core -> dss_venc */
232 struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
233 .master = &omap2xxx_l4_core_hwmod,
234 .slave = &omap2xxx_dss_venc_hwmod,
235 .clk = "dss_ick",
236 .fw = {
237 .omap2 = {
238 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
239 .flags = OMAP_FIREWALL_L4,
242 .flags = OCPIF_SWSUP_IDLE,
243 .user = OCP_USER_MPU | OCP_USER_SDMA,
246 /* l4_core -> rng */
247 struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = {
248 .master = &omap2xxx_l4_core_hwmod,
249 .slave = &omap2xxx_rng_hwmod,
250 .clk = "rng_ick",
251 .user = OCP_USER_MPU | OCP_USER_SDMA,
254 /* l4 core -> sham interface */
255 struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = {
256 .master = &omap2xxx_l4_core_hwmod,
257 .slave = &omap2xxx_sham_hwmod,
258 .clk = "sha_ick",
259 .user = OCP_USER_MPU | OCP_USER_SDMA,
262 /* l4 core -> aes interface */
263 struct omap_hwmod_ocp_if omap2xxx_l4_core__aes = {
264 .master = &omap2xxx_l4_core_hwmod,
265 .slave = &omap2xxx_aes_hwmod,
266 .clk = "aes_ick",
267 .user = OCP_USER_MPU | OCP_USER_SDMA,