arch/arm/mach-omap2/omap_hwmod_33xx_data.c

   1 /*
   2  * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
   3  *
   4  * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This file is automatically generated from the AM33XX hardware databases.
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/i2c-omap.h>
  18
  19 #include "omap_hwmod.h"
  20 #include <linux/platform_data/gpio-omap.h>
  21 #include <linux/platform_data/spi-omap2-mcspi.h>
  22
  23 #include "omap_hwmod_common_data.h"
  24
  25 #include "control.h"
  26 #include "cm33xx.h"
  27 #include "prm33xx.h"
  28 #include "prm-regbits-33xx.h"
  29 #include "i2c.h"
  30 #include "wd_timer.h"
  31 #include "omap_hwmod_33xx_43xx_common_data.h"
  32
  33 /*
  34  * IP blocks
  35  */
  36
  37 /* emif */
  38 static struct omap_hwmod am33xx_emif_hwmod = {
  39         .name           = "emif",
  40         .class          = &am33xx_emif_hwmod_class,
  41         .clkdm_name     = "l3_clkdm",
  42         .flags          = HWMOD_INIT_NO_IDLE,
  43         .main_clk       = "dpll_ddr_m2_div2_ck",
  44         .prcm           = {
  45                 .omap4  = {
  46                         .clkctrl_offs   = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
  47                         .modulemode     = MODULEMODE_SWCTRL,
  48                 },
  49         },
  50 };
  51
  52 /* l4_hs */
  53 static struct omap_hwmod am33xx_l4_hs_hwmod = {
  54         .name           = "l4_hs",
  55         .class          = &am33xx_l4_hwmod_class,
  56         .clkdm_name     = "l4hs_clkdm",
  57         .flags          = HWMOD_INIT_NO_IDLE,
  58         .main_clk       = "l4hs_gclk",
  59         .prcm           = {
  60                 .omap4  = {
  61                         .clkctrl_offs   = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
  62                         .modulemode     = MODULEMODE_SWCTRL,
  63                 },
  64         },
  65 };
  66
  67 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
  68         { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
  69 };
  70
  71 /* wkup_m3  */
  72 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
  73         .name           = "wkup_m3",
  74         .class          = &am33xx_wkup_m3_hwmod_class,
  75         .clkdm_name     = "l4_wkup_aon_clkdm",
  76         /* Keep hardreset asserted */
  77         .flags          = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
  78         .main_clk       = "dpll_core_m4_div2_ck",
  79         .prcm           = {
  80                 .omap4  = {
  81                         .clkctrl_offs   = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
  82                         .rstctrl_offs   = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
  83                         .rstst_offs     = AM33XX_RM_WKUP_RSTST_OFFSET,
  84                         .modulemode     = MODULEMODE_SWCTRL,
  85                 },
  86         },
  87         .rst_lines      = am33xx_wkup_m3_resets,
  88         .rst_lines_cnt  = ARRAY_SIZE(am33xx_wkup_m3_resets),
  89 };
  90
  91 /*
  92  * 'adc/tsc' class
  93  * TouchScreen Controller (Anolog-To-Digital Converter)
  94  */
  95 static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
  96         .rev_offs       = 0x00,
  97         .sysc_offs      = 0x10,
  98         .sysc_flags     = SYSC_HAS_SIDLEMODE,
  99         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 100                         SIDLE_SMART_WKUP),
 101         .sysc_fields    = &omap_hwmod_sysc_type2,
 102 };
 103
 104 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
 105         .name           = "adc_tsc",
 106         .sysc           = &am33xx_adc_tsc_sysc,
 107 };
 108
 109 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
 110         .name           = "adc_tsc",
 111         .class          = &am33xx_adc_tsc_hwmod_class,
 112         .clkdm_name     = "l4_wkup_clkdm",
 113         .main_clk       = "adc_tsc_fck",
 114         .prcm           = {
 115                 .omap4  = {
 116                         .clkctrl_offs   = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
 117                         .modulemode     = MODULEMODE_SWCTRL,
 118                 },
 119         },
 120 };
 121
 122 /*
 123  * Modules omap_hwmod structures
 124  *
 125  * The following IPs are excluded for the moment because:
 126  * - They do not need an explicit SW control using omap_hwmod API.
 127  * - They still need to be validated with the driver
 128  *   properly adapted to omap_hwmod / omap_device
 129  *
 130  *    - cEFUSE (doesn't fall under any ocp_if)
 131  *    - clkdiv32k
 132  *    - ocp watch point
 133  */
 134 #if 0
 135 /*
 136  * 'cefuse' class
 137  */
 138 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
 139         .name           = "cefuse",
 140 };
 141
 142 static struct omap_hwmod am33xx_cefuse_hwmod = {
 143         .name           = "cefuse",
 144         .class          = &am33xx_cefuse_hwmod_class,
 145         .clkdm_name     = "l4_cefuse_clkdm",
 146         .main_clk       = "cefuse_fck",
 147         .prcm           = {
 148                 .omap4  = {
 149                         .clkctrl_offs   = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
 150                         .modulemode     = MODULEMODE_SWCTRL,
 151                 },
 152         },
 153 };
 154
 155 /*
 156  * 'clkdiv32k' class
 157  */
 158 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
 159         .name           = "clkdiv32k",
 160 };
 161
 162 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
 163         .name           = "clkdiv32k",
 164         .class          = &am33xx_clkdiv32k_hwmod_class,
 165         .clkdm_name     = "clk_24mhz_clkdm",
 166         .main_clk       = "clkdiv32k_ick",
 167         .prcm           = {
 168                 .omap4  = {
 169                         .clkctrl_offs   = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
 170                         .modulemode     = MODULEMODE_SWCTRL,
 171                 },
 172         },
 173 };
 174
 175 /* ocpwp */
 176 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
 177         .name           = "ocpwp",
 178 };
 179
 180 static struct omap_hwmod am33xx_ocpwp_hwmod = {
 181         .name           = "ocpwp",
 182         .class          = &am33xx_ocpwp_hwmod_class,
 183         .clkdm_name     = "l4ls_clkdm",
 184         .main_clk       = "l4ls_gclk",
 185         .prcm           = {
 186                 .omap4  = {
 187                         .clkctrl_offs   = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
 188                         .modulemode     = MODULEMODE_SWCTRL,
 189                 },
 190         },
 191 };
 192 #endif
 193
 194 /*
 195  * 'debugss' class
 196  * debug sub system
 197  */
 198 static struct omap_hwmod_opt_clk debugss_opt_clks[] = {
 199         { .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" },
 200         { .role = "dbg_clka", .clk = "dbg_clka_ck" },
 201 };
 202
 203 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
 204         .name           = "debugss",
 205 };
 206
 207 static struct omap_hwmod am33xx_debugss_hwmod = {
 208         .name           = "debugss",
 209         .class          = &am33xx_debugss_hwmod_class,
 210         .clkdm_name     = "l3_aon_clkdm",
 211         .main_clk       = "trace_clk_div_ck",
 212         .prcm           = {
 213                 .omap4  = {
 214                         .clkctrl_offs   = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
 215                         .modulemode     = MODULEMODE_SWCTRL,
 216                 },
 217         },
 218         .opt_clks       = debugss_opt_clks,
 219         .opt_clks_cnt   = ARRAY_SIZE(debugss_opt_clks),
 220 };
 221
 222 static struct omap_hwmod am33xx_control_hwmod = {
 223         .name           = "control",
 224         .class          = &am33xx_control_hwmod_class,
 225         .clkdm_name     = "l4_wkup_clkdm",
 226         .flags          = HWMOD_INIT_NO_IDLE,
 227         .main_clk       = "dpll_core_m4_div2_ck",
 228         .prcm           = {
 229                 .omap4  = {
 230                         .clkctrl_offs   = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
 231                         .modulemode     = MODULEMODE_SWCTRL,
 232                 },
 233         },
 234 };
 235
 236 /* gpio0 */
 237 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
 238         { .role = "dbclk", .clk = "gpio0_dbclk" },
 239 };
 240
 241 static struct omap_hwmod am33xx_gpio0_hwmod = {
 242         .name           = "gpio1",
 243         .class          = &am33xx_gpio_hwmod_class,
 244         .clkdm_name     = "l4_wkup_clkdm",
 245         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 246         .main_clk       = "dpll_core_m4_div2_ck",
 247         .prcm           = {
 248                 .omap4  = {
 249                         .clkctrl_offs   = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
 250                         .modulemode     = MODULEMODE_SWCTRL,
 251                 },
 252         },
 253         .opt_clks       = gpio0_opt_clks,
 254         .opt_clks_cnt   = ARRAY_SIZE(gpio0_opt_clks),
 255         .dev_attr       = &gpio_dev_attr,
 256 };
 257
 258 /* lcdc */
 259 static struct omap_hwmod_class_sysconfig lcdc_sysc = {
 260         .rev_offs       = 0x0,
 261         .sysc_offs      = 0x54,
 262         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
 263         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 264         .sysc_fields    = &omap_hwmod_sysc_type2,
 265 };
 266
 267 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
 268         .name           = "lcdc",
 269         .sysc           = &lcdc_sysc,
 270 };
 271
 272 static struct omap_hwmod am33xx_lcdc_hwmod = {
 273         .name           = "lcdc",
 274         .class          = &am33xx_lcdc_hwmod_class,
 275         .clkdm_name     = "lcdc_clkdm",
 276         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 277         .main_clk       = "lcd_gclk",
 278         .prcm           = {
 279                 .omap4  = {
 280                         .clkctrl_offs   = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
 281                         .modulemode     = MODULEMODE_SWCTRL,
 282                 },
 283         },
 284 };
 285
 286 /*
 287  * 'usb_otg' class
 288  * high-speed on-the-go universal serial bus (usb_otg) controller
 289  */
 290 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
 291         .rev_offs       = 0x0,
 292         .sysc_offs      = 0x10,
 293         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
 294         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 295                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 296         .sysc_fields    = &omap_hwmod_sysc_type2,
 297 };
 298
 299 static struct omap_hwmod_class am33xx_usbotg_class = {
 300         .name           = "usbotg",
 301         .sysc           = &am33xx_usbhsotg_sysc,
 302 };
 303
 304 static struct omap_hwmod am33xx_usbss_hwmod = {
 305         .name           = "usb_otg_hs",
 306         .class          = &am33xx_usbotg_class,
 307         .clkdm_name     = "l3s_clkdm",
 308         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 309         .main_clk       = "usbotg_fck",
 310         .prcm           = {
 311                 .omap4  = {
 312                         .clkctrl_offs   = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
 313                         .modulemode     = MODULEMODE_SWCTRL,
 314                 },
 315         },
 316 };
 317
 318
 319 /*
 320  * Interfaces
 321  */
 322
 323 static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
 324         {
 325                 .pa_start       = 0x4c000000,
 326                 .pa_end         = 0x4c000fff,
 327                 .flags          = ADDR_TYPE_RT
 328         },
 329         { }
 330 };
 331 /* l3 main -> emif */
 332 static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
 333         .master         = &am33xx_l3_main_hwmod,
 334         .slave          = &am33xx_emif_hwmod,
 335         .clk            = "dpll_core_m4_ck",
 336         .addr           = am33xx_emif_addrs,
 337         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 338 };
 339
 340 /* l3 main -> l4 hs */
 341 static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
 342         .master         = &am33xx_l3_main_hwmod,
 343         .slave          = &am33xx_l4_hs_hwmod,
 344         .clk            = "l3s_gclk",
 345         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 346 };
 347
 348 /* wkup m3 -> l4 wkup */
 349 static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
 350         .master         = &am33xx_wkup_m3_hwmod,
 351         .slave          = &am33xx_l4_wkup_hwmod,
 352         .clk            = "dpll_core_m4_div2_ck",
 353         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 354 };
 355
 356 /* l4 wkup -> wkup m3 */
 357 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
 358         .master         = &am33xx_l4_wkup_hwmod,
 359         .slave          = &am33xx_wkup_m3_hwmod,
 360         .clk            = "dpll_core_m4_div2_ck",
 361         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 362 };
 363
 364 /* l4 hs -> pru-icss */
 365 static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
 366         .master         = &am33xx_l4_hs_hwmod,
 367         .slave          = &am33xx_pruss_hwmod,
 368         .clk            = "dpll_core_m4_ck",
 369         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 370 };
 371
 372 /* l3_main -> debugss */
 373 static struct omap_hwmod_addr_space am33xx_debugss_addrs[] = {
 374         {
 375                 .pa_start       = 0x4b000000,
 376                 .pa_end         = 0x4b000000 + SZ_16M - 1,
 377                 .flags          = ADDR_TYPE_RT
 378         },
 379         { }
 380 };
 381
 382 static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
 383         .master         = &am33xx_l3_main_hwmod,
 384         .slave          = &am33xx_debugss_hwmod,
 385         .clk            = "dpll_core_m4_ck",
 386         .addr           = am33xx_debugss_addrs,
 387         .user           = OCP_USER_MPU,
 388 };
 389
 390 /* l4 wkup -> smartreflex0 */
 391 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
 392         .master         = &am33xx_l4_wkup_hwmod,
 393         .slave          = &am33xx_smartreflex0_hwmod,
 394         .clk            = "dpll_core_m4_div2_ck",
 395         .user           = OCP_USER_MPU,
 396 };
 397
 398 /* l4 wkup -> smartreflex1 */
 399 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
 400         .master         = &am33xx_l4_wkup_hwmod,
 401         .slave          = &am33xx_smartreflex1_hwmod,
 402         .clk            = "dpll_core_m4_div2_ck",
 403         .user           = OCP_USER_MPU,
 404 };
 405
 406 /* l4 wkup -> control */
 407 static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
 408         .master         = &am33xx_l4_wkup_hwmod,
 409         .slave          = &am33xx_control_hwmod,
 410         .clk            = "dpll_core_m4_div2_ck",
 411         .user           = OCP_USER_MPU,
 412 };
 413
 414 /* L4 WKUP -> I2C1 */
 415 static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
 416         .master         = &am33xx_l4_wkup_hwmod,
 417         .slave          = &am33xx_i2c1_hwmod,
 418         .clk            = "dpll_core_m4_div2_ck",
 419         .user           = OCP_USER_MPU,
 420 };
 421
 422 /* L4 WKUP -> GPIO1 */
 423 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
 424         .master         = &am33xx_l4_wkup_hwmod,
 425         .slave          = &am33xx_gpio0_hwmod,
 426         .clk            = "dpll_core_m4_div2_ck",
 427         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 428 };
 429
 430 /* L4 WKUP -> ADC_TSC */
 431 static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
 432         {
 433                 .pa_start       = 0x44E0D000,
 434                 .pa_end         = 0x44E0D000 + SZ_8K - 1,
 435                 .flags          = ADDR_TYPE_RT
 436         },
 437         { }
 438 };
 439
 440 static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
 441         .master         = &am33xx_l4_wkup_hwmod,
 442         .slave          = &am33xx_adc_tsc_hwmod,
 443         .clk            = "dpll_core_m4_div2_ck",
 444         .addr           = am33xx_adc_tsc_addrs,
 445         .user           = OCP_USER_MPU,
 446 };
 447
 448 static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
 449         .master         = &am33xx_l4_hs_hwmod,
 450         .slave          = &am33xx_cpgmac0_hwmod,
 451         .clk            = "cpsw_125mhz_gclk",
 452         .user           = OCP_USER_MPU,
 453 };
 454
 455 static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
 456         {
 457                 .pa_start       = 0x4830E000,
 458                 .pa_end         = 0x4830E000 + SZ_8K - 1,
 459                 .flags          = ADDR_TYPE_RT,
 460         },
 461         { }
 462 };
 463
 464 static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
 465         .master         = &am33xx_l3_main_hwmod,
 466         .slave          = &am33xx_lcdc_hwmod,
 467         .clk            = "dpll_core_m4_ck",
 468         .addr           = am33xx_lcdc_addr_space,
 469         .user           = OCP_USER_MPU,
 470 };
 471
 472 /* l4 wkup -> timer1 */
 473 static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
 474         .master         = &am33xx_l4_wkup_hwmod,
 475         .slave          = &am33xx_timer1_hwmod,
 476         .clk            = "dpll_core_m4_div2_ck",
 477         .user           = OCP_USER_MPU,
 478 };
 479
 480 /* l4 wkup -> uart1 */
 481 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
 482         .master         = &am33xx_l4_wkup_hwmod,
 483         .slave          = &am33xx_uart1_hwmod,
 484         .clk            = "dpll_core_m4_div2_ck",
 485         .user           = OCP_USER_MPU,
 486 };
 487
 488 /* l4 wkup -> wd_timer1 */
 489 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
 490         .master         = &am33xx_l4_wkup_hwmod,
 491         .slave          = &am33xx_wd_timer1_hwmod,
 492         .clk            = "dpll_core_m4_div2_ck",
 493         .user           = OCP_USER_MPU,
 494 };
 495
 496 /* usbss */
 497 /* l3 s -> USBSS interface */
 498 static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
 499         .master         = &am33xx_l3_s_hwmod,
 500         .slave          = &am33xx_usbss_hwmod,
 501         .clk            = "l3s_gclk",
 502         .user           = OCP_USER_MPU,
 503         .flags          = OCPIF_SWSUP_IDLE,
 504 };
 505
 506 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
 507         &am33xx_l3_main__emif,
 508         &am33xx_mpu__l3_main,
 509         &am33xx_mpu__prcm,
 510         &am33xx_l3_s__l4_ls,
 511         &am33xx_l3_s__l4_wkup,
 512         &am33xx_l3_main__l4_hs,
 513         &am33xx_l3_main__l3_s,
 514         &am33xx_l3_main__l3_instr,
 515         &am33xx_l3_main__gfx,
 516         &am33xx_l3_s__l3_main,
 517         &am33xx_pruss__l3_main,
 518         &am33xx_wkup_m3__l4_wkup,
 519         &am33xx_gfx__l3_main,
 520         &am33xx_l3_main__debugss,
 521         &am33xx_l4_wkup__wkup_m3,
 522         &am33xx_l4_wkup__control,
 523         &am33xx_l4_wkup__smartreflex0,
 524         &am33xx_l4_wkup__smartreflex1,
 525         &am33xx_l4_wkup__uart1,
 526         &am33xx_l4_wkup__timer1,
 527         &am33xx_l4_wkup__rtc,
 528         &am33xx_l4_wkup__i2c1,
 529         &am33xx_l4_wkup__gpio0,
 530         &am33xx_l4_wkup__adc_tsc,
 531         &am33xx_l4_wkup__wd_timer1,
 532         &am33xx_l4_hs__pruss,
 533         &am33xx_l4_per__dcan0,
 534         &am33xx_l4_per__dcan1,
 535         &am33xx_l4_per__gpio1,
 536         &am33xx_l4_per__gpio2,
 537         &am33xx_l4_per__gpio3,
 538         &am33xx_l4_per__i2c2,
 539         &am33xx_l4_per__i2c3,
 540         &am33xx_l4_per__mailbox,
 541         &am33xx_l4_ls__mcasp0,
 542         &am33xx_l4_ls__mcasp1,
 543         &am33xx_l4_ls__mmc0,
 544         &am33xx_l4_ls__mmc1,
 545         &am33xx_l3_s__mmc2,
 546         &am33xx_l4_ls__timer2,
 547         &am33xx_l4_ls__timer3,
 548         &am33xx_l4_ls__timer4,
 549         &am33xx_l4_ls__timer5,
 550         &am33xx_l4_ls__timer6,
 551         &am33xx_l4_ls__timer7,
 552         &am33xx_l3_main__tpcc,
 553         &am33xx_l4_ls__uart2,
 554         &am33xx_l4_ls__uart3,
 555         &am33xx_l4_ls__uart4,
 556         &am33xx_l4_ls__uart5,
 557         &am33xx_l4_ls__uart6,
 558         &am33xx_l4_ls__spinlock,
 559         &am33xx_l4_ls__elm,
 560         &am33xx_l4_ls__epwmss0,
 561         &am33xx_l4_ls__epwmss1,
 562         &am33xx_l4_ls__epwmss2,
 563         &am33xx_l3_s__gpmc,
 564         &am33xx_l3_main__lcdc,
 565         &am33xx_l4_ls__mcspi0,
 566         &am33xx_l4_ls__mcspi1,
 567         &am33xx_l3_main__tptc0,
 568         &am33xx_l3_main__tptc1,
 569         &am33xx_l3_main__tptc2,
 570         &am33xx_l3_main__ocmc,
 571         &am33xx_l3_s__usbss,
 572         &am33xx_l4_hs__cpgmac0,
 573         &am33xx_cpgmac0__mdio,
 574         &am33xx_l3_main__sha0,
 575         &am33xx_l3_main__aes0,
 576         &am33xx_l4_per__rng,
 577         NULL,
 578 };
 579
 580 int __init am33xx_hwmod_init(void)
 581 {
 582         omap_hwmod_am33xx_reg();
 583         omap_hwmod_init();
 584         return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
 585 }