mm: fix exec activate_mm vs TLB shootdown and lazy tlb switching race
[linux/fpc-iii.git] / arch / arm / mach-omap2 / prm44xx.c
blob5affa9f5300bc2ef183d7c317fc84a314c2c5143
1 /*
2 * OMAP4 PRM module functions
4 * Copyright (C) 2011-2012 Texas Instruments, Inc.
5 * Copyright (C) 2010 Nokia Corporation
6 * BenoƮt Cousson
7 * Paul Walmsley
8 * Rajendra Nayak <rnayak@ti.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/delay.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/io.h>
20 #include <linux/of_irq.h>
21 #include <linux/of.h>
23 #include "soc.h"
24 #include "iomap.h"
25 #include "common.h"
26 #include "vp.h"
27 #include "prm44xx.h"
28 #include "prcm43xx.h"
29 #include "prm-regbits-44xx.h"
30 #include "prcm44xx.h"
31 #include "prminst44xx.h"
32 #include "powerdomain.h"
34 /* Static data */
36 static void omap44xx_prm_read_pending_irqs(unsigned long *events);
37 static void omap44xx_prm_ocp_barrier(void);
38 static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
39 static void omap44xx_prm_restore_irqen(u32 *saved_mask);
40 static void omap44xx_prm_reconfigure_io_chain(void);
42 static const struct omap_prcm_irq omap4_prcm_irqs[] = {
43 OMAP_PRCM_IRQ("io", 9, 1),
46 static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
47 .ack = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
48 .mask = OMAP4_PRM_IRQENABLE_MPU_OFFSET,
49 .pm_ctrl = OMAP4_PRM_IO_PMCTRL_OFFSET,
50 .nr_regs = 2,
51 .irqs = omap4_prcm_irqs,
52 .nr_irqs = ARRAY_SIZE(omap4_prcm_irqs),
53 .irq = 11 + OMAP44XX_IRQ_GIC_START,
54 .xlate_irq = omap4_xlate_irq,
55 .read_pending_irqs = &omap44xx_prm_read_pending_irqs,
56 .ocp_barrier = &omap44xx_prm_ocp_barrier,
57 .save_and_clear_irqen = &omap44xx_prm_save_and_clear_irqen,
58 .restore_irqen = &omap44xx_prm_restore_irqen,
59 .reconfigure_io_chain = &omap44xx_prm_reconfigure_io_chain,
63 * omap44xx_prm_reset_src_map - map from bits in the PRM_RSTST
64 * hardware register (which are specific to OMAP44xx SoCs) to reset
65 * source ID bit shifts (which is an OMAP SoC-independent
66 * enumeration)
68 static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = {
69 { OMAP4430_GLOBAL_WARM_SW_RST_SHIFT,
70 OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },
71 { OMAP4430_GLOBAL_COLD_RST_SHIFT,
72 OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },
73 { OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT,
74 OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },
75 { OMAP4430_MPU_WDT_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
76 { OMAP4430_SECURE_WDT_RST_SHIFT, OMAP_SECU_WD_RST_SRC_ID_SHIFT },
77 { OMAP4430_EXTERNAL_WARM_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT },
78 { OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT,
79 OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT },
80 { OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT,
81 OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT },
82 { OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT,
83 OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT },
84 { OMAP4430_ICEPICK_RST_SHIFT, OMAP_ICEPICK_RST_SRC_ID_SHIFT },
85 { OMAP4430_C2C_RST_SHIFT, OMAP_C2C_RST_SRC_ID_SHIFT },
86 { -1, -1 },
89 /* PRM low-level functions */
91 /* Read a register in a CM/PRM instance in the PRM module */
92 static u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
94 return readl_relaxed(prm_base.va + inst + reg);
97 /* Write into a register in a CM/PRM instance in the PRM module */
98 static void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
100 writel_relaxed(val, prm_base.va + inst + reg);
103 /* Read-modify-write a register in a PRM module. Caller must lock */
104 static u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
106 u32 v;
108 v = omap4_prm_read_inst_reg(inst, reg);
109 v &= ~mask;
110 v |= bits;
111 omap4_prm_write_inst_reg(v, inst, reg);
113 return v;
116 /* PRM VP */
119 * struct omap4_vp - OMAP4 VP register access description.
120 * @irqstatus_mpu: offset to IRQSTATUS_MPU register for VP
121 * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
123 struct omap4_vp {
124 u32 irqstatus_mpu;
125 u32 tranxdone_status;
128 static struct omap4_vp omap4_vp[] = {
129 [OMAP4_VP_VDD_MPU_ID] = {
130 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
131 .tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
133 [OMAP4_VP_VDD_IVA_ID] = {
134 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
135 .tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
137 [OMAP4_VP_VDD_CORE_ID] = {
138 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
139 .tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
143 static u32 omap4_prm_vp_check_txdone(u8 vp_id)
145 struct omap4_vp *vp = &omap4_vp[vp_id];
146 u32 irqstatus;
148 irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
149 OMAP4430_PRM_OCP_SOCKET_INST,
150 vp->irqstatus_mpu);
151 return irqstatus & vp->tranxdone_status;
154 static void omap4_prm_vp_clear_txdone(u8 vp_id)
156 struct omap4_vp *vp = &omap4_vp[vp_id];
158 omap4_prminst_write_inst_reg(vp->tranxdone_status,
159 OMAP4430_PRM_PARTITION,
160 OMAP4430_PRM_OCP_SOCKET_INST,
161 vp->irqstatus_mpu);
164 u32 omap4_prm_vcvp_read(u8 offset)
166 s32 inst = omap4_prmst_get_prm_dev_inst();
168 if (inst == PRM_INSTANCE_UNKNOWN)
169 return 0;
171 return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
172 inst, offset);
175 void omap4_prm_vcvp_write(u32 val, u8 offset)
177 s32 inst = omap4_prmst_get_prm_dev_inst();
179 if (inst == PRM_INSTANCE_UNKNOWN)
180 return;
182 omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION,
183 inst, offset);
186 u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
188 s32 inst = omap4_prmst_get_prm_dev_inst();
190 if (inst == PRM_INSTANCE_UNKNOWN)
191 return 0;
193 return omap4_prminst_rmw_inst_reg_bits(mask, bits,
194 OMAP4430_PRM_PARTITION,
195 inst,
196 offset);
199 static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs)
201 u32 mask, st;
203 /* XXX read mask from RAM? */
204 mask = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
205 irqen_offs);
206 st = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, irqst_offs);
208 return mask & st;
212 * omap44xx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
213 * @events: ptr to two consecutive u32s, preallocated by caller
215 * Read PRM_IRQSTATUS_MPU* bits, AND'ed with the currently-enabled PRM
216 * MPU IRQs, and store the result into the two u32s pointed to by @events.
217 * No return value.
219 static void omap44xx_prm_read_pending_irqs(unsigned long *events)
221 int i;
223 for (i = 0; i < omap4_prcm_irq_setup.nr_regs; i++)
224 events[i] = _read_pending_irq_reg(omap4_prcm_irq_setup.mask +
225 i * 4, omap4_prcm_irq_setup.ack + i * 4);
229 * omap44xx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
231 * Force any buffered writes to the PRM IP block to complete. Needed
232 * by the PRM IRQ handler, which reads and writes directly to the IP
233 * block, to avoid race conditions after acknowledging or clearing IRQ
234 * bits. No return value.
236 static void omap44xx_prm_ocp_barrier(void)
238 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
239 OMAP4_REVISION_PRM_OFFSET);
243 * omap44xx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU* regs
244 * @saved_mask: ptr to a u32 array to save IRQENABLE bits
246 * Save the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers to
247 * @saved_mask. @saved_mask must be allocated by the caller.
248 * Intended to be used in the PRM interrupt handler suspend callback.
249 * The OCP barrier is needed to ensure the write to disable PRM
250 * interrupts reaches the PRM before returning; otherwise, spurious
251 * interrupts might occur. No return value.
253 static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
255 int i;
256 u16 reg;
258 for (i = 0; i < omap4_prcm_irq_setup.nr_regs; i++) {
259 reg = omap4_prcm_irq_setup.mask + i * 4;
261 saved_mask[i] =
262 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
263 reg);
264 omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST, reg);
267 /* OCP barrier */
268 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
269 OMAP4_REVISION_PRM_OFFSET);
273 * omap44xx_prm_restore_irqen - set PRM_IRQENABLE_MPU* registers from args
274 * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
276 * Restore the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers from
277 * @saved_mask. Intended to be used in the PRM interrupt handler resume
278 * callback to restore values saved by omap44xx_prm_save_and_clear_irqen().
279 * No OCP barrier should be needed here; any pending PRM interrupts will fire
280 * once the writes reach the PRM. No return value.
282 static void omap44xx_prm_restore_irqen(u32 *saved_mask)
284 int i;
286 for (i = 0; i < omap4_prcm_irq_setup.nr_regs; i++)
287 omap4_prm_write_inst_reg(saved_mask[i],
288 OMAP4430_PRM_OCP_SOCKET_INST,
289 omap4_prcm_irq_setup.mask + i * 4);
293 * omap44xx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
295 * Clear any previously-latched I/O wakeup events and ensure that the
296 * I/O wakeup gates are aligned with the current mux settings. Works
297 * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then
298 * deasserting WUCLKIN and waiting for WUCLKOUT to be deasserted.
299 * No return value. XXX Are the final two steps necessary?
301 static void omap44xx_prm_reconfigure_io_chain(void)
303 int i = 0;
304 s32 inst = omap4_prmst_get_prm_dev_inst();
306 if (inst == PRM_INSTANCE_UNKNOWN)
307 return;
309 /* Trigger WUCLKIN enable */
310 omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK,
311 OMAP4430_WUCLK_CTRL_MASK,
312 inst,
313 omap4_prcm_irq_setup.pm_ctrl);
314 omap_test_timeout(
315 (((omap4_prm_read_inst_reg(inst,
316 omap4_prcm_irq_setup.pm_ctrl) &
317 OMAP4430_WUCLK_STATUS_MASK) >>
318 OMAP4430_WUCLK_STATUS_SHIFT) == 1),
319 MAX_IOPAD_LATCH_TIME, i);
320 if (i == MAX_IOPAD_LATCH_TIME)
321 pr_warn("PRM: I/O chain clock line assertion timed out\n");
323 /* Trigger WUCLKIN disable */
324 omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 0x0,
325 inst,
326 omap4_prcm_irq_setup.pm_ctrl);
327 omap_test_timeout(
328 (((omap4_prm_read_inst_reg(inst,
329 omap4_prcm_irq_setup.pm_ctrl) &
330 OMAP4430_WUCLK_STATUS_MASK) >>
331 OMAP4430_WUCLK_STATUS_SHIFT) == 0),
332 MAX_IOPAD_LATCH_TIME, i);
333 if (i == MAX_IOPAD_LATCH_TIME)
334 pr_warn("PRM: I/O chain clock line deassertion timed out\n");
336 return;
340 * omap44xx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
342 * Activates the I/O wakeup event latches and allows events logged by
343 * those latches to signal a wakeup event to the PRCM. For I/O wakeups
344 * to occur, WAKEUPENABLE bits must be set in the pad mux registers, and
345 * omap44xx_prm_reconfigure_io_chain() must be called. No return value.
347 static void omap44xx_prm_enable_io_wakeup(void)
349 s32 inst = omap4_prmst_get_prm_dev_inst();
351 if (inst == PRM_INSTANCE_UNKNOWN)
352 return;
354 omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
355 OMAP4430_GLOBAL_WUEN_MASK,
356 inst,
357 omap4_prcm_irq_setup.pm_ctrl);
361 * omap44xx_prm_read_reset_sources - return the last SoC reset source
363 * Return a u32 representing the last reset sources of the SoC. The
364 * returned reset source bits are standardized across OMAP SoCs.
366 static u32 omap44xx_prm_read_reset_sources(void)
368 struct prm_reset_src_map *p;
369 u32 r = 0;
370 u32 v;
371 s32 inst = omap4_prmst_get_prm_dev_inst();
373 if (inst == PRM_INSTANCE_UNKNOWN)
374 return 0;
377 v = omap4_prm_read_inst_reg(inst,
378 OMAP4_RM_RSTST);
380 p = omap44xx_prm_reset_src_map;
381 while (p->reg_shift >= 0 && p->std_shift >= 0) {
382 if (v & (1 << p->reg_shift))
383 r |= 1 << p->std_shift;
384 p++;
387 return r;
391 * omap44xx_prm_was_any_context_lost_old - was module hardware context lost?
392 * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
393 * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
394 * @idx: CONTEXT register offset
396 * Return 1 if any bits were set in the *_CONTEXT_* register
397 * identified by (@part, @inst, @idx), which means that some context
398 * was lost for that module; otherwise, return 0.
400 static bool omap44xx_prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx)
402 return (omap4_prminst_read_inst_reg(part, inst, idx)) ? 1 : 0;
406 * omap44xx_prm_clear_context_lost_flags_old - clear context loss flags
407 * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
408 * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
409 * @idx: CONTEXT register offset
411 * Clear hardware context loss bits for the module identified by
412 * (@part, @inst, @idx). No return value. XXX Writes to reserved bits;
413 * is there a way to avoid this?
415 static void omap44xx_prm_clear_context_loss_flags_old(u8 part, s16 inst,
416 u16 idx)
418 omap4_prminst_write_inst_reg(0xffffffff, part, inst, idx);
421 /* Powerdomain low-level functions */
423 static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
425 omap4_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK,
426 (pwrst << OMAP_POWERSTATE_SHIFT),
427 pwrdm->prcm_partition,
428 pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
429 return 0;
432 static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
434 u32 v;
436 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
437 OMAP4_PM_PWSTCTRL);
438 v &= OMAP_POWERSTATE_MASK;
439 v >>= OMAP_POWERSTATE_SHIFT;
441 return v;
444 static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm)
446 u32 v;
448 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
449 OMAP4_PM_PWSTST);
450 v &= OMAP_POWERSTATEST_MASK;
451 v >>= OMAP_POWERSTATEST_SHIFT;
453 return v;
456 static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
458 u32 v;
460 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
461 OMAP4_PM_PWSTST);
462 v &= OMAP4430_LASTPOWERSTATEENTERED_MASK;
463 v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT;
465 return v;
468 static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
470 omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
471 (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
472 pwrdm->prcm_partition,
473 pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
474 return 0;
477 static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
479 omap4_prminst_rmw_inst_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK,
480 OMAP4430_LASTPOWERSTATEENTERED_MASK,
481 pwrdm->prcm_partition,
482 pwrdm->prcm_offs, OMAP4_PM_PWSTST);
483 return 0;
486 static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
488 u32 v;
490 v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK);
491 omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v,
492 pwrdm->prcm_partition, pwrdm->prcm_offs,
493 OMAP4_PM_PWSTCTRL);
495 return 0;
498 static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
499 u8 pwrst)
501 u32 m;
503 m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
505 omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
506 pwrdm->prcm_partition, pwrdm->prcm_offs,
507 OMAP4_PM_PWSTCTRL);
509 return 0;
512 static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
513 u8 pwrst)
515 u32 m;
517 m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
519 omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
520 pwrdm->prcm_partition, pwrdm->prcm_offs,
521 OMAP4_PM_PWSTCTRL);
523 return 0;
526 static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
528 u32 v;
530 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
531 OMAP4_PM_PWSTST);
532 v &= OMAP4430_LOGICSTATEST_MASK;
533 v >>= OMAP4430_LOGICSTATEST_SHIFT;
535 return v;
538 static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
540 u32 v;
542 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
543 OMAP4_PM_PWSTCTRL);
544 v &= OMAP4430_LOGICRETSTATE_MASK;
545 v >>= OMAP4430_LOGICRETSTATE_SHIFT;
547 return v;
551 * omap4_pwrdm_read_prev_logic_pwrst - read the previous logic powerstate
552 * @pwrdm: struct powerdomain * to read the state for
554 * Reads the previous logic powerstate for a powerdomain. This
555 * function must determine the previous logic powerstate by first
556 * checking the previous powerstate for the domain. If that was OFF,
557 * then logic has been lost. If previous state was RETENTION, the
558 * function reads the setting for the next retention logic state to
559 * see the actual value. In every other case, the logic is
560 * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
561 * depending whether the logic was retained or not.
563 static int omap4_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
565 int state;
567 state = omap4_pwrdm_read_prev_pwrst(pwrdm);
569 if (state == PWRDM_POWER_OFF)
570 return PWRDM_POWER_OFF;
572 if (state != PWRDM_POWER_RET)
573 return PWRDM_POWER_RET;
575 return omap4_pwrdm_read_logic_retst(pwrdm);
578 static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
580 u32 m, v;
582 m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
584 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
585 OMAP4_PM_PWSTST);
586 v &= m;
587 v >>= __ffs(m);
589 return v;
592 static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
594 u32 m, v;
596 m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
598 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
599 OMAP4_PM_PWSTCTRL);
600 v &= m;
601 v >>= __ffs(m);
603 return v;
607 * omap4_pwrdm_read_prev_mem_pwrst - reads the previous memory powerstate
608 * @pwrdm: struct powerdomain * to read mem powerstate for
609 * @bank: memory bank index
611 * Reads the previous memory powerstate for a powerdomain. This
612 * function must determine the previous memory powerstate by first
613 * checking the previous powerstate for the domain. If that was OFF,
614 * then logic has been lost. If previous state was RETENTION, the
615 * function reads the setting for the next memory retention state to
616 * see the actual value. In every other case, the logic is
617 * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
618 * depending whether logic was retained or not.
620 static int omap4_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
622 int state;
624 state = omap4_pwrdm_read_prev_pwrst(pwrdm);
626 if (state == PWRDM_POWER_OFF)
627 return PWRDM_POWER_OFF;
629 if (state != PWRDM_POWER_RET)
630 return PWRDM_POWER_RET;
632 return omap4_pwrdm_read_mem_retst(pwrdm, bank);
635 static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
637 u32 c = 0;
640 * REVISIT: pwrdm_wait_transition() may be better implemented
641 * via a callback and a periodic timer check -- how long do we expect
642 * powerdomain transitions to take?
645 /* XXX Is this udelay() value meaningful? */
646 while ((omap4_prminst_read_inst_reg(pwrdm->prcm_partition,
647 pwrdm->prcm_offs,
648 OMAP4_PM_PWSTST) &
649 OMAP_INTRANSITION_MASK) &&
650 (c++ < PWRDM_TRANSITION_BAILOUT))
651 udelay(1);
653 if (c > PWRDM_TRANSITION_BAILOUT) {
654 pr_err("powerdomain: %s: waited too long to complete transition\n",
655 pwrdm->name);
656 return -EAGAIN;
659 pr_debug("powerdomain: completed transition in %d loops\n", c);
661 return 0;
664 static int omap4_check_vcvp(void)
666 if (prm_features & PRM_HAS_VOLTAGE)
667 return 1;
669 return 0;
672 struct pwrdm_ops omap4_pwrdm_operations = {
673 .pwrdm_set_next_pwrst = omap4_pwrdm_set_next_pwrst,
674 .pwrdm_read_next_pwrst = omap4_pwrdm_read_next_pwrst,
675 .pwrdm_read_pwrst = omap4_pwrdm_read_pwrst,
676 .pwrdm_read_prev_pwrst = omap4_pwrdm_read_prev_pwrst,
677 .pwrdm_set_lowpwrstchange = omap4_pwrdm_set_lowpwrstchange,
678 .pwrdm_clear_all_prev_pwrst = omap4_pwrdm_clear_all_prev_pwrst,
679 .pwrdm_set_logic_retst = omap4_pwrdm_set_logic_retst,
680 .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst,
681 .pwrdm_read_prev_logic_pwrst = omap4_pwrdm_read_prev_logic_pwrst,
682 .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst,
683 .pwrdm_read_mem_pwrst = omap4_pwrdm_read_mem_pwrst,
684 .pwrdm_read_mem_retst = omap4_pwrdm_read_mem_retst,
685 .pwrdm_read_prev_mem_pwrst = omap4_pwrdm_read_prev_mem_pwrst,
686 .pwrdm_set_mem_onst = omap4_pwrdm_set_mem_onst,
687 .pwrdm_set_mem_retst = omap4_pwrdm_set_mem_retst,
688 .pwrdm_wait_transition = omap4_pwrdm_wait_transition,
689 .pwrdm_has_voltdm = omap4_check_vcvp,
692 static int omap44xx_prm_late_init(void);
695 * XXX document
697 static struct prm_ll_data omap44xx_prm_ll_data = {
698 .read_reset_sources = &omap44xx_prm_read_reset_sources,
699 .was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old,
700 .clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old,
701 .late_init = &omap44xx_prm_late_init,
702 .assert_hardreset = omap4_prminst_assert_hardreset,
703 .deassert_hardreset = omap4_prminst_deassert_hardreset,
704 .is_hardreset_asserted = omap4_prminst_is_hardreset_asserted,
705 .reset_system = omap4_prminst_global_warm_sw_reset,
706 .vp_check_txdone = omap4_prm_vp_check_txdone,
707 .vp_clear_txdone = omap4_prm_vp_clear_txdone,
710 static const struct omap_prcm_init_data *prm_init_data;
712 int __init omap44xx_prm_init(const struct omap_prcm_init_data *data)
714 omap_prm_base_init();
716 prm_init_data = data;
718 if (data->flags & PRM_HAS_IO_WAKEUP)
719 prm_features |= PRM_HAS_IO_WAKEUP;
721 if (data->flags & PRM_HAS_VOLTAGE)
722 prm_features |= PRM_HAS_VOLTAGE;
724 omap4_prminst_set_prm_dev_inst(data->device_inst_offset);
726 /* Add AM437X specific differences */
727 if (of_device_is_compatible(data->np, "ti,am4-prcm")) {
728 omap4_prcm_irq_setup.nr_irqs = 1;
729 omap4_prcm_irq_setup.nr_regs = 1;
730 omap4_prcm_irq_setup.pm_ctrl = AM43XX_PRM_IO_PMCTRL_OFFSET;
731 omap4_prcm_irq_setup.ack = AM43XX_PRM_IRQSTATUS_MPU_OFFSET;
732 omap4_prcm_irq_setup.mask = AM43XX_PRM_IRQENABLE_MPU_OFFSET;
735 return prm_register(&omap44xx_prm_ll_data);
738 static int omap44xx_prm_late_init(void)
740 int irq_num;
742 if (!(prm_features & PRM_HAS_IO_WAKEUP))
743 return 0;
745 irq_num = of_irq_get(prm_init_data->np, 0);
747 * Already have OMAP4 IRQ num. For all other platforms, we need
748 * IRQ numbers from DT
750 if (irq_num <= 0 && !(prm_init_data->flags & PRM_IRQ_DEFAULT)) {
751 if (irq_num == -EPROBE_DEFER)
752 return irq_num;
754 /* Have nothing to do */
755 return 0;
758 /* Once OMAP4 DT is filled as well */
759 if (irq_num > 0) {
760 omap4_prcm_irq_setup.irq = irq_num;
761 omap4_prcm_irq_setup.xlate_irq = NULL;
764 omap44xx_prm_enable_io_wakeup();
766 return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
769 static void __exit omap44xx_prm_exit(void)
771 prm_unregister(&omap44xx_prm_ll_data);
773 __exitcall(omap44xx_prm_exit);