mm: fix exec activate_mm vs TLB shootdown and lazy tlb switching race
[linux/fpc-iii.git] / arch / arm / mach-omap2 / sram.h
blob18dc884267fa6b6efa37a18596843e4e595773e3
1 /*
2 * Interface for functions that need to be run in internal SRAM
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
9 #ifndef __ASSEMBLY__
10 #include <plat/sram.h>
12 extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
13 u32 base_cs, u32 force_unlock);
14 extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
15 u32 mem_type);
16 extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
18 extern void omap3_sram_restore_context(void);
20 /* Do not use these */
21 extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
22 extern unsigned long omap24xx_sram_reprogram_clock_sz;
24 extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
25 u32 base_cs, u32 force_unlock);
26 extern unsigned long omap242x_sram_ddr_init_sz;
28 extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
29 int bypass);
30 extern unsigned long omap242x_sram_set_prcm_sz;
32 extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
33 u32 mem_type);
34 extern unsigned long omap242x_sram_reprogram_sdrc_sz;
37 extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
38 u32 base_cs, u32 force_unlock);
39 extern unsigned long omap243x_sram_ddr_init_sz;
41 extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
42 int bypass);
43 extern unsigned long omap243x_sram_set_prcm_sz;
45 extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
46 u32 mem_type);
47 extern unsigned long omap243x_sram_reprogram_sdrc_sz;
49 #ifdef CONFIG_PM
50 extern void omap_push_sram_idle(void);
51 #else
52 static inline void omap_push_sram_idle(void) {}
53 #endif /* CONFIG_PM */
55 #endif /* __ASSEMBLY__ */
58 * OMAP2+: define the SRAM PA addresses.
59 * Used by the SRAM management code and the idle sleep code.
61 #define OMAP2_SRAM_PA 0x40200000
62 #define OMAP3_SRAM_PA 0x40200000