2 * OMAP Voltage Controller (VC) interface
4 * Copyright (C) 2011 Texas Instruments, Inc.
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/bug.h>
16 #include <asm/div64.h>
22 #include "prm-regbits-34xx.h"
23 #include "prm-regbits-44xx.h"
30 * struct omap_vc_channel_cfg - describe the cfg_channel bitfield
31 * @sa: bit for slave address
32 * @rav: bit for voltage configuration register
33 * @rac: bit for command configuration register
34 * @racen: enable bit for RAC
35 * @cmd: bit for command value set selection
37 * Channel configuration bits, common for OMAP3+
38 * OMAP3 register: PRM_VC_CH_CONF
39 * OMAP4 register: PRM_VC_CFG_CHANNEL
40 * OMAP5 register: PRM_VC_SMPS_<voltdm>_CONFIG
42 struct omap_vc_channel_cfg
{
50 static struct omap_vc_channel_cfg vc_default_channel_cfg
= {
59 * On OMAP3+, all VC channels have the above default bitfield
60 * configuration, except the OMAP4 MPU channel. This appears
61 * to be a freak accident as every other VC channel has the
62 * default configuration, thus creating a mutant channel config.
64 static struct omap_vc_channel_cfg vc_mutant_channel_cfg
= {
72 static struct omap_vc_channel_cfg
*vc_cfg_bits
;
74 /* Default I2C trace length on pcb, 6.3cm. Used for capacitance calculations. */
75 static u32 sr_i2c_pcb_length
= 63;
76 #define CFG_CHANNEL_MASK 0x1f
79 * omap_vc_config_channel - configure VC channel to PMIC mappings
80 * @voltdm: pointer to voltagdomain defining the desired VC channel
82 * Configures the VC channel to PMIC mappings for the following
84 * - i2c slave address (SA)
85 * - voltage configuration address (RAV)
86 * - command configuration address (RAC) and enable bit (RACEN)
87 * - command values for ON, ONLP, RET and OFF (CMD)
89 * This function currently only allows flexible configuration of the
90 * non-default channel. Starting with OMAP4, there are more than 2
91 * channels, with one defined as the default (on OMAP4, it's MPU.)
92 * Only the non-default channel can be configured.
94 static int omap_vc_config_channel(struct voltagedomain
*voltdm
)
96 struct omap_vc_channel
*vc
= voltdm
->vc
;
99 * For default channel, the only configurable bit is RACEN.
100 * All others must stay at zero (see function comment above.)
102 if (vc
->flags
& OMAP_VC_CHANNEL_DEFAULT
)
103 vc
->cfg_channel
&= vc_cfg_bits
->racen
;
105 voltdm
->rmw(CFG_CHANNEL_MASK
<< vc
->cfg_channel_sa_shift
,
106 vc
->cfg_channel
<< vc
->cfg_channel_sa_shift
,
107 vc
->cfg_channel_reg
);
112 /* Voltage scale and accessory APIs */
113 int omap_vc_pre_scale(struct voltagedomain
*voltdm
,
114 unsigned long target_volt
,
115 u8
*target_vsel
, u8
*current_vsel
)
117 struct omap_vc_channel
*vc
= voltdm
->vc
;
120 /* Check if sufficient pmic info is available for this vdd */
122 pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
123 __func__
, voltdm
->name
);
127 if (!voltdm
->pmic
->uv_to_vsel
) {
128 pr_err("%s: PMIC function to convert voltage in uV to vsel not registered. Hence unable to scale voltage for vdd_%s\n",
129 __func__
, voltdm
->name
);
133 if (!voltdm
->read
|| !voltdm
->write
) {
134 pr_err("%s: No read/write API for accessing vdd_%s regs\n",
135 __func__
, voltdm
->name
);
139 *target_vsel
= voltdm
->pmic
->uv_to_vsel(target_volt
);
140 *current_vsel
= voltdm
->pmic
->uv_to_vsel(voltdm
->nominal_volt
);
142 /* Setting the ON voltage to the new target voltage */
143 vc_cmdval
= voltdm
->read(vc
->cmdval_reg
);
144 vc_cmdval
&= ~vc
->common
->cmd_on_mask
;
145 vc_cmdval
|= (*target_vsel
<< vc
->common
->cmd_on_shift
);
146 voltdm
->write(vc_cmdval
, vc
->cmdval_reg
);
148 voltdm
->vc_param
->on
= target_volt
;
150 omap_vp_update_errorgain(voltdm
, target_volt
);
155 void omap_vc_post_scale(struct voltagedomain
*voltdm
,
156 unsigned long target_volt
,
157 u8 target_vsel
, u8 current_vsel
)
159 u32 smps_steps
= 0, smps_delay
= 0;
161 smps_steps
= abs(target_vsel
- current_vsel
);
162 /* SMPS slew rate / step size. 2us added as buffer. */
163 smps_delay
= ((smps_steps
* voltdm
->pmic
->step_size
) /
164 voltdm
->pmic
->slew_rate
) + 2;
168 /* vc_bypass_scale - VC bypass method of voltage scaling */
169 int omap_vc_bypass_scale(struct voltagedomain
*voltdm
,
170 unsigned long target_volt
)
172 struct omap_vc_channel
*vc
= voltdm
->vc
;
173 u32 loop_cnt
= 0, retries_cnt
= 0;
174 u32 vc_valid
, vc_bypass_val_reg
, vc_bypass_value
;
175 u8 target_vsel
, current_vsel
;
178 ret
= omap_vc_pre_scale(voltdm
, target_volt
, &target_vsel
, ¤t_vsel
);
182 vc_valid
= vc
->common
->valid
;
183 vc_bypass_val_reg
= vc
->common
->bypass_val_reg
;
184 vc_bypass_value
= (target_vsel
<< vc
->common
->data_shift
) |
185 (vc
->volt_reg_addr
<< vc
->common
->regaddr_shift
) |
186 (vc
->i2c_slave_addr
<< vc
->common
->slaveaddr_shift
);
188 voltdm
->write(vc_bypass_value
, vc_bypass_val_reg
);
189 voltdm
->write(vc_bypass_value
| vc_valid
, vc_bypass_val_reg
);
191 vc_bypass_value
= voltdm
->read(vc_bypass_val_reg
);
193 * Loop till the bypass command is acknowledged from the SMPS.
194 * NOTE: This is legacy code. The loop count and retry count needs
197 while (!(vc_bypass_value
& vc_valid
)) {
200 if (retries_cnt
> 10) {
201 pr_warn("%s: Retry count exceeded\n", __func__
);
210 vc_bypass_value
= voltdm
->read(vc_bypass_val_reg
);
213 omap_vc_post_scale(voltdm
, target_volt
, target_vsel
, current_vsel
);
217 /* Convert microsecond value to number of 32kHz clock cycles */
218 static inline u32
omap_usec_to_32k(u32 usec
)
220 return DIV_ROUND_UP_ULL(32768ULL * (u64
)usec
, 1000000ULL);
223 struct omap3_vc_timings
{
229 struct voltagedomain
*vd
;
233 struct omap3_vc_timings timings
[2];
235 static struct omap3_vc vc
;
237 void omap3_vc_set_pmic_signaling(int core_next_state
)
239 struct voltagedomain
*vd
= vc
.vd
;
240 struct omap3_vc_timings
*c
= vc
.timings
;
241 u32 voltctrl
, voltsetup1
, voltsetup2
;
243 voltctrl
= vc
.voltctrl
;
244 voltsetup1
= vc
.voltsetup1
;
245 voltsetup2
= vc
.voltsetup2
;
247 switch (core_next_state
) {
248 case PWRDM_POWER_OFF
:
249 voltctrl
&= ~(OMAP3430_PRM_VOLTCTRL_AUTO_RET
|
250 OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP
);
251 voltctrl
|= OMAP3430_PRM_VOLTCTRL_AUTO_OFF
;
252 if (voltctrl
& OMAP3430_PRM_VOLTCTRL_SEL_OFF
)
253 voltsetup2
= c
->voltsetup2
;
255 voltsetup1
= c
->voltsetup1
;
257 case PWRDM_POWER_RET
:
260 voltctrl
&= ~(OMAP3430_PRM_VOLTCTRL_AUTO_OFF
|
261 OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP
);
262 voltctrl
|= OMAP3430_PRM_VOLTCTRL_AUTO_RET
;
263 voltsetup1
= c
->voltsetup1
;
267 if (voltctrl
!= vc
.voltctrl
) {
268 vd
->write(voltctrl
, OMAP3_PRM_VOLTCTRL_OFFSET
);
269 vc
.voltctrl
= voltctrl
;
271 if (voltsetup1
!= vc
.voltsetup1
) {
272 vd
->write(c
->voltsetup1
,
273 OMAP3_PRM_VOLTSETUP1_OFFSET
);
274 vc
.voltsetup1
= voltsetup1
;
276 if (voltsetup2
!= vc
.voltsetup2
) {
277 vd
->write(c
->voltsetup2
,
278 OMAP3_PRM_VOLTSETUP2_OFFSET
);
279 vc
.voltsetup2
= voltsetup2
;
284 * Configure signal polarity for sys_clkreq and sys_off_mode pins
285 * as the default values are wrong and can cause the system to hang
286 * if any twl4030 scripts are loaded.
288 static void __init
omap3_vc_init_pmic_signaling(struct voltagedomain
*voltdm
)
297 val
= voltdm
->read(OMAP3_PRM_POLCTRL_OFFSET
);
298 if (!(val
& OMAP3430_PRM_POLCTRL_CLKREQ_POL
) ||
299 (val
& OMAP3430_PRM_POLCTRL_OFFMODE_POL
)) {
300 val
|= OMAP3430_PRM_POLCTRL_CLKREQ_POL
;
301 val
&= ~OMAP3430_PRM_POLCTRL_OFFMODE_POL
;
302 pr_debug("PM: fixing sys_clkreq and sys_off_mode polarity to 0x%x\n",
304 voltdm
->write(val
, OMAP3_PRM_POLCTRL_OFFSET
);
308 * By default let's use I2C4 signaling for retention idle
309 * and sys_off_mode pin signaling for off idle. This way we
310 * have sys_clk_req pin go down for retention and both
311 * sys_clk_req and sys_off_mode pins will go down for off
312 * idle. And we can also scale voltages to zero for off-idle.
313 * Note that no actual voltage scaling during off-idle will
314 * happen unless the board specific twl4030 PMIC scripts are
315 * loaded. See also omap_vc_i2c_init for comments regarding
318 val
= voltdm
->read(OMAP3_PRM_VOLTCTRL_OFFSET
);
319 if (!(val
& OMAP3430_PRM_VOLTCTRL_SEL_OFF
)) {
320 val
|= OMAP3430_PRM_VOLTCTRL_SEL_OFF
;
321 pr_debug("PM: setting voltctrl sys_off_mode signaling to 0x%x\n",
323 voltdm
->write(val
, OMAP3_PRM_VOLTCTRL_OFFSET
);
327 omap3_vc_set_pmic_signaling(PWRDM_POWER_ON
);
330 static void omap3_init_voltsetup1(struct voltagedomain
*voltdm
,
331 struct omap3_vc_timings
*c
, u32 idle
)
335 val
= (voltdm
->vc_param
->on
- idle
) / voltdm
->pmic
->slew_rate
;
336 val
*= voltdm
->sys_clk
.rate
/ 8 / 1000000 + 1;
337 val
<<= __ffs(voltdm
->vfsm
->voltsetup_mask
);
338 c
->voltsetup1
&= ~voltdm
->vfsm
->voltsetup_mask
;
339 c
->voltsetup1
|= val
;
343 * omap3_set_i2c_timings - sets i2c sleep timings for a channel
344 * @voltdm: channel to configure
345 * @off_mode: select whether retention or off mode values used
347 * Calculates and sets up voltage controller to use I2C based
348 * voltage scaling for sleep modes. This can be used for either off mode
349 * or retention. Off mode has additionally an option to use sys_off_mode
350 * pad, which uses a global signal to program the whole power IC to
353 * Note that pmic is not controlling the voltage scaling during
354 * retention signaled over I2C4, so we can keep voltsetup2 as 0.
355 * And the oscillator is not shut off over I2C4, so no need to
358 static void omap3_set_i2c_timings(struct voltagedomain
*voltdm
)
360 struct omap3_vc_timings
*c
= vc
.timings
;
362 /* Configure PRWDM_POWER_OFF over I2C4 */
363 omap3_init_voltsetup1(voltdm
, c
, voltdm
->vc_param
->off
);
365 /* Configure PRWDM_POWER_RET over I2C4 */
366 omap3_init_voltsetup1(voltdm
, c
, voltdm
->vc_param
->ret
);
370 * omap3_set_off_timings - sets off-mode timings for a channel
371 * @voltdm: channel to configure
373 * Calculates and sets up off-mode timings for a channel. Off-mode
374 * can use either I2C based voltage scaling, or alternatively
375 * sys_off_mode pad can be used to send a global command to power IC.n,
376 * sys_off_mode has the additional benefit that voltages can be
377 * scaled to zero volt level with TWL4030 / TWL5030, I2C can only
380 * Note that omap is not controlling the voltage scaling during
381 * off idle signaled by sys_off_mode, so we can keep voltsetup1
384 static void omap3_set_off_timings(struct voltagedomain
*voltdm
)
386 struct omap3_vc_timings
*c
= vc
.timings
;
387 u32 tstart
, tshut
, clksetup
, voltoffset
;
392 omap_pm_get_oscillator(&tstart
, &tshut
);
393 if (tstart
== ULONG_MAX
) {
394 pr_debug("PM: oscillator start-up time not initialized, using 10ms\n");
395 clksetup
= omap_usec_to_32k(10000);
397 clksetup
= omap_usec_to_32k(tstart
);
401 * For twl4030 errata 27, we need to allow minimum ~488.32 us wait to
402 * switch from HFCLKIN to internal oscillator. That means timings
403 * have voltoffset fixed to 0xa in rounded up 32 KiHz cycles. And
404 * that means we can calculate the value based on the oscillator
405 * start-up time since voltoffset2 = clksetup - voltoffset.
407 voltoffset
= omap_usec_to_32k(488);
408 c
->voltsetup2
= clksetup
- voltoffset
;
409 voltdm
->write(clksetup
, OMAP3_PRM_CLKSETUP_OFFSET
);
410 voltdm
->write(voltoffset
, OMAP3_PRM_VOLTOFFSET_OFFSET
);
413 static void __init
omap3_vc_init_channel(struct voltagedomain
*voltdm
)
415 omap3_vc_init_pmic_signaling(voltdm
);
416 omap3_set_off_timings(voltdm
);
417 omap3_set_i2c_timings(voltdm
);
421 * omap4_calc_volt_ramp - calculates voltage ramping delays on omap4
422 * @voltdm: channel to calculate values for
423 * @voltage_diff: voltage difference in microvolts
425 * Calculates voltage ramp prescaler + counter values for a voltage
426 * difference on omap4. Returns a field value suitable for writing to
427 * VOLTSETUP register for a channel in following format:
428 * bits[8:9] prescaler ... bits[0:5] counter. See OMAP4 TRM for reference.
430 static u32
omap4_calc_volt_ramp(struct voltagedomain
*voltdm
, u32 voltage_diff
)
436 time
= voltage_diff
/ voltdm
->pmic
->slew_rate
;
438 cycles
= voltdm
->sys_clk
.rate
/ 1000 * time
/ 1000;
443 /* shift to next prescaler until no overflow */
445 /* scale for div 256 = 64 * 4 */
451 /* scale for div 512 = 256 * 2 */
457 /* scale for div 2048 = 512 * 4 */
463 /* check for overflow => invalid ramp time */
465 pr_warn("%s: invalid setuptime for vdd_%s\n", __func__
,
472 return (prescaler
<< OMAP4430_RAMP_UP_PRESCAL_SHIFT
) |
473 (cycles
<< OMAP4430_RAMP_UP_COUNT_SHIFT
);
477 * omap4_usec_to_val_scrm - convert microsecond value to SCRM module bitfield
478 * @usec: microseconds
479 * @shift: number of bits to shift left
480 * @mask: bitfield mask
482 * Converts microsecond value to OMAP4 SCRM bitfield. Bitfield is
483 * shifted to requested position, and checked agains the mask value.
484 * If larger, forced to the max value of the field (i.e. the mask itself.)
485 * Returns the SCRM bitfield value.
487 static u32
omap4_usec_to_val_scrm(u32 usec
, int shift
, u32 mask
)
491 val
= omap_usec_to_32k(usec
) << shift
;
493 /* Check for overflow, if yes, force to max value */
501 * omap4_set_timings - set voltage ramp timings for a channel
502 * @voltdm: channel to configure
503 * @off_mode: whether off-mode values are used
505 * Calculates and sets the voltage ramp up / down values for a channel.
507 static void omap4_set_timings(struct voltagedomain
*voltdm
, bool off_mode
)
515 ramp
= omap4_calc_volt_ramp(voltdm
,
516 voltdm
->vc_param
->on
- voltdm
->vc_param
->off
);
517 offset
= voltdm
->vfsm
->voltsetup_off_reg
;
519 ramp
= omap4_calc_volt_ramp(voltdm
,
520 voltdm
->vc_param
->on
- voltdm
->vc_param
->ret
);
521 offset
= voltdm
->vfsm
->voltsetup_reg
;
527 val
= voltdm
->read(offset
);
529 val
|= ramp
<< OMAP4430_RAMP_DOWN_COUNT_SHIFT
;
531 val
|= ramp
<< OMAP4430_RAMP_UP_COUNT_SHIFT
;
533 voltdm
->write(val
, offset
);
535 omap_pm_get_oscillator(&tstart
, &tshut
);
537 val
= omap4_usec_to_val_scrm(tstart
, OMAP4_SETUPTIME_SHIFT
,
538 OMAP4_SETUPTIME_MASK
);
539 val
|= omap4_usec_to_val_scrm(tshut
, OMAP4_DOWNTIME_SHIFT
,
540 OMAP4_DOWNTIME_MASK
);
542 writel_relaxed(val
, OMAP4_SCRM_CLKSETUPTIME
);
545 /* OMAP4 specific voltage init functions */
546 static void __init
omap4_vc_init_channel(struct voltagedomain
*voltdm
)
548 omap4_set_timings(voltdm
, true);
549 omap4_set_timings(voltdm
, false);
552 struct i2c_init_data
{
562 static const struct i2c_init_data omap4_i2c_timing_data
[] __initconst
= {
602 * omap4_vc_i2c_timing_init - sets up board I2C timing parameters
603 * @voltdm: voltagedomain pointer to get data from
605 * Use PMIC + board supplied settings for calculating the total I2C
606 * channel capacitance and set the timing parameters based on this.
607 * Pre-calculated values are provided in data tables, as it is not
608 * too straightforward to calculate these runtime.
610 static void __init
omap4_vc_i2c_timing_init(struct voltagedomain
*voltdm
)
615 const struct i2c_init_data
*i2c_data
;
617 if (!voltdm
->pmic
->i2c_high_speed
) {
618 pr_warn("%s: only high speed supported!\n", __func__
);
622 /* PCB trace capacitance, 0.125pF / mm => mm / 8 */
623 capacitance
= DIV_ROUND_UP(sr_i2c_pcb_length
, 8);
625 /* OMAP pad capacitance */
628 /* PMIC pad capacitance */
629 capacitance
+= voltdm
->pmic
->i2c_pad_load
;
631 /* Search for capacitance match in the table */
632 i2c_data
= omap4_i2c_timing_data
;
634 while (i2c_data
->load
> capacitance
)
637 /* Select proper values based on sysclk frequency */
638 switch (voltdm
->sys_clk
.rate
) {
640 hsscll
= i2c_data
->hsscll_38_4
;
643 hsscll
= i2c_data
->hsscll_26
;
646 hsscll
= i2c_data
->hsscll_19_2
;
649 hsscll
= i2c_data
->hsscll_16_8
;
652 hsscll
= i2c_data
->hsscll_12
;
655 pr_warn("%s: unsupported sysclk rate: %d!\n", __func__
,
656 voltdm
->sys_clk
.rate
);
660 /* Loadbits define pull setup for the I2C channels */
661 val
= i2c_data
->loadbits
<< 25 | i2c_data
->loadbits
<< 29;
663 /* Write to SYSCTRL_PADCONF_WKUP_CTRL_I2C_2 to setup I2C pull */
664 writel_relaxed(val
, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP
+
665 OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2
));
667 /* HSSCLH can always be zero */
668 val
= hsscll
<< OMAP4430_HSSCLL_SHIFT
;
669 val
|= (0x28 << OMAP4430_SCLL_SHIFT
| 0x2c << OMAP4430_SCLH_SHIFT
);
671 /* Write setup times to I2C config register */
672 voltdm
->write(val
, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET
);
678 * omap_vc_i2c_init - initialize I2C interface to PMIC
679 * @voltdm: voltage domain containing VC data
681 * Use PMIC supplied settings for I2C high-speed mode and
682 * master code (if set) and program the VC I2C configuration
685 * The VC I2C configuration is common to all VC channels,
686 * so this function only configures I2C for the first VC
687 * channel registers. All other VC channels will use the
688 * same configuration.
690 static void __init
omap_vc_i2c_init(struct voltagedomain
*voltdm
)
692 struct omap_vc_channel
*vc
= voltdm
->vc
;
693 static bool initialized
;
694 static bool i2c_high_speed
;
698 if (voltdm
->pmic
->i2c_high_speed
!= i2c_high_speed
)
699 pr_warn("%s: I2C config for vdd_%s does not match other channels (%u).\n",
700 __func__
, voltdm
->name
, i2c_high_speed
);
705 * Note that for omap3 OMAP3430_SREN_MASK clears SREN to work around
706 * erratum i531 "Extra Power Consumed When Repeated Start Operation
707 * Mode Is Enabled on I2C Interface Dedicated for Smart Reflex (I2C4)".
708 * Otherwise I2C4 eventually leads into about 23mW extra power being
709 * consumed even during off idle using VMODE.
711 i2c_high_speed
= voltdm
->pmic
->i2c_high_speed
;
713 voltdm
->rmw(vc
->common
->i2c_cfg_clear_mask
,
714 vc
->common
->i2c_cfg_hsen_mask
,
715 vc
->common
->i2c_cfg_reg
);
717 mcode
= voltdm
->pmic
->i2c_mcode
;
719 voltdm
->rmw(vc
->common
->i2c_mcode_mask
,
720 mcode
<< __ffs(vc
->common
->i2c_mcode_mask
),
721 vc
->common
->i2c_cfg_reg
);
723 if (cpu_is_omap44xx())
724 omap4_vc_i2c_timing_init(voltdm
);
730 * omap_vc_calc_vsel - calculate vsel value for a channel
731 * @voltdm: channel to calculate value for
732 * @uvolt: microvolt value to convert to vsel
734 * Converts a microvolt value to vsel value for the used PMIC.
735 * This checks whether the microvolt value is out of bounds, and
736 * adjusts the value accordingly. If unsupported value detected,
739 static u8
omap_vc_calc_vsel(struct voltagedomain
*voltdm
, u32 uvolt
)
741 if (voltdm
->pmic
->vddmin
> uvolt
)
742 uvolt
= voltdm
->pmic
->vddmin
;
743 if (voltdm
->pmic
->vddmax
< uvolt
) {
744 WARN(1, "%s: voltage not supported by pmic: %u vs max %u\n",
745 __func__
, uvolt
, voltdm
->pmic
->vddmax
);
746 /* Lets try maximum value anyway */
747 uvolt
= voltdm
->pmic
->vddmax
;
750 return voltdm
->pmic
->uv_to_vsel(uvolt
);
755 * omap_pm_setup_sr_i2c_pcb_length - set length of SR I2C traces on PCB
756 * @mm: length of the PCB trace in millimetres
758 * Sets the PCB trace length for the I2C channel. By default uses 63mm.
759 * This is needed for properly calculating the capacitance value for
760 * the PCB trace, and for setting the SR I2C channel timing parameters.
762 void __init
omap_pm_setup_sr_i2c_pcb_length(u32 mm
)
764 sr_i2c_pcb_length
= mm
;
768 void __init
omap_vc_init_channel(struct voltagedomain
*voltdm
)
770 struct omap_vc_channel
*vc
= voltdm
->vc
;
771 u8 on_vsel
, onlp_vsel
, ret_vsel
, off_vsel
;
774 if (!voltdm
->pmic
|| !voltdm
->pmic
->uv_to_vsel
) {
775 pr_err("%s: No PMIC info for vdd_%s\n", __func__
, voltdm
->name
);
779 if (!voltdm
->read
|| !voltdm
->write
) {
780 pr_err("%s: No read/write API for accessing vdd_%s regs\n",
781 __func__
, voltdm
->name
);
786 if (vc
->flags
& OMAP_VC_CHANNEL_CFG_MUTANT
)
787 vc_cfg_bits
= &vc_mutant_channel_cfg
;
789 vc_cfg_bits
= &vc_default_channel_cfg
;
791 /* get PMIC/board specific settings */
792 vc
->i2c_slave_addr
= voltdm
->pmic
->i2c_slave_addr
;
793 vc
->volt_reg_addr
= voltdm
->pmic
->volt_reg_addr
;
794 vc
->cmd_reg_addr
= voltdm
->pmic
->cmd_reg_addr
;
796 /* Configure the i2c slave address for this VC */
797 voltdm
->rmw(vc
->smps_sa_mask
,
798 vc
->i2c_slave_addr
<< __ffs(vc
->smps_sa_mask
),
800 vc
->cfg_channel
|= vc_cfg_bits
->sa
;
803 * Configure the PMIC register addresses.
805 voltdm
->rmw(vc
->smps_volra_mask
,
806 vc
->volt_reg_addr
<< __ffs(vc
->smps_volra_mask
),
808 vc
->cfg_channel
|= vc_cfg_bits
->rav
;
810 if (vc
->cmd_reg_addr
) {
811 voltdm
->rmw(vc
->smps_cmdra_mask
,
812 vc
->cmd_reg_addr
<< __ffs(vc
->smps_cmdra_mask
),
814 vc
->cfg_channel
|= vc_cfg_bits
->rac
;
817 if (vc
->cmd_reg_addr
== vc
->volt_reg_addr
)
818 vc
->cfg_channel
|= vc_cfg_bits
->racen
;
820 /* Set up the on, inactive, retention and off voltage */
821 on_vsel
= omap_vc_calc_vsel(voltdm
, voltdm
->vc_param
->on
);
822 onlp_vsel
= omap_vc_calc_vsel(voltdm
, voltdm
->vc_param
->onlp
);
823 ret_vsel
= omap_vc_calc_vsel(voltdm
, voltdm
->vc_param
->ret
);
824 off_vsel
= omap_vc_calc_vsel(voltdm
, voltdm
->vc_param
->off
);
826 val
= ((on_vsel
<< vc
->common
->cmd_on_shift
) |
827 (onlp_vsel
<< vc
->common
->cmd_onlp_shift
) |
828 (ret_vsel
<< vc
->common
->cmd_ret_shift
) |
829 (off_vsel
<< vc
->common
->cmd_off_shift
));
830 voltdm
->write(val
, vc
->cmdval_reg
);
831 vc
->cfg_channel
|= vc_cfg_bits
->cmd
;
833 /* Channel configuration */
834 omap_vc_config_channel(voltdm
);
836 omap_vc_i2c_init(voltdm
);
838 if (cpu_is_omap34xx())
839 omap3_vc_init_channel(voltdm
);
840 else if (cpu_is_omap44xx())
841 omap4_vc_init_channel(voltdm
);