arch/arm/mach-orion5x/ts78xx-setup.c

   1 /*
   2  * arch/arm/mach-orion5x/ts78xx-setup.c
   3  *
   4  * Maintainer: Alexander Clouter <alex@digriz.org.uk>
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/sysfs.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/mv643xx_eth.h>
  18 #include <linux/ata_platform.h>
  19 #include <linux/mtd/rawnand.h>
  20 #include <linux/mtd/partitions.h>
  21 #include <linux/timeriomem-rng.h>
  22 #include <asm/mach-types.h>
  23 #include <asm/mach/arch.h>
  24 #include <asm/mach/map.h>
  25 #include "common.h"
  26 #include "mpp.h"
  27 #include "orion5x.h"
  28 #include "ts78xx-fpga.h"
  29
  30 /*****************************************************************************
  31  * TS-78xx Info
  32  ****************************************************************************/
  33
  34 /*
  35  * FPGA - lives where the PCI bus would be at ORION5X_PCI_MEM_PHYS_BASE
  36  */
  37 #define TS78XX_FPGA_REGS_PHYS_BASE      0xe8000000
  38 #define TS78XX_FPGA_REGS_VIRT_BASE      IOMEM(0xff900000)
  39 #define TS78XX_FPGA_REGS_SIZE           SZ_1M
  40
  41 static struct ts78xx_fpga_data ts78xx_fpga = {
  42         .id             = 0,
  43         .state          = 1,
  44 /*      .supports       = ... - populated by ts78xx_fpga_supports() */
  45 };
  46
  47 /*****************************************************************************
  48  * I/O Address Mapping
  49  ****************************************************************************/
  50 static struct map_desc ts78xx_io_desc[] __initdata = {
  51         {
  52                 .virtual        = (unsigned long)TS78XX_FPGA_REGS_VIRT_BASE,
  53                 .pfn            = __phys_to_pfn(TS78XX_FPGA_REGS_PHYS_BASE),
  54                 .length         = TS78XX_FPGA_REGS_SIZE,
  55                 .type           = MT_DEVICE,
  56         },
  57 };
  58
  59 static void __init ts78xx_map_io(void)
  60 {
  61         orion5x_map_io();
  62         iotable_init(ts78xx_io_desc, ARRAY_SIZE(ts78xx_io_desc));
  63 }
  64
  65 /*****************************************************************************
  66  * Ethernet
  67  ****************************************************************************/
  68 static struct mv643xx_eth_platform_data ts78xx_eth_data = {
  69         .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
  70 };
  71
  72 /*****************************************************************************
  73  * SATA
  74  ****************************************************************************/
  75 static struct mv_sata_platform_data ts78xx_sata_data = {
  76         .n_ports        = 2,
  77 };
  78
  79 /*****************************************************************************
  80  * RTC M48T86 - nicked^Wborrowed from arch/arm/mach-ep93xx/ts72xx.c
  81  ****************************************************************************/
  82 #define TS_RTC_CTRL     (TS78XX_FPGA_REGS_PHYS_BASE + 0x808)
  83 #define TS_RTC_DATA     (TS78XX_FPGA_REGS_PHYS_BASE + 0x80c)
  84
  85 static struct resource ts78xx_ts_rtc_resources[] = {
  86         DEFINE_RES_MEM(TS_RTC_CTRL, 0x01),
  87         DEFINE_RES_MEM(TS_RTC_DATA, 0x01),
  88 };
  89
  90 static struct platform_device ts78xx_ts_rtc_device = {
  91         .name           = "rtc-m48t86",
  92         .id             = -1,
  93         .resource       = ts78xx_ts_rtc_resources,
  94         .num_resources  = ARRAY_SIZE(ts78xx_ts_rtc_resources),
  95 };
  96
  97 static int ts78xx_ts_rtc_load(void)
  98 {
  99         int rc;
 100
 101         if (ts78xx_fpga.supports.ts_rtc.init == 0) {
 102                 rc = platform_device_register(&ts78xx_ts_rtc_device);
 103                 if (!rc)
 104                         ts78xx_fpga.supports.ts_rtc.init = 1;
 105         } else {
 106                 rc = platform_device_add(&ts78xx_ts_rtc_device);
 107         }
 108
 109         if (rc)
 110                 pr_info("RTC could not be registered: %d\n", rc);
 111
 112         return rc;
 113 }
 114
 115 static void ts78xx_ts_rtc_unload(void)
 116 {
 117         platform_device_del(&ts78xx_ts_rtc_device);
 118 }
 119
 120 /*****************************************************************************
 121  * NAND Flash
 122  ****************************************************************************/
 123 #define TS_NAND_CTRL    (TS78XX_FPGA_REGS_VIRT_BASE + 0x800)    /* VIRT */
 124 #define TS_NAND_DATA    (TS78XX_FPGA_REGS_PHYS_BASE + 0x804)    /* PHYS */
 125
 126 /*
 127  * hardware specific access to control-lines
 128  *
 129  * ctrl:
 130  * NAND_NCE: bit 0 -> bit 2
 131  * NAND_CLE: bit 1 -> bit 1
 132  * NAND_ALE: bit 2 -> bit 0
 133  */
 134 static void ts78xx_ts_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
 135                         unsigned int ctrl)
 136 {
 137         struct nand_chip *this = mtd_to_nand(mtd);
 138
 139         if (ctrl & NAND_CTRL_CHANGE) {
 140                 unsigned char bits;
 141
 142                 bits = (ctrl & NAND_NCE) << 2;
 143                 bits |= ctrl & NAND_CLE;
 144                 bits |= (ctrl & NAND_ALE) >> 2;
 145
 146                 writeb((readb(TS_NAND_CTRL) & ~0x7) | bits, TS_NAND_CTRL);
 147         }
 148
 149         if (cmd != NAND_CMD_NONE)
 150                 writeb(cmd, this->IO_ADDR_W);
 151 }
 152
 153 static int ts78xx_ts_nand_dev_ready(struct mtd_info *mtd)
 154 {
 155         return readb(TS_NAND_CTRL) & 0x20;
 156 }
 157
 158 static void ts78xx_ts_nand_write_buf(struct mtd_info *mtd,
 159                         const uint8_t *buf, int len)
 160 {
 161         struct nand_chip *chip = mtd_to_nand(mtd);
 162         void __iomem *io_base = chip->IO_ADDR_W;
 163         unsigned long off = ((unsigned long)buf & 3);
 164         int sz;
 165
 166         if (off) {
 167                 sz = min_t(int, 4 - off, len);
 168                 writesb(io_base, buf, sz);
 169                 buf += sz;
 170                 len -= sz;
 171         }
 172
 173         sz = len >> 2;
 174         if (sz) {
 175                 u32 *buf32 = (u32 *)buf;
 176                 writesl(io_base, buf32, sz);
 177                 buf += sz << 2;
 178                 len -= sz << 2;
 179         }
 180
 181         if (len)
 182                 writesb(io_base, buf, len);
 183 }
 184
 185 static void ts78xx_ts_nand_read_buf(struct mtd_info *mtd,
 186                         uint8_t *buf, int len)
 187 {
 188         struct nand_chip *chip = mtd_to_nand(mtd);
 189         void __iomem *io_base = chip->IO_ADDR_R;
 190         unsigned long off = ((unsigned long)buf & 3);
 191         int sz;
 192
 193         if (off) {
 194                 sz = min_t(int, 4 - off, len);
 195                 readsb(io_base, buf, sz);
 196                 buf += sz;
 197                 len -= sz;
 198         }
 199
 200         sz = len >> 2;
 201         if (sz) {
 202                 u32 *buf32 = (u32 *)buf;
 203                 readsl(io_base, buf32, sz);
 204                 buf += sz << 2;
 205                 len -= sz << 2;
 206         }
 207
 208         if (len)
 209                 readsb(io_base, buf, len);
 210 }
 211
 212 static struct mtd_partition ts78xx_ts_nand_parts[] = {
 213         {
 214                 .name           = "mbr",
 215                 .offset         = 0,
 216                 .size           = SZ_128K,
 217                 .mask_flags     = MTD_WRITEABLE,
 218         }, {
 219                 .name           = "kernel",
 220                 .offset         = MTDPART_OFS_APPEND,
 221                 .size           = SZ_4M,
 222         }, {
 223                 .name           = "initrd",
 224                 .offset         = MTDPART_OFS_APPEND,
 225                 .size           = SZ_4M,
 226         }, {
 227                 .name           = "rootfs",
 228                 .offset         = MTDPART_OFS_APPEND,
 229                 .size           = MTDPART_SIZ_FULL,
 230         }
 231 };
 232
 233 static struct platform_nand_data ts78xx_ts_nand_data = {
 234         .chip   = {
 235                 .nr_chips               = 1,
 236                 .partitions             = ts78xx_ts_nand_parts,
 237                 .nr_partitions          = ARRAY_SIZE(ts78xx_ts_nand_parts),
 238                 .chip_delay             = 15,
 239                 .bbt_options            = NAND_BBT_USE_FLASH,
 240         },
 241         .ctrl   = {
 242                 /*
 243                  * The HW ECC offloading functions, used to give about a 9%
 244                  * performance increase for 'dd if=/dev/mtdblockX' and 5% for
 245                  * nanddump.  This all however was changed by git commit
 246                  * e6cf5df1838c28bb060ac45b5585e48e71bbc740 so now there is
 247                  * no performance advantage to be had so we no longer bother
 248                  */
 249                 .cmd_ctrl               = ts78xx_ts_nand_cmd_ctrl,
 250                 .dev_ready              = ts78xx_ts_nand_dev_ready,
 251                 .write_buf              = ts78xx_ts_nand_write_buf,
 252                 .read_buf               = ts78xx_ts_nand_read_buf,
 253         },
 254 };
 255
 256 static struct resource ts78xx_ts_nand_resources
 257                         = DEFINE_RES_MEM(TS_NAND_DATA, 4);
 258
 259 static struct platform_device ts78xx_ts_nand_device = {
 260         .name           = "gen_nand",
 261         .id             = -1,
 262         .dev            = {
 263                 .platform_data  = &ts78xx_ts_nand_data,
 264         },
 265         .resource       = &ts78xx_ts_nand_resources,
 266         .num_resources  = 1,
 267 };
 268
 269 static int ts78xx_ts_nand_load(void)
 270 {
 271         int rc;
 272
 273         if (ts78xx_fpga.supports.ts_nand.init == 0) {
 274                 rc = platform_device_register(&ts78xx_ts_nand_device);
 275                 if (!rc)
 276                         ts78xx_fpga.supports.ts_nand.init = 1;
 277         } else
 278                 rc = platform_device_add(&ts78xx_ts_nand_device);
 279
 280         if (rc)
 281                 pr_info("NAND could not be registered: %d\n", rc);
 282         return rc;
 283 };
 284
 285 static void ts78xx_ts_nand_unload(void)
 286 {
 287         platform_device_del(&ts78xx_ts_nand_device);
 288 }
 289
 290 /*****************************************************************************
 291  * HW RNG
 292  ****************************************************************************/
 293 #define TS_RNG_DATA     (TS78XX_FPGA_REGS_PHYS_BASE | 0x044)
 294
 295 static struct resource ts78xx_ts_rng_resource
 296                         = DEFINE_RES_MEM(TS_RNG_DATA, 4);
 297
 298 static struct timeriomem_rng_data ts78xx_ts_rng_data = {
 299         .period         = 1000000, /* one second */
 300 };
 301
 302 static struct platform_device ts78xx_ts_rng_device = {
 303         .name           = "timeriomem_rng",
 304         .id             = -1,
 305         .dev            = {
 306                 .platform_data  = &ts78xx_ts_rng_data,
 307         },
 308         .resource       = &ts78xx_ts_rng_resource,
 309         .num_resources  = 1,
 310 };
 311
 312 static int ts78xx_ts_rng_load(void)
 313 {
 314         int rc;
 315
 316         if (ts78xx_fpga.supports.ts_rng.init == 0) {
 317                 rc = platform_device_register(&ts78xx_ts_rng_device);
 318                 if (!rc)
 319                         ts78xx_fpga.supports.ts_rng.init = 1;
 320         } else
 321                 rc = platform_device_add(&ts78xx_ts_rng_device);
 322
 323         if (rc)
 324                 pr_info("RNG could not be registered: %d\n", rc);
 325         return rc;
 326 };
 327
 328 static void ts78xx_ts_rng_unload(void)
 329 {
 330         platform_device_del(&ts78xx_ts_rng_device);
 331 }
 332
 333 /*****************************************************************************
 334  * FPGA 'hotplug' support code
 335  ****************************************************************************/
 336 static void ts78xx_fpga_devices_zero_init(void)
 337 {
 338         ts78xx_fpga.supports.ts_rtc.init = 0;
 339         ts78xx_fpga.supports.ts_nand.init = 0;
 340         ts78xx_fpga.supports.ts_rng.init = 0;
 341 }
 342
 343 static void ts78xx_fpga_supports(void)
 344 {
 345         /* TODO: put this 'table' into ts78xx-fpga.h */
 346         switch (ts78xx_fpga.id) {
 347         case TS7800_REV_1:
 348         case TS7800_REV_2:
 349         case TS7800_REV_3:
 350         case TS7800_REV_4:
 351         case TS7800_REV_5:
 352         case TS7800_REV_6:
 353         case TS7800_REV_7:
 354         case TS7800_REV_8:
 355         case TS7800_REV_9:
 356                 ts78xx_fpga.supports.ts_rtc.present = 1;
 357                 ts78xx_fpga.supports.ts_nand.present = 1;
 358                 ts78xx_fpga.supports.ts_rng.present = 1;
 359                 break;
 360         default:
 361                 /* enable devices if magic matches */
 362                 switch ((ts78xx_fpga.id >> 8) & 0xffffff) {
 363                 case TS7800_FPGA_MAGIC:
 364                         pr_warn("unrecognised FPGA revision 0x%.2x\n",
 365                                 ts78xx_fpga.id & 0xff);
 366                         ts78xx_fpga.supports.ts_rtc.present = 1;
 367                         ts78xx_fpga.supports.ts_nand.present = 1;
 368                         ts78xx_fpga.supports.ts_rng.present = 1;
 369                         break;
 370                 default:
 371                         ts78xx_fpga.supports.ts_rtc.present = 0;
 372                         ts78xx_fpga.supports.ts_nand.present = 0;
 373                         ts78xx_fpga.supports.ts_rng.present = 0;
 374                 }
 375         }
 376 }
 377
 378 static int ts78xx_fpga_load_devices(void)
 379 {
 380         int tmp, ret = 0;
 381
 382         if (ts78xx_fpga.supports.ts_rtc.present == 1) {
 383                 tmp = ts78xx_ts_rtc_load();
 384                 if (tmp)
 385                         ts78xx_fpga.supports.ts_rtc.present = 0;
 386                 ret |= tmp;
 387         }
 388         if (ts78xx_fpga.supports.ts_nand.present == 1) {
 389                 tmp = ts78xx_ts_nand_load();
 390                 if (tmp)
 391                         ts78xx_fpga.supports.ts_nand.present = 0;
 392                 ret |= tmp;
 393         }
 394         if (ts78xx_fpga.supports.ts_rng.present == 1) {
 395                 tmp = ts78xx_ts_rng_load();
 396                 if (tmp)
 397                         ts78xx_fpga.supports.ts_rng.present = 0;
 398                 ret |= tmp;
 399         }
 400
 401         return ret;
 402 }
 403
 404 static int ts78xx_fpga_unload_devices(void)
 405 {
 406         int ret = 0;
 407
 408         if (ts78xx_fpga.supports.ts_rtc.present == 1)
 409                 ts78xx_ts_rtc_unload();
 410         if (ts78xx_fpga.supports.ts_nand.present == 1)
 411                 ts78xx_ts_nand_unload();
 412         if (ts78xx_fpga.supports.ts_rng.present == 1)
 413                 ts78xx_ts_rng_unload();
 414
 415         return ret;
 416 }
 417
 418 static int ts78xx_fpga_load(void)
 419 {
 420         ts78xx_fpga.id = readl(TS78XX_FPGA_REGS_VIRT_BASE);
 421
 422         pr_info("FPGA magic=0x%.6x, rev=0x%.2x\n",
 423                         (ts78xx_fpga.id >> 8) & 0xffffff,
 424                         ts78xx_fpga.id & 0xff);
 425
 426         ts78xx_fpga_supports();
 427
 428         if (ts78xx_fpga_load_devices()) {
 429                 ts78xx_fpga.state = -1;
 430                 return -EBUSY;
 431         }
 432
 433         return 0;
 434 };
 435
 436 static int ts78xx_fpga_unload(void)
 437 {
 438         unsigned int fpga_id;
 439
 440         fpga_id = readl(TS78XX_FPGA_REGS_VIRT_BASE);
 441
 442         /*
 443          * There does not seem to be a feasible way to block access to the GPIO
 444          * pins from userspace (/dev/mem).  This if clause should hopefully warn
 445          * those foolish enough not to follow 'policy' :)
 446          *
 447          * UrJTAG SVN since r1381 can be used to reprogram the FPGA
 448          */
 449         if (ts78xx_fpga.id != fpga_id) {
 450                 pr_err("FPGA magic/rev mismatch\n"
 451                         "TS-78xx FPGA: was 0x%.6x/%.2x but now 0x%.6x/%.2x\n",
 452                         (ts78xx_fpga.id >> 8) & 0xffffff, ts78xx_fpga.id & 0xff,
 453                         (fpga_id >> 8) & 0xffffff, fpga_id & 0xff);
 454                 ts78xx_fpga.state = -1;
 455                 return -EBUSY;
 456         }
 457
 458         if (ts78xx_fpga_unload_devices()) {
 459                 ts78xx_fpga.state = -1;
 460                 return -EBUSY;
 461         }
 462
 463         return 0;
 464 };
 465
 466 static ssize_t ts78xx_fpga_show(struct kobject *kobj,
 467                         struct kobj_attribute *attr, char *buf)
 468 {
 469         if (ts78xx_fpga.state < 0)
 470                 return sprintf(buf, "borked\n");
 471
 472         return sprintf(buf, "%s\n", (ts78xx_fpga.state) ? "online" : "offline");
 473 }
 474
 475 static ssize_t ts78xx_fpga_store(struct kobject *kobj,
 476                         struct kobj_attribute *attr, const char *buf, size_t n)
 477 {
 478         int value, ret;
 479
 480         if (ts78xx_fpga.state < 0) {
 481                 pr_err("FPGA borked, you must powercycle ASAP\n");
 482                 return -EBUSY;
 483         }
 484
 485         if (strncmp(buf, "online", sizeof("online") - 1) == 0)
 486                 value = 1;
 487         else if (strncmp(buf, "offline", sizeof("offline") - 1) == 0)
 488                 value = 0;
 489         else
 490                 return -EINVAL;
 491
 492         if (ts78xx_fpga.state == value)
 493                 return n;
 494
 495         ret = (ts78xx_fpga.state == 0)
 496                 ? ts78xx_fpga_load()
 497                 : ts78xx_fpga_unload();
 498
 499         if (!(ret < 0))
 500                 ts78xx_fpga.state = value;
 501
 502         return n;
 503 }
 504
 505 static struct kobj_attribute ts78xx_fpga_attr =
 506         __ATTR(ts78xx_fpga, 0644, ts78xx_fpga_show, ts78xx_fpga_store);
 507
 508 /*****************************************************************************
 509  * General Setup
 510  ****************************************************************************/
 511 static unsigned int ts78xx_mpp_modes[] __initdata = {
 512         MPP0_UNUSED,
 513         MPP1_GPIO,              /* JTAG Clock */
 514         MPP2_GPIO,              /* JTAG Data In */
 515         MPP3_GPIO,              /* Lat ECP2 256 FPGA - PB2B */
 516         MPP4_GPIO,              /* JTAG Data Out */
 517         MPP5_GPIO,              /* JTAG TMS */
 518         MPP6_GPIO,              /* Lat ECP2 256 FPGA - PB31A_CLK4+ */
 519         MPP7_GPIO,              /* Lat ECP2 256 FPGA - PB22B */
 520         MPP8_UNUSED,
 521         MPP9_UNUSED,
 522         MPP10_UNUSED,
 523         MPP11_UNUSED,
 524         MPP12_UNUSED,
 525         MPP13_UNUSED,
 526         MPP14_UNUSED,
 527         MPP15_UNUSED,
 528         MPP16_UART,
 529         MPP17_UART,
 530         MPP18_UART,
 531         MPP19_UART,
 532         /*
 533          * MPP[20] PCI Clock Out 1
 534          * MPP[21] PCI Clock Out 0
 535          * MPP[22] Unused
 536          * MPP[23] Unused
 537          * MPP[24] Unused
 538          * MPP[25] Unused
 539          */
 540         0,
 541 };
 542
 543 static void __init ts78xx_init(void)
 544 {
 545         int ret;
 546
 547         /*
 548          * Setup basic Orion functions. Need to be called early.
 549          */
 550         orion5x_init();
 551
 552         orion5x_mpp_conf(ts78xx_mpp_modes);
 553
 554         /*
 555          * Configure peripherals.
 556          */
 557         orion5x_ehci0_init();
 558         orion5x_ehci1_init();
 559         orion5x_eth_init(&ts78xx_eth_data);
 560         orion5x_sata_init(&ts78xx_sata_data);
 561         orion5x_uart0_init();
 562         orion5x_uart1_init();
 563         orion5x_xor_init();
 564
 565         /* FPGA init */
 566         ts78xx_fpga_devices_zero_init();
 567         ret = ts78xx_fpga_load();
 568         ret = sysfs_create_file(firmware_kobj, &ts78xx_fpga_attr.attr);
 569         if (ret)
 570                 pr_err("sysfs_create_file failed: %d\n", ret);
 571 }
 572
 573 MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC")
 574         /* Maintainer: Alexander Clouter <alex@digriz.org.uk> */
 575         .atag_offset    = 0x100,
 576         .nr_irqs        = ORION5X_NR_IRQS,
 577         .init_machine   = ts78xx_init,
 578         .map_io         = ts78xx_map_io,
 579         .init_early     = orion5x_init_early,
 580         .init_irq       = orion5x_init_irq,
 581         .init_time      = orion5x_timer_init,
 582         .restart        = orion5x_restart,
 583 MACHINE_END