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mm: fix exec activate_mm vs TLB shootdown and lazy tlb switching race
[linux/fpc-iii.git] / arch / arm / net / bpf_jit_32.c
blobe13aca6e6d4b1e067c449a6c6810212f9980c108
1 /*
2 * Just-In-Time compiler for eBPF filters on 32bit ARM
3 *
4 * Copyright (c) 2017 Shubham Bansal <illusionist.neo@gmail.com>
5 * Copyright (c) 2011 Mircea Gherzan <mgherzan@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; version 2 of the License.
10 */
11
12 #include <linux/bpf.h>
13 #include <linux/bitops.h>
14 #include <linux/compiler.h>
15 #include <linux/errno.h>
16 #include <linux/filter.h>
17 #include <linux/netdevice.h>
18 #include <linux/string.h>
19 #include <linux/slab.h>
20 #include <linux/if_vlan.h>
21
22 #include <asm/cacheflush.h>
23 #include <asm/hwcap.h>
24 #include <asm/opcodes.h>
25
26 #include "bpf_jit_32.h"
27
28 /*
29 * eBPF prog stack layout:
30 *
31 * high
32 * original ARM_SP => +-----+
33 * | | callee saved registers
34 * +-----+ <= (BPF_FP + SCRATCH_SIZE)
35 * | ... | eBPF JIT scratch space
36 * eBPF fp register => +-----+
37 * (BPF_FP) | ... | eBPF prog stack
38 * +-----+
39 * |RSVD | JIT scratchpad
40 * current ARM_SP => +-----+ <= (BPF_FP - STACK_SIZE + SCRATCH_SIZE)
41 * | |
42 * | ... | Function call stack
43 * | |
44 * +-----+
45 * low
46 *
47 * The callee saved registers depends on whether frame pointers are enabled.
48 * With frame pointers (to be compliant with the ABI):
49 *
50 * high
51 * original ARM_SP => +------------------+ \
52 * | pc | |
53 * current ARM_FP => +------------------+ } callee saved registers
54 * |r4-r8,r10,fp,ip,lr| |
55 * +------------------+ /
56 * low
57 *
58 * Without frame pointers:
59 *
60 * high
61 * original ARM_SP => +------------------+
62 * | r4-r8,r10,fp,lr | callee saved registers
63 * current ARM_FP => +------------------+
64 * low
65 *
66 * When popping registers off the stack at the end of a BPF function, we
67 * reference them via the current ARM_FP register.
68 */
69 #define CALLEE_MASK (1 << ARM_R4 | 1 << ARM_R5 | 1 << ARM_R6 | \
70 1 << ARM_R7 | 1 << ARM_R8 | 1 << ARM_R10 | \
71 1 << ARM_FP)
72 #define CALLEE_PUSH_MASK (CALLEE_MASK | 1 << ARM_LR)
73 #define CALLEE_POP_MASK (CALLEE_MASK | 1 << ARM_PC)
74
75 #define STACK_OFFSET(k) (k)
76 #define TMP_REG_1 (MAX_BPF_JIT_REG + 0) /* TEMP Register 1 */
77 #define TMP_REG_2 (MAX_BPF_JIT_REG + 1) /* TEMP Register 2 */
78 #define TCALL_CNT (MAX_BPF_JIT_REG + 2) /* Tail Call Count */
79
80 #define FLAG_IMM_OVERFLOW (1 << 0)
81
82 /*
83 * Map eBPF registers to ARM 32bit registers or stack scratch space.
84 *
85 * 1. First argument is passed using the arm 32bit registers and rest of the
86 * arguments are passed on stack scratch space.
87 * 2. First callee-saved arugument is mapped to arm 32 bit registers and rest
88 * arguments are mapped to scratch space on stack.
89 * 3. We need two 64 bit temp registers to do complex operations on eBPF
90 * registers.
91 *
92 * As the eBPF registers are all 64 bit registers and arm has only 32 bit
93 * registers, we have to map each eBPF registers with two arm 32 bit regs or
94 * scratch memory space and we have to build eBPF 64 bit register from those.
95 *
96 */
97 static const u8 bpf2a32[][2] = {
98 /* return value from in-kernel function, and exit value from eBPF */
99 [BPF_REG_0] = {ARM_R1, ARM_R0},
100 /* arguments from eBPF program to in-kernel function */
101 [BPF_REG_1] = {ARM_R3, ARM_R2},
102 /* Stored on stack scratch space */
103 [BPF_REG_2] = {STACK_OFFSET(0), STACK_OFFSET(4)},
104 [BPF_REG_3] = {STACK_OFFSET(8), STACK_OFFSET(12)},
105 [BPF_REG_4] = {STACK_OFFSET(16), STACK_OFFSET(20)},
106 [BPF_REG_5] = {STACK_OFFSET(24), STACK_OFFSET(28)},
107 /* callee saved registers that in-kernel function will preserve */
108 [BPF_REG_6] = {ARM_R5, ARM_R4},
109 /* Stored on stack scratch space */
110 [BPF_REG_7] = {STACK_OFFSET(32), STACK_OFFSET(36)},
111 [BPF_REG_8] = {STACK_OFFSET(40), STACK_OFFSET(44)},
112 [BPF_REG_9] = {STACK_OFFSET(48), STACK_OFFSET(52)},
113 /* Read only Frame Pointer to access Stack */
114 [BPF_REG_FP] = {STACK_OFFSET(56), STACK_OFFSET(60)},
115 /* Temporary Register for internal BPF JIT, can be used
116 * for constant blindings and others.
117 */
118 [TMP_REG_1] = {ARM_R7, ARM_R6},
119 [TMP_REG_2] = {ARM_R10, ARM_R8},
120 /* Tail call count. Stored on stack scratch space. */
121 [TCALL_CNT] = {STACK_OFFSET(64), STACK_OFFSET(68)},
122 /* temporary register for blinding constants.
123 * Stored on stack scratch space.
124 */
125 [BPF_REG_AX] = {STACK_OFFSET(72), STACK_OFFSET(76)},
126 };
127
128 #define dst_lo dst[1]
129 #define dst_hi dst[0]
130 #define src_lo src[1]
131 #define src_hi src[0]
132
133 /*
134 * JIT Context:
135 *
136 * prog : bpf_prog
137 * idx : index of current last JITed instruction.
138 * prologue_bytes : bytes used in prologue.
139 * epilogue_offset : offset of epilogue starting.
140 * offsets : array of eBPF instruction offsets in
141 * JITed code.
142 * target : final JITed code.
143 * epilogue_bytes : no of bytes used in epilogue.
144 * imm_count : no of immediate counts used for global
145 * variables.
146 * imms : array of global variable addresses.
147 */
148
149 struct jit_ctx {
150 const struct bpf_prog *prog;
151 unsigned int idx;
152 unsigned int prologue_bytes;
153 unsigned int epilogue_offset;
154 u32 flags;
155 u32 *offsets;
156 u32 *target;
157 u32 stack_size;
158 #if __LINUX_ARM_ARCH__ < 7
159 u16 epilogue_bytes;
160 u16 imm_count;
161 u32 *imms;
162 #endif
163 };
164
165 /*
166 * Wrappers which handle both OABI and EABI and assures Thumb2 interworking
167 * (where the assembly routines like __aeabi_uidiv could cause problems).
168 */
169 static u32 jit_udiv32(u32 dividend, u32 divisor)
170 {
171 return dividend / divisor;
172 }
173
174 static u32 jit_mod32(u32 dividend, u32 divisor)
175 {
176 return dividend % divisor;
177 }
178
179 static inline void _emit(int cond, u32 inst, struct jit_ctx *ctx)
180 {
181 inst |= (cond << 28);
182 inst = __opcode_to_mem_arm(inst);
183
184 if (ctx->target != NULL)
185 ctx->target[ctx->idx] = inst;
186
187 ctx->idx++;
188 }
189
190 /*
191 * Emit an instruction that will be executed unconditionally.
192 */
193 static inline void emit(u32 inst, struct jit_ctx *ctx)
194 {
195 _emit(ARM_COND_AL, inst, ctx);
196 }
197
198 /*
199 * Checks if immediate value can be converted to imm12(12 bits) value.
200 */
201 static int16_t imm8m(u32 x)
202 {
203 u32 rot;
204
205 for (rot = 0; rot < 16; rot++)
206 if ((x & ~ror32(0xff, 2 * rot)) == 0)
207 return rol32(x, 2 * rot) | (rot << 8);
208 return -1;
209 }
210
211 /*
212 * Initializes the JIT space with undefined instructions.
213 */
214 static void jit_fill_hole(void *area, unsigned int size)
215 {
216 u32 *ptr;
217 /* We are guaranteed to have aligned memory. */
218 for (ptr = area; size >= sizeof(u32); size -= sizeof(u32))
219 *ptr++ = __opcode_to_mem_arm(ARM_INST_UDF);
220 }
221
222 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
223 /* EABI requires the stack to be aligned to 64-bit boundaries */
224 #define STACK_ALIGNMENT 8
225 #else
226 /* Stack must be aligned to 32-bit boundaries */
227 #define STACK_ALIGNMENT 4
228 #endif
229
230 /* Stack space for BPF_REG_2, BPF_REG_3, BPF_REG_4,
231 * BPF_REG_5, BPF_REG_7, BPF_REG_8, BPF_REG_9,
232 * BPF_REG_FP and Tail call counts.
233 */
234 #define SCRATCH_SIZE 80
235
236 /* total stack size used in JITed code */
237 #define _STACK_SIZE \
238 (ctx->prog->aux->stack_depth + \
239 + SCRATCH_SIZE + \
240 + 4 /* extra for skb_copy_bits buffer */)
241
242 #define STACK_SIZE ALIGN(_STACK_SIZE, STACK_ALIGNMENT)
243
244 /* Get the offset of eBPF REGISTERs stored on scratch space. */
245 #define STACK_VAR(off) (STACK_SIZE-off-4)
246
247 /* Offset of skb_copy_bits buffer */
248 #define SKB_BUFFER STACK_VAR(SCRATCH_SIZE)
249
250 #if __LINUX_ARM_ARCH__ < 7
251
252 static u16 imm_offset(u32 k, struct jit_ctx *ctx)
253 {
254 unsigned int i = 0, offset;
255 u16 imm;
256
257 /* on the "fake" run we just count them (duplicates included) */
258 if (ctx->target == NULL) {
259 ctx->imm_count++;
260 return 0;
261 }
262
263 while ((i < ctx->imm_count) && ctx->imms[i]) {
264 if (ctx->imms[i] == k)
265 break;
266 i++;
267 }
268
269 if (ctx->imms[i] == 0)
270 ctx->imms[i] = k;
271
272 /* constants go just after the epilogue */
273 offset = ctx->offsets[ctx->prog->len - 1] * 4;
274 offset += ctx->prologue_bytes;
275 offset += ctx->epilogue_bytes;
276 offset += i * 4;
277
278 ctx->target[offset / 4] = k;
279
280 /* PC in ARM mode == address of the instruction + 8 */
281 imm = offset - (8 + ctx->idx * 4);
282
283 if (imm & ~0xfff) {
284 /*
285 * literal pool is too far, signal it into flags. we
286 * can only detect it on the second pass unfortunately.
287 */
288 ctx->flags |= FLAG_IMM_OVERFLOW;
289 return 0;
290 }
291
292 return imm;
293 }
294
295 #endif /* __LINUX_ARM_ARCH__ */
296
297 static inline int bpf2a32_offset(int bpf_to, int bpf_from,
298 const struct jit_ctx *ctx) {
299 int to, from;
300
301 if (ctx->target == NULL)
302 return 0;
303 to = ctx->offsets[bpf_to];
304 from = ctx->offsets[bpf_from];
305
306 return to - from - 1;
307 }
308
309 /*
310 * Move an immediate that's not an imm8m to a core register.
311 */
312 static inline void emit_mov_i_no8m(const u8 rd, u32 val, struct jit_ctx *ctx)
313 {
314 #if __LINUX_ARM_ARCH__ < 7
315 emit(ARM_LDR_I(rd, ARM_PC, imm_offset(val, ctx)), ctx);
316 #else
317 emit(ARM_MOVW(rd, val & 0xffff), ctx);
318 if (val > 0xffff)
319 emit(ARM_MOVT(rd, val >> 16), ctx);
320 #endif
321 }
322
323 static inline void emit_mov_i(const u8 rd, u32 val, struct jit_ctx *ctx)
324 {
325 int imm12 = imm8m(val);
326
327 if (imm12 >= 0)
328 emit(ARM_MOV_I(rd, imm12), ctx);
329 else
330 emit_mov_i_no8m(rd, val, ctx);
331 }
332
333 static void emit_bx_r(u8 tgt_reg, struct jit_ctx *ctx)
334 {
335 if (elf_hwcap & HWCAP_THUMB)
336 emit(ARM_BX(tgt_reg), ctx);
337 else
338 emit(ARM_MOV_R(ARM_PC, tgt_reg), ctx);
339 }
340
341 static inline void emit_blx_r(u8 tgt_reg, struct jit_ctx *ctx)
342 {
343 #if __LINUX_ARM_ARCH__ < 5
344 emit(ARM_MOV_R(ARM_LR, ARM_PC), ctx);
345 emit_bx_r(tgt_reg, ctx);
346 #else
347 emit(ARM_BLX_R(tgt_reg), ctx);
348 #endif
349 }
350
351 static inline int epilogue_offset(const struct jit_ctx *ctx)
352 {
353 int to, from;
354 /* No need for 1st dummy run */
355 if (ctx->target == NULL)
356 return 0;
357 to = ctx->epilogue_offset;
358 from = ctx->idx;
359
360 return to - from - 2;
361 }
362
363 static inline void emit_udivmod(u8 rd, u8 rm, u8 rn, struct jit_ctx *ctx, u8 op)
364 {
365 const u8 *tmp = bpf2a32[TMP_REG_1];
366 s32 jmp_offset;
367
368 /* checks if divisor is zero or not. If it is, then
369 * exit directly.
370 */
371 emit(ARM_CMP_I(rn, 0), ctx);
372 _emit(ARM_COND_EQ, ARM_MOV_I(ARM_R0, 0), ctx);
373 jmp_offset = epilogue_offset(ctx);
374 _emit(ARM_COND_EQ, ARM_B(jmp_offset), ctx);
375 #if __LINUX_ARM_ARCH__ == 7
376 if (elf_hwcap & HWCAP_IDIVA) {
377 if (op == BPF_DIV)
378 emit(ARM_UDIV(rd, rm, rn), ctx);
379 else {
380 emit(ARM_UDIV(ARM_IP, rm, rn), ctx);
381 emit(ARM_MLS(rd, rn, ARM_IP, rm), ctx);
382 }
383 return;
384 }
385 #endif
386
387 /*
388 * For BPF_ALU | BPF_DIV | BPF_K instructions
389 * As ARM_R1 and ARM_R0 contains 1st argument of bpf
390 * function, we need to save it on caller side to save
391 * it from getting destroyed within callee.
392 * After the return from the callee, we restore ARM_R0
393 * ARM_R1.
394 */
395 if (rn != ARM_R1) {
396 emit(ARM_MOV_R(tmp[0], ARM_R1), ctx);
397 emit(ARM_MOV_R(ARM_R1, rn), ctx);
398 }
399 if (rm != ARM_R0) {
400 emit(ARM_MOV_R(tmp[1], ARM_R0), ctx);
401 emit(ARM_MOV_R(ARM_R0, rm), ctx);
402 }
403
404 /* Call appropriate function */
405 emit_mov_i(ARM_IP, op == BPF_DIV ?
406 (u32)jit_udiv32 : (u32)jit_mod32, ctx);
407 emit_blx_r(ARM_IP, ctx);
408
409 /* Save return value */
410 if (rd != ARM_R0)
411 emit(ARM_MOV_R(rd, ARM_R0), ctx);
412
413 /* Restore ARM_R0 and ARM_R1 */
414 if (rn != ARM_R1)
415 emit(ARM_MOV_R(ARM_R1, tmp[0]), ctx);
416 if (rm != ARM_R0)
417 emit(ARM_MOV_R(ARM_R0, tmp[1]), ctx);
418 }
419
420 /* Checks whether BPF register is on scratch stack space or not. */
421 static inline bool is_on_stack(u8 bpf_reg)
422 {
423 static u8 stack_regs[] = {BPF_REG_AX, BPF_REG_3, BPF_REG_4, BPF_REG_5,
424 BPF_REG_7, BPF_REG_8, BPF_REG_9, TCALL_CNT,
425 BPF_REG_2, BPF_REG_FP};
426 int i, reg_len = sizeof(stack_regs);
427
428 for (i = 0 ; i < reg_len ; i++) {
429 if (bpf_reg == stack_regs[i])
430 return true;
431 }
432 return false;
433 }
434
435 static inline void emit_a32_mov_i(const u8 dst, const u32 val,
436 bool dstk, struct jit_ctx *ctx)
437 {
438 const u8 *tmp = bpf2a32[TMP_REG_1];
439
440 if (dstk) {
441 emit_mov_i(tmp[1], val, ctx);
442 emit(ARM_STR_I(tmp[1], ARM_SP, STACK_VAR(dst)), ctx);
443 } else {
444 emit_mov_i(dst, val, ctx);
445 }
446 }
447
448 /* Sign extended move */
449 static inline void emit_a32_mov_i64(const bool is64, const u8 dst[],
450 const u32 val, bool dstk,
451 struct jit_ctx *ctx) {
452 u32 hi = 0;
453
454 if (is64 && (val & (1<<31)))
455 hi = (u32)~0;
456 emit_a32_mov_i(dst_lo, val, dstk, ctx);
457 emit_a32_mov_i(dst_hi, hi, dstk, ctx);
458 }
459
460 static inline void emit_a32_add_r(const u8 dst, const u8 src,
461 const bool is64, const bool hi,
462 struct jit_ctx *ctx) {
463 /* 64 bit :
464 * adds dst_lo, dst_lo, src_lo
465 * adc dst_hi, dst_hi, src_hi
466 * 32 bit :
467 * add dst_lo, dst_lo, src_lo
468 */
469 if (!hi && is64)
470 emit(ARM_ADDS_R(dst, dst, src), ctx);
471 else if (hi && is64)
472 emit(ARM_ADC_R(dst, dst, src), ctx);
473 else
474 emit(ARM_ADD_R(dst, dst, src), ctx);
475 }
476
477 static inline void emit_a32_sub_r(const u8 dst, const u8 src,
478 const bool is64, const bool hi,
479 struct jit_ctx *ctx) {
480 /* 64 bit :
481 * subs dst_lo, dst_lo, src_lo
482 * sbc dst_hi, dst_hi, src_hi
483 * 32 bit :
484 * sub dst_lo, dst_lo, src_lo
485 */
486 if (!hi && is64)
487 emit(ARM_SUBS_R(dst, dst, src), ctx);
488 else if (hi && is64)
489 emit(ARM_SBC_R(dst, dst, src), ctx);
490 else
491 emit(ARM_SUB_R(dst, dst, src), ctx);
492 }
493
494 static inline void emit_alu_r(const u8 dst, const u8 src, const bool is64,
495 const bool hi, const u8 op, struct jit_ctx *ctx){
496 switch (BPF_OP(op)) {
497 /* dst = dst + src */
498 case BPF_ADD:
499 emit_a32_add_r(dst, src, is64, hi, ctx);
500 break;
501 /* dst = dst - src */
502 case BPF_SUB:
503 emit_a32_sub_r(dst, src, is64, hi, ctx);
504 break;
505 /* dst = dst | src */
506 case BPF_OR:
507 emit(ARM_ORR_R(dst, dst, src), ctx);
508 break;
509 /* dst = dst & src */
510 case BPF_AND:
511 emit(ARM_AND_R(dst, dst, src), ctx);
512 break;
513 /* dst = dst ^ src */
514 case BPF_XOR:
515 emit(ARM_EOR_R(dst, dst, src), ctx);
516 break;
517 /* dst = dst * src */
518 case BPF_MUL:
519 emit(ARM_MUL(dst, dst, src), ctx);
520 break;
521 /* dst = dst << src */
522 case BPF_LSH:
523 emit(ARM_LSL_R(dst, dst, src), ctx);
524 break;
525 /* dst = dst >> src */
526 case BPF_RSH:
527 emit(ARM_LSR_R(dst, dst, src), ctx);
528 break;
529 /* dst = dst >> src (signed)*/
530 case BPF_ARSH:
531 emit(ARM_MOV_SR(dst, dst, SRTYPE_ASR, src), ctx);
532 break;
533 }
534 }
535
536 /* ALU operation (32 bit)
537 * dst = dst (op) src
538 */
539 static inline void emit_a32_alu_r(const u8 dst, const u8 src,
540 bool dstk, bool sstk,
541 struct jit_ctx *ctx, const bool is64,
542 const bool hi, const u8 op) {
543 const u8 *tmp = bpf2a32[TMP_REG_1];
544 u8 rn = sstk ? tmp[1] : src;
545
546 if (sstk)
547 emit(ARM_LDR_I(rn, ARM_SP, STACK_VAR(src)), ctx);
548
549 /* ALU operation */
550 if (dstk) {
551 emit(ARM_LDR_I(tmp[0], ARM_SP, STACK_VAR(dst)), ctx);
552 emit_alu_r(tmp[0], rn, is64, hi, op, ctx);
553 emit(ARM_STR_I(tmp[0], ARM_SP, STACK_VAR(dst)), ctx);
554 } else {
555 emit_alu_r(dst, rn, is64, hi, op, ctx);
556 }
557 }
558
559 /* ALU operation (64 bit) */
560 static inline void emit_a32_alu_r64(const bool is64, const u8 dst[],
561 const u8 src[], bool dstk,
562 bool sstk, struct jit_ctx *ctx,
563 const u8 op) {
564 emit_a32_alu_r(dst_lo, src_lo, dstk, sstk, ctx, is64, false, op);
565 if (is64)
566 emit_a32_alu_r(dst_hi, src_hi, dstk, sstk, ctx, is64, true, op);
567 else
568 emit_a32_mov_i(dst_hi, 0, dstk, ctx);
569 }
570
571 /* dst = imm (4 bytes)*/
572 static inline void emit_a32_mov_r(const u8 dst, const u8 src,
573 bool dstk, bool sstk,
574 struct jit_ctx *ctx) {
575 const u8 *tmp = bpf2a32[TMP_REG_1];
576 u8 rt = sstk ? tmp[0] : src;
577
578 if (sstk)
579 emit(ARM_LDR_I(tmp[0], ARM_SP, STACK_VAR(src)), ctx);
580 if (dstk)
581 emit(ARM_STR_I(rt, ARM_SP, STACK_VAR(dst)), ctx);
582 else
583 emit(ARM_MOV_R(dst, rt), ctx);
584 }
585
586 /* dst = src */
587 static inline void emit_a32_mov_r64(const bool is64, const u8 dst[],
588 const u8 src[], bool dstk,
589 bool sstk, struct jit_ctx *ctx) {
590 emit_a32_mov_r(dst_lo, src_lo, dstk, sstk, ctx);
591 if (is64) {
592 /* complete 8 byte move */
593 emit_a32_mov_r(dst_hi, src_hi, dstk, sstk, ctx);
594 } else {
595 /* Zero out high 4 bytes */
596 emit_a32_mov_i(dst_hi, 0, dstk, ctx);
597 }
598 }
599
600 /* Shift operations */
601 static inline void emit_a32_alu_i(const u8 dst, const u32 val, bool dstk,
602 struct jit_ctx *ctx, const u8 op) {
603 const u8 *tmp = bpf2a32[TMP_REG_1];
604 u8 rd = dstk ? tmp[0] : dst;
605
606 if (dstk)
607 emit(ARM_LDR_I(rd, ARM_SP, STACK_VAR(dst)), ctx);
608
609 /* Do shift operation */
610 switch (op) {
611 case BPF_LSH:
612 emit(ARM_LSL_I(rd, rd, val), ctx);
613 break;
614 case BPF_RSH:
615 emit(ARM_LSR_I(rd, rd, val), ctx);
616 break;
617 case BPF_NEG:
618 emit(ARM_RSB_I(rd, rd, val), ctx);
619 break;
620 }
621
622 if (dstk)
623 emit(ARM_STR_I(rd, ARM_SP, STACK_VAR(dst)), ctx);
624 }
625
626 /* dst = ~dst (64 bit) */
627 static inline void emit_a32_neg64(const u8 dst[], bool dstk,
628 struct jit_ctx *ctx){
629 const u8 *tmp = bpf2a32[TMP_REG_1];
630 u8 rd = dstk ? tmp[1] : dst[1];
631 u8 rm = dstk ? tmp[0] : dst[0];
632
633 /* Setup Operand */
634 if (dstk) {
635 emit(ARM_LDR_I(rd, ARM_SP, STACK_VAR(dst_lo)), ctx);
636 emit(ARM_LDR_I(rm, ARM_SP, STACK_VAR(dst_hi)), ctx);
637 }
638
639 /* Do Negate Operation */
640 emit(ARM_RSBS_I(rd, rd, 0), ctx);
641 emit(ARM_RSC_I(rm, rm, 0), ctx);
642
643 if (dstk) {
644 emit(ARM_STR_I(rd, ARM_SP, STACK_VAR(dst_lo)), ctx);
645 emit(ARM_STR_I(rm, ARM_SP, STACK_VAR(dst_hi)), ctx);
646 }
647 }
648
649 /* dst = dst << src */
650 static inline void emit_a32_lsh_r64(const u8 dst[], const u8 src[], bool dstk,
651 bool sstk, struct jit_ctx *ctx) {
652 const u8 *tmp = bpf2a32[TMP_REG_1];
653 const u8 *tmp2 = bpf2a32[TMP_REG_2];
654
655 /* Setup Operands */
656 u8 rt = sstk ? tmp2[1] : src_lo;
657 u8 rd = dstk ? tmp[1] : dst_lo;
658 u8 rm = dstk ? tmp[0] : dst_hi;
659
660 if (sstk)
661 emit(ARM_LDR_I(rt, ARM_SP, STACK_VAR(src_lo)), ctx);
662 if (dstk) {
663 emit(ARM_LDR_I(rd, ARM_SP, STACK_VAR(dst_lo)), ctx);
664 emit(ARM_LDR_I(rm, ARM_SP, STACK_VAR(dst_hi)), ctx);
665 }
666
667 /* Do LSH operation */
668 emit(ARM_SUB_I(ARM_IP, rt, 32), ctx);
669 emit(ARM_RSB_I(tmp2[0], rt, 32), ctx);
670 emit(ARM_MOV_SR(ARM_LR, rm, SRTYPE_ASL, rt), ctx);
671 emit(ARM_ORR_SR(ARM_LR, ARM_LR, rd, SRTYPE_ASL, ARM_IP), ctx);
672 emit(ARM_ORR_SR(ARM_IP, ARM_LR, rd, SRTYPE_LSR, tmp2[0]), ctx);
673 emit(ARM_MOV_SR(ARM_LR, rd, SRTYPE_ASL, rt), ctx);
674
675 if (dstk) {
676 emit(ARM_STR_I(ARM_LR, ARM_SP, STACK_VAR(dst_lo)), ctx);
677 emit(ARM_STR_I(ARM_IP, ARM_SP, STACK_VAR(dst_hi)), ctx);
678 } else {
679 emit(ARM_MOV_R(rd, ARM_LR), ctx);
680 emit(ARM_MOV_R(rm, ARM_IP), ctx);
681 }
682 }
683
684 /* dst = dst >> src (signed)*/
685 static inline void emit_a32_arsh_r64(const u8 dst[], const u8 src[], bool dstk,
686 bool sstk, struct jit_ctx *ctx) {
687 const u8 *tmp = bpf2a32[TMP_REG_1];
688 const u8 *tmp2 = bpf2a32[TMP_REG_2];
689 /* Setup Operands */
690 u8 rt = sstk ? tmp2[1] : src_lo;
691 u8 rd = dstk ? tmp[1] : dst_lo;
692 u8 rm = dstk ? tmp[0] : dst_hi;
693
694 if (sstk)
695 emit(ARM_LDR_I(rt, ARM_SP, STACK_VAR(src_lo)), ctx);
696 if (dstk) {
697 emit(ARM_LDR_I(rd, ARM_SP, STACK_VAR(dst_lo)), ctx);
698 emit(ARM_LDR_I(rm, ARM_SP, STACK_VAR(dst_hi)), ctx);
699 }
700
701 /* Do the ARSH operation */
702 emit(ARM_RSB_I(ARM_IP, rt, 32), ctx);
703 emit(ARM_SUBS_I(tmp2[0], rt, 32), ctx);
704 emit(ARM_MOV_SR(ARM_LR, rd, SRTYPE_LSR, rt), ctx);
705 emit(ARM_ORR_SR(ARM_LR, ARM_LR, rm, SRTYPE_ASL, ARM_IP), ctx);
706 _emit(ARM_COND_MI, ARM_B(0), ctx);
707 emit(ARM_ORR_SR(ARM_LR, ARM_LR, rm, SRTYPE_ASR, tmp2[0]), ctx);
708 emit(ARM_MOV_SR(ARM_IP, rm, SRTYPE_ASR, rt), ctx);
709 if (dstk) {
710 emit(ARM_STR_I(ARM_LR, ARM_SP, STACK_VAR(dst_lo)), ctx);
711 emit(ARM_STR_I(ARM_IP, ARM_SP, STACK_VAR(dst_hi)), ctx);
712 } else {
713 emit(ARM_MOV_R(rd, ARM_LR), ctx);
714 emit(ARM_MOV_R(rm, ARM_IP), ctx);
715 }
716 }
717
718 /* dst = dst >> src */
719 static inline void emit_a32_rsh_r64(const u8 dst[], const u8 src[], bool dstk,
720 bool sstk, struct jit_ctx *ctx) {
721 const u8 *tmp = bpf2a32[TMP_REG_1];
722 const u8 *tmp2 = bpf2a32[TMP_REG_2];
723 /* Setup Operands */
724 u8 rt = sstk ? tmp2[1] : src_lo;
725 u8 rd = dstk ? tmp[1] : dst_lo;
726 u8 rm = dstk ? tmp[0] : dst_hi;
727
728 if (sstk)
729 emit(ARM_LDR_I(rt, ARM_SP, STACK_VAR(src_lo)), ctx);
730 if (dstk) {
731 emit(ARM_LDR_I(rd, ARM_SP, STACK_VAR(dst_lo)), ctx);
732 emit(ARM_LDR_I(rm, ARM_SP, STACK_VAR(dst_hi)), ctx);
733 }
734
735 /* Do RSH operation */
736 emit(ARM_RSB_I(ARM_IP, rt, 32), ctx);
737 emit(ARM_SUBS_I(tmp2[0], rt, 32), ctx);
738 emit(ARM_MOV_SR(ARM_LR, rd, SRTYPE_LSR, rt), ctx);
739 emit(ARM_ORR_SR(ARM_LR, ARM_LR, rm, SRTYPE_ASL, ARM_IP), ctx);
740 emit(ARM_ORR_SR(ARM_LR, ARM_LR, rm, SRTYPE_LSR, tmp2[0]), ctx);
741 emit(ARM_MOV_SR(ARM_IP, rm, SRTYPE_LSR, rt), ctx);
742 if (dstk) {
743 emit(ARM_STR_I(ARM_LR, ARM_SP, STACK_VAR(dst_lo)), ctx);
744 emit(ARM_STR_I(ARM_IP, ARM_SP, STACK_VAR(dst_hi)), ctx);
745 } else {
746 emit(ARM_MOV_R(rd, ARM_LR), ctx);
747 emit(ARM_MOV_R(rm, ARM_IP), ctx);
748 }
749 }
750
751 /* dst = dst << val */
752 static inline void emit_a32_lsh_i64(const u8 dst[], bool dstk,
753 const u32 val, struct jit_ctx *ctx){
754 const u8 *tmp = bpf2a32[TMP_REG_1];
755 const u8 *tmp2 = bpf2a32[TMP_REG_2];
756 /* Setup operands */
757 u8 rd = dstk ? tmp[1] : dst_lo;
758 u8 rm = dstk ? tmp[0] : dst_hi;
759
760 if (dstk) {
761 emit(ARM_LDR_I(rd, ARM_SP, STACK_VAR(dst_lo)), ctx);
762 emit(ARM_LDR_I(rm, ARM_SP, STACK_VAR(dst_hi)), ctx);
763 }
764
765 /* Do LSH operation */
766 if (val < 32) {
767 emit(ARM_MOV_SI(tmp2[0], rm, SRTYPE_ASL, val), ctx);
768 emit(ARM_ORR_SI(rm, tmp2[0], rd, SRTYPE_LSR, 32 - val), ctx);
769 emit(ARM_MOV_SI(rd, rd, SRTYPE_ASL, val), ctx);
770 } else {
771 if (val == 32)
772 emit(ARM_MOV_R(rm, rd), ctx);
773 else
774 emit(ARM_MOV_SI(rm, rd, SRTYPE_ASL, val - 32), ctx);
775 emit(ARM_EOR_R(rd, rd, rd), ctx);
776 }
777
778 if (dstk) {
779 emit(ARM_STR_I(rd, ARM_SP, STACK_VAR(dst_lo)), ctx);
780 emit(ARM_STR_I(rm, ARM_SP, STACK_VAR(dst_hi)), ctx);
781 }
782 }
783
784 /* dst = dst >> val */
785 static inline void emit_a32_rsh_i64(const u8 dst[], bool dstk,
786 const u32 val, struct jit_ctx *ctx) {
787 const u8 *tmp = bpf2a32[TMP_REG_1];
788 const u8 *tmp2 = bpf2a32[TMP_REG_2];
789 /* Setup operands */
790 u8 rd = dstk ? tmp[1] : dst_lo;
791 u8 rm = dstk ? tmp[0] : dst_hi;
792
793 if (dstk) {
794 emit(ARM_LDR_I(rd, ARM_SP, STACK_VAR(dst_lo)), ctx);
795 emit(ARM_LDR_I(rm, ARM_SP, STACK_VAR(dst_hi)), ctx);
796 }
797
798 /* Do LSR operation */
799 if (val == 0) {
800 /* An immediate value of 0 encodes a shift amount of 32
801 * for LSR. To shift by 0, don't do anything.
802 */
803 } else if (val < 32) {
804 emit(ARM_MOV_SI(tmp2[1], rd, SRTYPE_LSR, val), ctx);
805 emit(ARM_ORR_SI(rd, tmp2[1], rm, SRTYPE_ASL, 32 - val), ctx);
806 emit(ARM_MOV_SI(rm, rm, SRTYPE_LSR, val), ctx);
807 } else if (val == 32) {
808 emit(ARM_MOV_R(rd, rm), ctx);
809 emit(ARM_MOV_I(rm, 0), ctx);
810 } else {
811 emit(ARM_MOV_SI(rd, rm, SRTYPE_LSR, val - 32), ctx);
812 emit(ARM_MOV_I(rm, 0), ctx);
813 }
814
815 if (dstk) {
816 emit(ARM_STR_I(rd, ARM_SP, STACK_VAR(dst_lo)), ctx);
817 emit(ARM_STR_I(rm, ARM_SP, STACK_VAR(dst_hi)), ctx);
818 }
819 }
820
821 /* dst = dst >> val (signed) */
822 static inline void emit_a32_arsh_i64(const u8 dst[], bool dstk,
823 const u32 val, struct jit_ctx *ctx){
824 const u8 *tmp = bpf2a32[TMP_REG_1];
825 const u8 *tmp2 = bpf2a32[TMP_REG_2];
826 /* Setup operands */
827 u8 rd = dstk ? tmp[1] : dst_lo;
828 u8 rm = dstk ? tmp[0] : dst_hi;
829
830 if (dstk) {
831 emit(ARM_LDR_I(rd, ARM_SP, STACK_VAR(dst_lo)), ctx);
832 emit(ARM_LDR_I(rm, ARM_SP, STACK_VAR(dst_hi)), ctx);
833 }
834
835 /* Do ARSH operation */
836 if (val == 0) {
837 /* An immediate value of 0 encodes a shift amount of 32
838 * for ASR. To shift by 0, don't do anything.
839 */
840 } else if (val < 32) {
841 emit(ARM_MOV_SI(tmp2[1], rd, SRTYPE_LSR, val), ctx);
842 emit(ARM_ORR_SI(rd, tmp2[1], rm, SRTYPE_ASL, 32 - val), ctx);
843 emit(ARM_MOV_SI(rm, rm, SRTYPE_ASR, val), ctx);
844 } else if (val == 32) {
845 emit(ARM_MOV_R(rd, rm), ctx);
846 emit(ARM_MOV_SI(rm, rm, SRTYPE_ASR, 31), ctx);
847 } else {
848 emit(ARM_MOV_SI(rd, rm, SRTYPE_ASR, val - 32), ctx);
849 emit(ARM_MOV_SI(rm, rm, SRTYPE_ASR, 31), ctx);
850 }
851
852 if (dstk) {
853 emit(ARM_STR_I(rd, ARM_SP, STACK_VAR(dst_lo)), ctx);
854 emit(ARM_STR_I(rm, ARM_SP, STACK_VAR(dst_hi)), ctx);
855 }
856 }
857
858 static inline void emit_a32_mul_r64(const u8 dst[], const u8 src[], bool dstk,
859 bool sstk, struct jit_ctx *ctx) {
860 const u8 *tmp = bpf2a32[TMP_REG_1];
861 const u8 *tmp2 = bpf2a32[TMP_REG_2];
862 /* Setup operands for multiplication */
863 u8 rd = dstk ? tmp[1] : dst_lo;
864 u8 rm = dstk ? tmp[0] : dst_hi;
865 u8 rt = sstk ? tmp2[1] : src_lo;
866 u8 rn = sstk ? tmp2[0] : src_hi;
867
868 if (dstk) {
869 emit(ARM_LDR_I(rd, ARM_SP, STACK_VAR(dst_lo)), ctx);
870 emit(ARM_LDR_I(rm, ARM_SP, STACK_VAR(dst_hi)), ctx);
871 }
872 if (sstk) {
873 emit(ARM_LDR_I(rt, ARM_SP, STACK_VAR(src_lo)), ctx);
874 emit(ARM_LDR_I(rn, ARM_SP, STACK_VAR(src_hi)), ctx);
875 }
876
877 /* Do Multiplication */
878 emit(ARM_MUL(ARM_IP, rd, rn), ctx);
879 emit(ARM_MUL(ARM_LR, rm, rt), ctx);
880 emit(ARM_ADD_R(ARM_LR, ARM_IP, ARM_LR), ctx);
881
882 emit(ARM_UMULL(ARM_IP, rm, rd, rt), ctx);
883 emit(ARM_ADD_R(rm, ARM_LR, rm), ctx);
884 if (dstk) {
885 emit(ARM_STR_I(ARM_IP, ARM_SP, STACK_VAR(dst_lo)), ctx);
886 emit(ARM_STR_I(rm, ARM_SP, STACK_VAR(dst_hi)), ctx);
887 } else {
888 emit(ARM_MOV_R(rd, ARM_IP), ctx);
889 }
890 }
891
892 /* *(size *)(dst + off) = src */
893 static inline void emit_str_r(const u8 dst, const u8 src, bool dstk,
894 const s32 off, struct jit_ctx *ctx, const u8 sz){
895 const u8 *tmp = bpf2a32[TMP_REG_1];
896 u8 rd = dstk ? tmp[1] : dst;
897
898 if (dstk)
899 emit(ARM_LDR_I(rd, ARM_SP, STACK_VAR(dst)), ctx);
900 if (off) {
901 emit_a32_mov_i(tmp[0], off, false, ctx);
902 emit(ARM_ADD_R(tmp[0], rd, tmp[0]), ctx);
903 rd = tmp[0];
904 }
905 switch (sz) {
906 case BPF_W:
907 /* Store a Word */
908 emit(ARM_STR_I(src, rd, 0), ctx);
909 break;
910 case BPF_H:
911 /* Store a HalfWord */
912 emit(ARM_STRH_I(src, rd, 0), ctx);
913 break;
914 case BPF_B:
915 /* Store a Byte */
916 emit(ARM_STRB_I(src, rd, 0), ctx);
917 break;
918 }
919 }
920
921 /* dst = *(size*)(src + off) */
922 static inline void emit_ldx_r(const u8 dst[], const u8 src, bool dstk,
923 s32 off, struct jit_ctx *ctx, const u8 sz){
924 const u8 *tmp = bpf2a32[TMP_REG_2];
925 const u8 *rd = dstk ? tmp : dst;
926 u8 rm = src;
927 s32 off_max;
928
929 if (sz == BPF_H)
930 off_max = 0xff;
931 else
932 off_max = 0xfff;
933
934 if (off < 0 || off > off_max) {
935 emit_a32_mov_i(tmp[0], off, false, ctx);
936 emit(ARM_ADD_R(tmp[0], tmp[0], src), ctx);
937 rm = tmp[0];
938 off = 0;
939 } else if (rd[1] == rm) {
940 emit(ARM_MOV_R(tmp[0], rm), ctx);
941 rm = tmp[0];
942 }
943 switch (sz) {
944 case BPF_B:
945 /* Load a Byte */
946 emit(ARM_LDRB_I(rd[1], rm, off), ctx);
947 emit_a32_mov_i(dst[0], 0, dstk, ctx);
948 break;
949 case BPF_H:
950 /* Load a HalfWord */
951 emit(ARM_LDRH_I(rd[1], rm, off), ctx);
952 emit_a32_mov_i(dst[0], 0, dstk, ctx);
953 break;
954 case BPF_W:
955 /* Load a Word */
956 emit(ARM_LDR_I(rd[1], rm, off), ctx);
957 emit_a32_mov_i(dst[0], 0, dstk, ctx);
958 break;
959 case BPF_DW:
960 /* Load a Double Word */
961 emit(ARM_LDR_I(rd[1], rm, off), ctx);
962 emit(ARM_LDR_I(rd[0], rm, off + 4), ctx);
963 break;
964 }
965 if (dstk)
966 emit(ARM_STR_I(rd[1], ARM_SP, STACK_VAR(dst[1])), ctx);
967 if (dstk && sz == BPF_DW)
968 emit(ARM_STR_I(rd[0], ARM_SP, STACK_VAR(dst[0])), ctx);
969 }
970
971 /* Arithmatic Operation */
972 static inline void emit_ar_r(const u8 rd, const u8 rt, const u8 rm,
973 const u8 rn, struct jit_ctx *ctx, u8 op) {
974 switch (op) {
975 case BPF_JSET:
976 emit(ARM_AND_R(ARM_IP, rt, rn), ctx);
977 emit(ARM_AND_R(ARM_LR, rd, rm), ctx);
978 emit(ARM_ORRS_R(ARM_IP, ARM_LR, ARM_IP), ctx);
979 break;
980 case BPF_JEQ:
981 case BPF_JNE:
982 case BPF_JGT:
983 case BPF_JGE:
984 case BPF_JLE:
985 case BPF_JLT:
986 emit(ARM_CMP_R(rd, rm), ctx);
987 _emit(ARM_COND_EQ, ARM_CMP_R(rt, rn), ctx);
988 break;
989 case BPF_JSLE:
990 case BPF_JSGT:
991 emit(ARM_CMP_R(rn, rt), ctx);
992 emit(ARM_SBCS_R(ARM_IP, rm, rd), ctx);
993 break;
994 case BPF_JSLT:
995 case BPF_JSGE:
996 emit(ARM_CMP_R(rt, rn), ctx);
997 emit(ARM_SBCS_R(ARM_IP, rd, rm), ctx);
998 break;
999 }
1000 }
1001
1002 static int out_offset = -1; /* initialized on the first pass of build_body() */
1003 static int emit_bpf_tail_call(struct jit_ctx *ctx)
1004 {
1005
1006 /* bpf_tail_call(void *prog_ctx, struct bpf_array *array, u64 index) */
1007 const u8 *r2 = bpf2a32[BPF_REG_2];
1008 const u8 *r3 = bpf2a32[BPF_REG_3];
1009 const u8 *tmp = bpf2a32[TMP_REG_1];
1010 const u8 *tmp2 = bpf2a32[TMP_REG_2];
1011 const u8 *tcc = bpf2a32[TCALL_CNT];
1012 const int idx0 = ctx->idx;
1013 #define cur_offset (ctx->idx - idx0)
1014 #define jmp_offset (out_offset - (cur_offset) - 2)
1015 u32 off, lo, hi;
1016
1017 /* if (index >= array->map.max_entries)
1018 * goto out;
1019 */
1020 off = offsetof(struct bpf_array, map.max_entries);
1021 /* array->map.max_entries */
1022 emit_a32_mov_i(tmp[1], off, false, ctx);
1023 emit(ARM_LDR_I(tmp2[1], ARM_SP, STACK_VAR(r2[1])), ctx);
1024 emit(ARM_LDR_R(tmp[1], tmp2[1], tmp[1]), ctx);
1025 /* index is 32-bit for arrays */
1026 emit(ARM_LDR_I(tmp2[1], ARM_SP, STACK_VAR(r3[1])), ctx);
1027 /* index >= array->map.max_entries */
1028 emit(ARM_CMP_R(tmp2[1], tmp[1]), ctx);
1029 _emit(ARM_COND_CS, ARM_B(jmp_offset), ctx);
1030
1031 /* if (tail_call_cnt > MAX_TAIL_CALL_CNT)
1032 * goto out;
1033 * tail_call_cnt++;
1034 */
1035 lo = (u32)MAX_TAIL_CALL_CNT;
1036 hi = (u32)((u64)MAX_TAIL_CALL_CNT >> 32);
1037 emit(ARM_LDR_I(tmp[1], ARM_SP, STACK_VAR(tcc[1])), ctx);
1038 emit(ARM_LDR_I(tmp[0], ARM_SP, STACK_VAR(tcc[0])), ctx);
1039 emit(ARM_CMP_I(tmp[0], hi), ctx);
1040 _emit(ARM_COND_EQ, ARM_CMP_I(tmp[1], lo), ctx);
1041 _emit(ARM_COND_HI, ARM_B(jmp_offset), ctx);
1042 emit(ARM_ADDS_I(tmp[1], tmp[1], 1), ctx);
1043 emit(ARM_ADC_I(tmp[0], tmp[0], 0), ctx);
1044 emit(ARM_STR_I(tmp[1], ARM_SP, STACK_VAR(tcc[1])), ctx);
1045 emit(ARM_STR_I(tmp[0], ARM_SP, STACK_VAR(tcc[0])), ctx);
1046
1047 /* prog = array->ptrs[index]
1048 * if (prog == NULL)
1049 * goto out;
1050 */
1051 off = offsetof(struct bpf_array, ptrs);
1052 emit_a32_mov_i(tmp[1], off, false, ctx);
1053 emit(ARM_LDR_I(tmp2[1], ARM_SP, STACK_VAR(r2[1])), ctx);
1054 emit(ARM_ADD_R(tmp[1], tmp2[1], tmp[1]), ctx);
1055 emit(ARM_LDR_I(tmp2[1], ARM_SP, STACK_VAR(r3[1])), ctx);
1056 emit(ARM_MOV_SI(tmp[0], tmp2[1], SRTYPE_ASL, 2), ctx);
1057 emit(ARM_LDR_R(tmp[1], tmp[1], tmp[0]), ctx);
1058 emit(ARM_CMP_I(tmp[1], 0), ctx);
1059 _emit(ARM_COND_EQ, ARM_B(jmp_offset), ctx);
1060
1061 /* goto *(prog->bpf_func + prologue_size); */
1062 off = offsetof(struct bpf_prog, bpf_func);
1063 emit_a32_mov_i(tmp2[1], off, false, ctx);
1064 emit(ARM_LDR_R(tmp[1], tmp[1], tmp2[1]), ctx);
1065 emit(ARM_ADD_I(tmp[1], tmp[1], ctx->prologue_bytes), ctx);
1066 emit_bx_r(tmp[1], ctx);
1067
1068 /* out: */
1069 if (out_offset == -1)
1070 out_offset = cur_offset;
1071 if (cur_offset != out_offset) {
1072 pr_err_once("tail_call out_offset = %d, expected %d!\n",
1073 cur_offset, out_offset);
1074 return -1;
1075 }
1076 return 0;
1077 #undef cur_offset
1078 #undef jmp_offset
1079 }
1080
1081 /* 0xabcd => 0xcdab */
1082 static inline void emit_rev16(const u8 rd, const u8 rn, struct jit_ctx *ctx)
1083 {
1084 #if __LINUX_ARM_ARCH__ < 6
1085 const u8 *tmp2 = bpf2a32[TMP_REG_2];
1086
1087 emit(ARM_AND_I(tmp2[1], rn, 0xff), ctx);
1088 emit(ARM_MOV_SI(tmp2[0], rn, SRTYPE_LSR, 8), ctx);
1089 emit(ARM_AND_I(tmp2[0], tmp2[0], 0xff), ctx);
1090 emit(ARM_ORR_SI(rd, tmp2[0], tmp2[1], SRTYPE_LSL, 8), ctx);
1091 #else /* ARMv6+ */
1092 emit(ARM_REV16(rd, rn), ctx);
1093 #endif
1094 }
1095
1096 /* 0xabcdefgh => 0xghefcdab */
1097 static inline void emit_rev32(const u8 rd, const u8 rn, struct jit_ctx *ctx)
1098 {
1099 #if __LINUX_ARM_ARCH__ < 6
1100 const u8 *tmp2 = bpf2a32[TMP_REG_2];
1101
1102 emit(ARM_AND_I(tmp2[1], rn, 0xff), ctx);
1103 emit(ARM_MOV_SI(tmp2[0], rn, SRTYPE_LSR, 24), ctx);
1104 emit(ARM_ORR_SI(ARM_IP, tmp2[0], tmp2[1], SRTYPE_LSL, 24), ctx);
1105
1106 emit(ARM_MOV_SI(tmp2[1], rn, SRTYPE_LSR, 8), ctx);
1107 emit(ARM_AND_I(tmp2[1], tmp2[1], 0xff), ctx);
1108 emit(ARM_MOV_SI(tmp2[0], rn, SRTYPE_LSR, 16), ctx);
1109 emit(ARM_AND_I(tmp2[0], tmp2[0], 0xff), ctx);
1110 emit(ARM_MOV_SI(tmp2[0], tmp2[0], SRTYPE_LSL, 8), ctx);
1111 emit(ARM_ORR_SI(tmp2[0], tmp2[0], tmp2[1], SRTYPE_LSL, 16), ctx);
1112 emit(ARM_ORR_R(rd, ARM_IP, tmp2[0]), ctx);
1113
1114 #else /* ARMv6+ */
1115 emit(ARM_REV(rd, rn), ctx);
1116 #endif
1117 }
1118
1119 // push the scratch stack register on top of the stack
1120 static inline void emit_push_r64(const u8 src[], const u8 shift,
1121 struct jit_ctx *ctx)
1122 {
1123 const u8 *tmp2 = bpf2a32[TMP_REG_2];
1124 u16 reg_set = 0;
1125
1126 emit(ARM_LDR_I(tmp2[1], ARM_SP, STACK_VAR(src[1]+shift)), ctx);
1127 emit(ARM_LDR_I(tmp2[0], ARM_SP, STACK_VAR(src[0]+shift)), ctx);
1128
1129 reg_set = (1 << tmp2[1]) | (1 << tmp2[0]);
1130 emit(ARM_PUSH(reg_set), ctx);
1131 }
1132
1133 static void build_prologue(struct jit_ctx *ctx)
1134 {
1135 const u8 r0 = bpf2a32[BPF_REG_0][1];
1136 const u8 r2 = bpf2a32[BPF_REG_1][1];
1137 const u8 r3 = bpf2a32[BPF_REG_1][0];
1138 const u8 r4 = bpf2a32[BPF_REG_6][1];
1139 const u8 fplo = bpf2a32[BPF_REG_FP][1];
1140 const u8 fphi = bpf2a32[BPF_REG_FP][0];
1141 const u8 *tcc = bpf2a32[TCALL_CNT];
1142
1143 /* Save callee saved registers. */
1144 #ifdef CONFIG_FRAME_POINTER
1145 u16 reg_set = CALLEE_PUSH_MASK | 1 << ARM_IP | 1 << ARM_PC;
1146 emit(ARM_MOV_R(ARM_IP, ARM_SP), ctx);
1147 emit(ARM_PUSH(reg_set), ctx);
1148 emit(ARM_SUB_I(ARM_FP, ARM_IP, 4), ctx);
1149 #else
1150 emit(ARM_PUSH(CALLEE_PUSH_MASK), ctx);
1151 emit(ARM_MOV_R(ARM_FP, ARM_SP), ctx);
1152 #endif
1153 /* Save frame pointer for later */
1154 emit(ARM_SUB_I(ARM_IP, ARM_SP, SCRATCH_SIZE), ctx);
1155
1156 ctx->stack_size = imm8m(STACK_SIZE);
1157
1158 /* Set up function call stack */
1159 emit(ARM_SUB_I(ARM_SP, ARM_SP, ctx->stack_size), ctx);
1160
1161 /* Set up BPF prog stack base register */
1162 emit_a32_mov_r(fplo, ARM_IP, true, false, ctx);
1163 emit_a32_mov_i(fphi, 0, true, ctx);
1164
1165 /* mov r4, 0 */
1166 emit(ARM_MOV_I(r4, 0), ctx);
1167
1168 /* Move BPF_CTX to BPF_R1 */
1169 emit(ARM_MOV_R(r3, r4), ctx);
1170 emit(ARM_MOV_R(r2, r0), ctx);
1171 /* Initialize Tail Count */
1172 emit(ARM_STR_I(r4, ARM_SP, STACK_VAR(tcc[0])), ctx);
1173 emit(ARM_STR_I(r4, ARM_SP, STACK_VAR(tcc[1])), ctx);
1174 /* end of prologue */
1175 }
1176
1177 /* restore callee saved registers. */
1178 static void build_epilogue(struct jit_ctx *ctx)
1179 {
1180 #ifdef CONFIG_FRAME_POINTER
1181 /* When using frame pointers, some additional registers need to
1182 * be loaded. */
1183 u16 reg_set = CALLEE_POP_MASK | 1 << ARM_SP;
1184 emit(ARM_SUB_I(ARM_SP, ARM_FP, hweight16(reg_set) * 4), ctx);
1185 emit(ARM_LDM(ARM_SP, reg_set), ctx);
1186 #else
1187 /* Restore callee saved registers. */
1188 emit(ARM_MOV_R(ARM_SP, ARM_FP), ctx);
1189 emit(ARM_POP(CALLEE_POP_MASK), ctx);
1190 #endif
1191 }
1192
1193 /*
1194 * Convert an eBPF instruction to native instruction, i.e
1195 * JITs an eBPF instruction.
1196 * Returns :
1197 * 0 - Successfully JITed an 8-byte eBPF instruction
1198 * >0 - Successfully JITed a 16-byte eBPF instruction
1199 * <0 - Failed to JIT.
1200 */
1201 static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx)
1202 {
1203 const u8 code = insn->code;
1204 const u8 *dst = bpf2a32[insn->dst_reg];
1205 const u8 *src = bpf2a32[insn->src_reg];
1206 const u8 *tmp = bpf2a32[TMP_REG_1];
1207 const u8 *tmp2 = bpf2a32[TMP_REG_2];
1208 const s16 off = insn->off;
1209 const s32 imm = insn->imm;
1210 const int i = insn - ctx->prog->insnsi;
1211 const bool is64 = BPF_CLASS(code) == BPF_ALU64;
1212 const bool dstk = is_on_stack(insn->dst_reg);
1213 const bool sstk = is_on_stack(insn->src_reg);
1214 u8 rd, rt, rm, rn;
1215 s32 jmp_offset;
1216
1217 #define check_imm(bits, imm) do { \
1218 if ((((imm) > 0) && ((imm) >> (bits))) || \
1219 (((imm) < 0) && (~(imm) >> (bits)))) { \
1220 pr_info("[%2d] imm=%d(0x%x) out of range\n", \
1221 i, imm, imm); \
1222 return -EINVAL; \
1223 } \
1224 } while (0)
1225 #define check_imm24(imm) check_imm(24, imm)
1226
1227 switch (code) {
1228 /* ALU operations */
1229
1230 /* dst = src */
1231 case BPF_ALU | BPF_MOV | BPF_K:
1232 case BPF_ALU | BPF_MOV | BPF_X:
1233 case BPF_ALU64 | BPF_MOV | BPF_K:
1234 case BPF_ALU64 | BPF_MOV | BPF_X:
1235 switch (BPF_SRC(code)) {
1236 case BPF_X:
1237 emit_a32_mov_r64(is64, dst, src, dstk, sstk, ctx);
1238 break;
1239 case BPF_K:
1240 /* Sign-extend immediate value to destination reg */
1241 emit_a32_mov_i64(is64, dst, imm, dstk, ctx);
1242 break;
1243 }
1244 break;
1245 /* dst = dst + src/imm */
1246 /* dst = dst - src/imm */
1247 /* dst = dst | src/imm */
1248 /* dst = dst & src/imm */
1249 /* dst = dst ^ src/imm */
1250 /* dst = dst * src/imm */
1251 /* dst = dst << src */
1252 /* dst = dst >> src */
1253 case BPF_ALU | BPF_ADD | BPF_K:
1254 case BPF_ALU | BPF_ADD | BPF_X:
1255 case BPF_ALU | BPF_SUB | BPF_K:
1256 case BPF_ALU | BPF_SUB | BPF_X:
1257 case BPF_ALU | BPF_OR | BPF_K:
1258 case BPF_ALU | BPF_OR | BPF_X:
1259 case BPF_ALU | BPF_AND | BPF_K:
1260 case BPF_ALU | BPF_AND | BPF_X:
1261 case BPF_ALU | BPF_XOR | BPF_K:
1262 case BPF_ALU | BPF_XOR | BPF_X:
1263 case BPF_ALU | BPF_MUL | BPF_K:
1264 case BPF_ALU | BPF_MUL | BPF_X:
1265 case BPF_ALU | BPF_LSH | BPF_X:
1266 case BPF_ALU | BPF_RSH | BPF_X:
1267 case BPF_ALU | BPF_ARSH | BPF_K:
1268 case BPF_ALU | BPF_ARSH | BPF_X:
1269 case BPF_ALU64 | BPF_ADD | BPF_K:
1270 case BPF_ALU64 | BPF_ADD | BPF_X:
1271 case BPF_ALU64 | BPF_SUB | BPF_K:
1272 case BPF_ALU64 | BPF_SUB | BPF_X:
1273 case BPF_ALU64 | BPF_OR | BPF_K:
1274 case BPF_ALU64 | BPF_OR | BPF_X:
1275 case BPF_ALU64 | BPF_AND | BPF_K:
1276 case BPF_ALU64 | BPF_AND | BPF_X:
1277 case BPF_ALU64 | BPF_XOR | BPF_K:
1278 case BPF_ALU64 | BPF_XOR | BPF_X:
1279 switch (BPF_SRC(code)) {
1280 case BPF_X:
1281 emit_a32_alu_r64(is64, dst, src, dstk, sstk,
1282 ctx, BPF_OP(code));
1283 break;
1284 case BPF_K:
1285 /* Move immediate value to the temporary register
1286 * and then do the ALU operation on the temporary
1287 * register as this will sign-extend the immediate
1288 * value into temporary reg and then it would be
1289 * safe to do the operation on it.
1290 */
1291 emit_a32_mov_i64(is64, tmp2, imm, false, ctx);
1292 emit_a32_alu_r64(is64, dst, tmp2, dstk, false,
1293 ctx, BPF_OP(code));
1294 break;
1295 }
1296 break;
1297 /* dst = dst / src(imm) */
1298 /* dst = dst % src(imm) */
1299 case BPF_ALU | BPF_DIV | BPF_K:
1300 case BPF_ALU | BPF_DIV | BPF_X:
1301 case BPF_ALU | BPF_MOD | BPF_K:
1302 case BPF_ALU | BPF_MOD | BPF_X:
1303 rt = src_lo;
1304 rd = dstk ? tmp2[1] : dst_lo;
1305 if (dstk)
1306 emit(ARM_LDR_I(rd, ARM_SP, STACK_VAR(dst_lo)), ctx);
1307 switch (BPF_SRC(code)) {
1308 case BPF_X:
1309 rt = sstk ? tmp2[0] : rt;
1310 if (sstk)
1311 emit(ARM_LDR_I(rt, ARM_SP, STACK_VAR(src_lo)),
1312 ctx);
1313 break;
1314 case BPF_K:
1315 rt = tmp2[0];
1316 emit_a32_mov_i(rt, imm, false, ctx);
1317 break;
1318 }
1319 emit_udivmod(rd, rd, rt, ctx, BPF_OP(code));
1320 if (dstk)
1321 emit(ARM_STR_I(rd, ARM_SP, STACK_VAR(dst_lo)), ctx);
1322 emit_a32_mov_i(dst_hi, 0, dstk, ctx);
1323 break;
1324 case BPF_ALU64 | BPF_DIV | BPF_K:
1325 case BPF_ALU64 | BPF_DIV | BPF_X:
1326 case BPF_ALU64 | BPF_MOD | BPF_K:
1327 case BPF_ALU64 | BPF_MOD | BPF_X:
1328 goto notyet;
1329 /* dst = dst >> imm */
1330 /* dst = dst << imm */
1331 case BPF_ALU | BPF_RSH | BPF_K:
1332 case BPF_ALU | BPF_LSH | BPF_K:
1333 if (unlikely(imm > 31))
1334 return -EINVAL;
1335 if (imm)
1336 emit_a32_alu_i(dst_lo, imm, dstk, ctx, BPF_OP(code));
1337 emit_a32_mov_i(dst_hi, 0, dstk, ctx);
1338 break;
1339 /* dst = dst << imm */
1340 case BPF_ALU64 | BPF_LSH | BPF_K:
1341 if (unlikely(imm > 63))
1342 return -EINVAL;
1343 emit_a32_lsh_i64(dst, dstk, imm, ctx);
1344 break;
1345 /* dst = dst >> imm */
1346 case BPF_ALU64 | BPF_RSH | BPF_K:
1347 if (unlikely(imm > 63))
1348 return -EINVAL;
1349 emit_a32_rsh_i64(dst, dstk, imm, ctx);
1350 break;
1351 /* dst = dst << src */
1352 case BPF_ALU64 | BPF_LSH | BPF_X:
1353 emit_a32_lsh_r64(dst, src, dstk, sstk, ctx);
1354 break;
1355 /* dst = dst >> src */
1356 case BPF_ALU64 | BPF_RSH | BPF_X:
1357 emit_a32_rsh_r64(dst, src, dstk, sstk, ctx);
1358 break;
1359 /* dst = dst >> src (signed) */
1360 case BPF_ALU64 | BPF_ARSH | BPF_X:
1361 emit_a32_arsh_r64(dst, src, dstk, sstk, ctx);
1362 break;
1363 /* dst = dst >> imm (signed) */
1364 case BPF_ALU64 | BPF_ARSH | BPF_K:
1365 if (unlikely(imm > 63))
1366 return -EINVAL;
1367 emit_a32_arsh_i64(dst, dstk, imm, ctx);
1368 break;
1369 /* dst = ~dst */
1370 case BPF_ALU | BPF_NEG:
1371 emit_a32_alu_i(dst_lo, 0, dstk, ctx, BPF_OP(code));
1372 emit_a32_mov_i(dst_hi, 0, dstk, ctx);
1373 break;
1374 /* dst = ~dst (64 bit) */
1375 case BPF_ALU64 | BPF_NEG:
1376 emit_a32_neg64(dst, dstk, ctx);
1377 break;
1378 /* dst = dst * src/imm */
1379 case BPF_ALU64 | BPF_MUL | BPF_X:
1380 case BPF_ALU64 | BPF_MUL | BPF_K:
1381 switch (BPF_SRC(code)) {
1382 case BPF_X:
1383 emit_a32_mul_r64(dst, src, dstk, sstk, ctx);
1384 break;
1385 case BPF_K:
1386 /* Move immediate value to the temporary register
1387 * and then do the multiplication on it as this
1388 * will sign-extend the immediate value into temp
1389 * reg then it would be safe to do the operation
1390 * on it.
1391 */
1392 emit_a32_mov_i64(is64, tmp2, imm, false, ctx);
1393 emit_a32_mul_r64(dst, tmp2, dstk, false, ctx);
1394 break;
1395 }
1396 break;
1397 /* dst = htole(dst) */
1398 /* dst = htobe(dst) */
1399 case BPF_ALU | BPF_END | BPF_FROM_LE:
1400 case BPF_ALU | BPF_END | BPF_FROM_BE:
1401 rd = dstk ? tmp[0] : dst_hi;
1402 rt = dstk ? tmp[1] : dst_lo;
1403 if (dstk) {
1404 emit(ARM_LDR_I(rt, ARM_SP, STACK_VAR(dst_lo)), ctx);
1405 emit(ARM_LDR_I(rd, ARM_SP, STACK_VAR(dst_hi)), ctx);
1406 }
1407 if (BPF_SRC(code) == BPF_FROM_LE)
1408 goto emit_bswap_uxt;
1409 switch (imm) {
1410 case 16:
1411 emit_rev16(rt, rt, ctx);
1412 goto emit_bswap_uxt;
1413 case 32:
1414 emit_rev32(rt, rt, ctx);
1415 goto emit_bswap_uxt;
1416 case 64:
1417 emit_rev32(ARM_LR, rt, ctx);
1418 emit_rev32(rt, rd, ctx);
1419 emit(ARM_MOV_R(rd, ARM_LR), ctx);
1420 break;
1421 }
1422 goto exit;
1423 emit_bswap_uxt:
1424 switch (imm) {
1425 case 16:
1426 /* zero-extend 16 bits into 64 bits */
1427 #if __LINUX_ARM_ARCH__ < 6
1428 emit_a32_mov_i(tmp2[1], 0xffff, false, ctx);
1429 emit(ARM_AND_R(rt, rt, tmp2[1]), ctx);
1430 #else /* ARMv6+ */
1431 emit(ARM_UXTH(rt, rt), ctx);
1432 #endif
1433 emit(ARM_EOR_R(rd, rd, rd), ctx);
1434 break;
1435 case 32:
1436 /* zero-extend 32 bits into 64 bits */
1437 emit(ARM_EOR_R(rd, rd, rd), ctx);
1438 break;
1439 case 64:
1440 /* nop */
1441 break;
1442 }
1443 exit:
1444 if (dstk) {
1445 emit(ARM_STR_I(rt, ARM_SP, STACK_VAR(dst_lo)), ctx);
1446 emit(ARM_STR_I(rd, ARM_SP, STACK_VAR(dst_hi)), ctx);
1447 }
1448 break;
1449 /* dst = imm64 */
1450 case BPF_LD | BPF_IMM | BPF_DW:
1451 {
1452 const struct bpf_insn insn1 = insn[1];
1453 u32 hi, lo = imm;
1454
1455 hi = insn1.imm;
1456 emit_a32_mov_i(dst_lo, lo, dstk, ctx);
1457 emit_a32_mov_i(dst_hi, hi, dstk, ctx);
1458
1459 return 1;
1460 }
1461 /* LDX: dst = *(size *)(src + off) */
1462 case BPF_LDX | BPF_MEM | BPF_W:
1463 case BPF_LDX | BPF_MEM | BPF_H:
1464 case BPF_LDX | BPF_MEM | BPF_B:
1465 case BPF_LDX | BPF_MEM | BPF_DW:
1466 rn = sstk ? tmp2[1] : src_lo;
1467 if (sstk)
1468 emit(ARM_LDR_I(rn, ARM_SP, STACK_VAR(src_lo)), ctx);
1469 emit_ldx_r(dst, rn, dstk, off, ctx, BPF_SIZE(code));
1470 break;
1471 /* R0 = ntohx(*(size *)(((struct sk_buff *)R6)->data + imm)) */
1472 case BPF_LD | BPF_ABS | BPF_W:
1473 case BPF_LD | BPF_ABS | BPF_H:
1474 case BPF_LD | BPF_ABS | BPF_B:
1475 /* R0 = ntohx(*(size *)(((struct sk_buff *)R6)->data + src + imm)) */
1476 case BPF_LD | BPF_IND | BPF_W:
1477 case BPF_LD | BPF_IND | BPF_H:
1478 case BPF_LD | BPF_IND | BPF_B:
1479 {
1480 const u8 r4 = bpf2a32[BPF_REG_6][1]; /* r4 = ptr to sk_buff */
1481 const u8 r0 = bpf2a32[BPF_REG_0][1]; /*r0: struct sk_buff *skb*/
1482 /* rtn value */
1483 const u8 r1 = bpf2a32[BPF_REG_0][0]; /* r1: int k */
1484 const u8 r2 = bpf2a32[BPF_REG_1][1]; /* r2: unsigned int size */
1485 const u8 r3 = bpf2a32[BPF_REG_1][0]; /* r3: void *buffer */
1486 const u8 r6 = bpf2a32[TMP_REG_1][1]; /* r6: void *(*func)(..) */
1487 int size;
1488
1489 /* Setting up first argument */
1490 emit(ARM_MOV_R(r0, r4), ctx);
1491
1492 /* Setting up second argument */
1493 emit_a32_mov_i(r1, imm, false, ctx);
1494 if (BPF_MODE(code) == BPF_IND)
1495 emit_a32_alu_r(r1, src_lo, false, sstk, ctx,
1496 false, false, BPF_ADD);
1497
1498 /* Setting up third argument */
1499 switch (BPF_SIZE(code)) {
1500 case BPF_W:
1501 size = 4;
1502 break;
1503 case BPF_H:
1504 size = 2;
1505 break;
1506 case BPF_B:
1507 size = 1;
1508 break;
1509 default:
1510 return -EINVAL;
1511 }
1512 emit_a32_mov_i(r2, size, false, ctx);
1513
1514 /* Setting up fourth argument */
1515 emit(ARM_ADD_I(r3, ARM_SP, imm8m(SKB_BUFFER)), ctx);
1516
1517 /* Setting up function pointer to call */
1518 emit_a32_mov_i(r6, (unsigned int)bpf_load_pointer, false, ctx);
1519 emit_blx_r(r6, ctx);
1520
1521 emit(ARM_EOR_R(r1, r1, r1), ctx);
1522 /* Check if return address is NULL or not.
1523 * if NULL then jump to epilogue
1524 * else continue to load the value from retn address
1525 */
1526 emit(ARM_CMP_I(r0, 0), ctx);
1527 jmp_offset = epilogue_offset(ctx);
1528 check_imm24(jmp_offset);
1529 _emit(ARM_COND_EQ, ARM_B(jmp_offset), ctx);
1530
1531 /* Load value from the address */
1532 switch (BPF_SIZE(code)) {
1533 case BPF_W:
1534 emit(ARM_LDR_I(r0, r0, 0), ctx);
1535 emit_rev32(r0, r0, ctx);
1536 break;
1537 case BPF_H:
1538 emit(ARM_LDRH_I(r0, r0, 0), ctx);
1539 emit_rev16(r0, r0, ctx);
1540 break;
1541 case BPF_B:
1542 emit(ARM_LDRB_I(r0, r0, 0), ctx);
1543 /* No need to reverse */
1544 break;
1545 }
1546 break;
1547 }
1548 /* ST: *(size *)(dst + off) = imm */
1549 case BPF_ST | BPF_MEM | BPF_W:
1550 case BPF_ST | BPF_MEM | BPF_H:
1551 case BPF_ST | BPF_MEM | BPF_B:
1552 case BPF_ST | BPF_MEM | BPF_DW:
1553 switch (BPF_SIZE(code)) {
1554 case BPF_DW:
1555 /* Sign-extend immediate value into temp reg */
1556 emit_a32_mov_i64(true, tmp2, imm, false, ctx);
1557 emit_str_r(dst_lo, tmp2[1], dstk, off, ctx, BPF_W);
1558 emit_str_r(dst_lo, tmp2[0], dstk, off+4, ctx, BPF_W);
1559 break;
1560 case BPF_W:
1561 case BPF_H:
1562 case BPF_B:
1563 emit_a32_mov_i(tmp2[1], imm, false, ctx);
1564 emit_str_r(dst_lo, tmp2[1], dstk, off, ctx,
1565 BPF_SIZE(code));
1566 break;
1567 }
1568 break;
1569 /* STX XADD: lock *(u32 *)(dst + off) += src */
1570 case BPF_STX | BPF_XADD | BPF_W:
1571 /* STX XADD: lock *(u64 *)(dst + off) += src */
1572 case BPF_STX | BPF_XADD | BPF_DW:
1573 goto notyet;
1574 /* STX: *(size *)(dst + off) = src */
1575 case BPF_STX | BPF_MEM | BPF_W:
1576 case BPF_STX | BPF_MEM | BPF_H:
1577 case BPF_STX | BPF_MEM | BPF_B:
1578 case BPF_STX | BPF_MEM | BPF_DW:
1579 {
1580 u8 sz = BPF_SIZE(code);
1581
1582 rn = sstk ? tmp2[1] : src_lo;
1583 rm = sstk ? tmp2[0] : src_hi;
1584 if (sstk) {
1585 emit(ARM_LDR_I(rn, ARM_SP, STACK_VAR(src_lo)), ctx);
1586 emit(ARM_LDR_I(rm, ARM_SP, STACK_VAR(src_hi)), ctx);
1587 }
1588
1589 /* Store the value */
1590 if (BPF_SIZE(code) == BPF_DW) {
1591 emit_str_r(dst_lo, rn, dstk, off, ctx, BPF_W);
1592 emit_str_r(dst_lo, rm, dstk, off+4, ctx, BPF_W);
1593 } else {
1594 emit_str_r(dst_lo, rn, dstk, off, ctx, sz);
1595 }
1596 break;
1597 }
1598 /* PC += off if dst == src */
1599 /* PC += off if dst > src */
1600 /* PC += off if dst >= src */
1601 /* PC += off if dst < src */
1602 /* PC += off if dst <= src */
1603 /* PC += off if dst != src */
1604 /* PC += off if dst > src (signed) */
1605 /* PC += off if dst >= src (signed) */
1606 /* PC += off if dst < src (signed) */
1607 /* PC += off if dst <= src (signed) */
1608 /* PC += off if dst & src */
1609 case BPF_JMP | BPF_JEQ | BPF_X:
1610 case BPF_JMP | BPF_JGT | BPF_X:
1611 case BPF_JMP | BPF_JGE | BPF_X:
1612 case BPF_JMP | BPF_JNE | BPF_X:
1613 case BPF_JMP | BPF_JSGT | BPF_X:
1614 case BPF_JMP | BPF_JSGE | BPF_X:
1615 case BPF_JMP | BPF_JSET | BPF_X:
1616 case BPF_JMP | BPF_JLE | BPF_X:
1617 case BPF_JMP | BPF_JLT | BPF_X:
1618 case BPF_JMP | BPF_JSLT | BPF_X:
1619 case BPF_JMP | BPF_JSLE | BPF_X:
1620 /* Setup source registers */
1621 rm = sstk ? tmp2[0] : src_hi;
1622 rn = sstk ? tmp2[1] : src_lo;
1623 if (sstk) {
1624 emit(ARM_LDR_I(rn, ARM_SP, STACK_VAR(src_lo)), ctx);
1625 emit(ARM_LDR_I(rm, ARM_SP, STACK_VAR(src_hi)), ctx);
1626 }
1627 goto go_jmp;
1628 /* PC += off if dst == imm */
1629 /* PC += off if dst > imm */
1630 /* PC += off if dst >= imm */
1631 /* PC += off if dst < imm */
1632 /* PC += off if dst <= imm */
1633 /* PC += off if dst != imm */
1634 /* PC += off if dst > imm (signed) */
1635 /* PC += off if dst >= imm (signed) */
1636 /* PC += off if dst < imm (signed) */
1637 /* PC += off if dst <= imm (signed) */
1638 /* PC += off if dst & imm */
1639 case BPF_JMP | BPF_JEQ | BPF_K:
1640 case BPF_JMP | BPF_JGT | BPF_K:
1641 case BPF_JMP | BPF_JGE | BPF_K:
1642 case BPF_JMP | BPF_JNE | BPF_K:
1643 case BPF_JMP | BPF_JSGT | BPF_K:
1644 case BPF_JMP | BPF_JSGE | BPF_K:
1645 case BPF_JMP | BPF_JSET | BPF_K:
1646 case BPF_JMP | BPF_JLT | BPF_K:
1647 case BPF_JMP | BPF_JLE | BPF_K:
1648 case BPF_JMP | BPF_JSLT | BPF_K:
1649 case BPF_JMP | BPF_JSLE | BPF_K:
1650 if (off == 0)
1651 break;
1652 rm = tmp2[0];
1653 rn = tmp2[1];
1654 /* Sign-extend immediate value */
1655 emit_a32_mov_i64(true, tmp2, imm, false, ctx);
1656 go_jmp:
1657 /* Setup destination register */
1658 rd = dstk ? tmp[0] : dst_hi;
1659 rt = dstk ? tmp[1] : dst_lo;
1660 if (dstk) {
1661 emit(ARM_LDR_I(rt, ARM_SP, STACK_VAR(dst_lo)), ctx);
1662 emit(ARM_LDR_I(rd, ARM_SP, STACK_VAR(dst_hi)), ctx);
1663 }
1664
1665 /* Check for the condition */
1666 emit_ar_r(rd, rt, rm, rn, ctx, BPF_OP(code));
1667
1668 /* Setup JUMP instruction */
1669 jmp_offset = bpf2a32_offset(i+off, i, ctx);
1670 switch (BPF_OP(code)) {
1671 case BPF_JNE:
1672 case BPF_JSET:
1673 _emit(ARM_COND_NE, ARM_B(jmp_offset), ctx);
1674 break;
1675 case BPF_JEQ:
1676 _emit(ARM_COND_EQ, ARM_B(jmp_offset), ctx);
1677 break;
1678 case BPF_JGT:
1679 _emit(ARM_COND_HI, ARM_B(jmp_offset), ctx);
1680 break;
1681 case BPF_JGE:
1682 _emit(ARM_COND_CS, ARM_B(jmp_offset), ctx);
1683 break;
1684 case BPF_JSGT:
1685 _emit(ARM_COND_LT, ARM_B(jmp_offset), ctx);
1686 break;
1687 case BPF_JSGE:
1688 _emit(ARM_COND_GE, ARM_B(jmp_offset), ctx);
1689 break;
1690 case BPF_JLE:
1691 _emit(ARM_COND_LS, ARM_B(jmp_offset), ctx);
1692 break;
1693 case BPF_JLT:
1694 _emit(ARM_COND_CC, ARM_B(jmp_offset), ctx);
1695 break;
1696 case BPF_JSLT:
1697 _emit(ARM_COND_LT, ARM_B(jmp_offset), ctx);
1698 break;
1699 case BPF_JSLE:
1700 _emit(ARM_COND_GE, ARM_B(jmp_offset), ctx);
1701 break;
1702 }
1703 break;
1704 /* JMP OFF */
1705 case BPF_JMP | BPF_JA:
1706 {
1707 if (off == 0)
1708 break;
1709 jmp_offset = bpf2a32_offset(i+off, i, ctx);
1710 check_imm24(jmp_offset);
1711 emit(ARM_B(jmp_offset), ctx);
1712 break;
1713 }
1714 /* tail call */
1715 case BPF_JMP | BPF_TAIL_CALL:
1716 if (emit_bpf_tail_call(ctx))
1717 return -EFAULT;
1718 break;
1719 /* function call */
1720 case BPF_JMP | BPF_CALL:
1721 {
1722 const u8 *r0 = bpf2a32[BPF_REG_0];
1723 const u8 *r1 = bpf2a32[BPF_REG_1];
1724 const u8 *r2 = bpf2a32[BPF_REG_2];
1725 const u8 *r3 = bpf2a32[BPF_REG_3];
1726 const u8 *r4 = bpf2a32[BPF_REG_4];
1727 const u8 *r5 = bpf2a32[BPF_REG_5];
1728 const u32 func = (u32)__bpf_call_base + (u32)imm;
1729
1730 emit_a32_mov_r64(true, r0, r1, false, false, ctx);
1731 emit_a32_mov_r64(true, r1, r2, false, true, ctx);
1732 emit_push_r64(r5, 0, ctx);
1733 emit_push_r64(r4, 8, ctx);
1734 emit_push_r64(r3, 16, ctx);
1735
1736 emit_a32_mov_i(tmp[1], func, false, ctx);
1737 emit_blx_r(tmp[1], ctx);
1738
1739 emit(ARM_ADD_I(ARM_SP, ARM_SP, imm8m(24)), ctx); // callee clean
1740 break;
1741 }
1742 /* function return */
1743 case BPF_JMP | BPF_EXIT:
1744 /* Optimization: when last instruction is EXIT
1745 * simply fallthrough to epilogue.
1746 */
1747 if (i == ctx->prog->len - 1)
1748 break;
1749 jmp_offset = epilogue_offset(ctx);
1750 check_imm24(jmp_offset);
1751 emit(ARM_B(jmp_offset), ctx);
1752 break;
1753 notyet:
1754 pr_info_once("*** NOT YET: opcode %02x ***\n", code);
1755 return -EFAULT;
1756 default:
1757 pr_err_once("unknown opcode %02x\n", code);
1758 return -EINVAL;
1759 }
1760
1761 if (ctx->flags & FLAG_IMM_OVERFLOW)
1762 /*
1763 * this instruction generated an overflow when
1764 * trying to access the literal pool, so
1765 * delegate this filter to the kernel interpreter.
1766 */
1767 return -1;
1768 return 0;
1769 }
1770
1771 static int build_body(struct jit_ctx *ctx)
1772 {
1773 const struct bpf_prog *prog = ctx->prog;
1774 unsigned int i;
1775
1776 for (i = 0; i < prog->len; i++) {
1777 const struct bpf_insn *insn = &(prog->insnsi[i]);
1778 int ret;
1779
1780 ret = build_insn(insn, ctx);
1781
1782 /* It's used with loading the 64 bit immediate value. */
1783 if (ret > 0) {
1784 i++;
1785 if (ctx->target == NULL)
1786 ctx->offsets[i] = ctx->idx;
1787 continue;
1788 }
1789
1790 if (ctx->target == NULL)
1791 ctx->offsets[i] = ctx->idx;
1792
1793 /* If unsuccesfull, return with error code */
1794 if (ret)
1795 return ret;
1796 }
1797 return 0;
1798 }
1799
1800 static int validate_code(struct jit_ctx *ctx)
1801 {
1802 int i;
1803
1804 for (i = 0; i < ctx->idx; i++) {
1805 if (ctx->target[i] == __opcode_to_mem_arm(ARM_INST_UDF))
1806 return -1;
1807 }
1808
1809 return 0;
1810 }
1811
1812 void bpf_jit_compile(struct bpf_prog *prog)
1813 {
1814 /* Nothing to do here. We support Internal BPF. */
1815 }
1816
1817 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
1818 {
1819 struct bpf_prog *tmp, *orig_prog = prog;
1820 struct bpf_binary_header *header;
1821 bool tmp_blinded = false;
1822 struct jit_ctx ctx;
1823 unsigned int tmp_idx;
1824 unsigned int image_size;
1825 u8 *image_ptr;
1826
1827 /* If BPF JIT was not enabled then we must fall back to
1828 * the interpreter.
1829 */
1830 if (!bpf_jit_enable)
1831 return orig_prog;
1832
1833 /* If constant blinding was enabled and we failed during blinding
1834 * then we must fall back to the interpreter. Otherwise, we save
1835 * the new JITed code.
1836 */
1837 tmp = bpf_jit_blind_constants(prog);
1838
1839 if (IS_ERR(tmp))
1840 return orig_prog;
1841 if (tmp != prog) {
1842 tmp_blinded = true;
1843 prog = tmp;
1844 }
1845
1846 memset(&ctx, 0, sizeof(ctx));
1847 ctx.prog = prog;
1848
1849 /* Not able to allocate memory for offsets[] , then
1850 * we must fall back to the interpreter
1851 */
1852 ctx.offsets = kcalloc(prog->len, sizeof(int), GFP_KERNEL);
1853 if (ctx.offsets == NULL) {
1854 prog = orig_prog;
1855 goto out;
1856 }
1857
1858 /* 1) fake pass to find in the length of the JITed code,
1859 * to compute ctx->offsets and other context variables
1860 * needed to compute final JITed code.
1861 * Also, calculate random starting pointer/start of JITed code
1862 * which is prefixed by random number of fault instructions.
1863 *
1864 * If the first pass fails then there is no chance of it
1865 * being successful in the second pass, so just fall back
1866 * to the interpreter.
1867 */
1868 if (build_body(&ctx)) {
1869 prog = orig_prog;
1870 goto out_off;
1871 }
1872
1873 tmp_idx = ctx.idx;
1874 build_prologue(&ctx);
1875 ctx.prologue_bytes = (ctx.idx - tmp_idx) * 4;
1876
1877 ctx.epilogue_offset = ctx.idx;
1878
1879 #if __LINUX_ARM_ARCH__ < 7
1880 tmp_idx = ctx.idx;
1881 build_epilogue(&ctx);
1882 ctx.epilogue_bytes = (ctx.idx - tmp_idx) * 4;
1883
1884 ctx.idx += ctx.imm_count;
1885 if (ctx.imm_count) {
1886 ctx.imms = kcalloc(ctx.imm_count, sizeof(u32), GFP_KERNEL);
1887 if (ctx.imms == NULL) {
1888 prog = orig_prog;
1889 goto out_off;
1890 }
1891 }
1892 #else
1893 /* there's nothing about the epilogue on ARMv7 */
1894 build_epilogue(&ctx);
1895 #endif
1896 /* Now we can get the actual image size of the JITed arm code.
1897 * Currently, we are not considering the THUMB-2 instructions
1898 * for jit, although it can decrease the size of the image.
1899 *
1900 * As each arm instruction is of length 32bit, we are translating
1901 * number of JITed intructions into the size required to store these
1902 * JITed code.
1903 */
1904 image_size = sizeof(u32) * ctx.idx;
1905
1906 /* Now we know the size of the structure to make */
1907 header = bpf_jit_binary_alloc(image_size, &image_ptr,
1908 sizeof(u32), jit_fill_hole);
1909 /* Not able to allocate memory for the structure then
1910 * we must fall back to the interpretation
1911 */
1912 if (header == NULL) {
1913 prog = orig_prog;
1914 goto out_imms;
1915 }
1916
1917 /* 2.) Actual pass to generate final JIT code */
1918 ctx.target = (u32 *) image_ptr;
1919 ctx.idx = 0;
1920
1921 build_prologue(&ctx);
1922
1923 /* If building the body of the JITed code fails somehow,
1924 * we fall back to the interpretation.
1925 */
1926 if (build_body(&ctx) < 0) {
1927 image_ptr = NULL;
1928 bpf_jit_binary_free(header);
1929 prog = orig_prog;
1930 goto out_imms;
1931 }
1932 build_epilogue(&ctx);
1933
1934 /* 3.) Extra pass to validate JITed Code */
1935 if (validate_code(&ctx)) {
1936 image_ptr = NULL;
1937 bpf_jit_binary_free(header);
1938 prog = orig_prog;
1939 goto out_imms;
1940 }
1941 flush_icache_range((u32)header, (u32)(ctx.target + ctx.idx));
1942
1943 if (bpf_jit_enable > 1)
1944 /* there are 2 passes here */
1945 bpf_jit_dump(prog->len, image_size, 2, ctx.target);
1946
1947 set_memory_ro((unsigned long)header, header->pages);
1948 prog->bpf_func = (void *)ctx.target;
1949 prog->jited = 1;
1950 prog->jited_len = image_size;
1951
1952 out_imms:
1953 #if __LINUX_ARM_ARCH__ < 7
1954 if (ctx.imm_count)
1955 kfree(ctx.imms);
1956 #endif
1957 out_off:
1958 kfree(ctx.offsets);
1959 out:
1960 if (tmp_blinded)
1961 bpf_jit_prog_release_other(prog, prog == orig_prog ?
1962 tmp : orig_prog);
1963 return prog;
1964 }
1965
Linux with added FPC-III support