2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/bootmem.h>
25 #include <linux/shmem_fs.h>
26 #include <linux/list.h>
27 #include <linux/syscalls.h>
28 #include <linux/irq.h>
29 #include <linux/vmalloc.h>
30 #include <linux/slab.h>
32 #include <linux/of_address.h>
33 #include <linux/of_irq.h>
34 #include <linux/of_pci.h>
35 #include <linux/export.h>
37 #include <asm/processor.h>
39 #include <asm/pci-bridge.h>
40 #include <asm/byteorder.h>
42 static DEFINE_SPINLOCK(hose_spinlock
);
45 /* XXX kill that some day ... */
46 static int global_phb_number
; /* Global phb counter */
48 /* ISA Memory physical address */
49 resource_size_t isa_mem_base
;
51 unsigned long isa_io_base
;
52 EXPORT_SYMBOL(isa_io_base
);
54 static int pci_bus_count
;
56 struct pci_controller
*pcibios_alloc_controller(struct device_node
*dev
)
58 struct pci_controller
*phb
;
60 phb
= zalloc_maybe_bootmem(sizeof(struct pci_controller
), GFP_KERNEL
);
63 spin_lock(&hose_spinlock
);
64 phb
->global_number
= global_phb_number
++;
65 list_add_tail(&phb
->list_node
, &hose_list
);
66 spin_unlock(&hose_spinlock
);
68 phb
->is_dynamic
= mem_init_done
;
72 void pcibios_free_controller(struct pci_controller
*phb
)
74 spin_lock(&hose_spinlock
);
75 list_del(&phb
->list_node
);
76 spin_unlock(&hose_spinlock
);
82 static resource_size_t
pcibios_io_size(const struct pci_controller
*hose
)
84 return resource_size(&hose
->io_resource
);
87 int pcibios_vaddr_is_ioport(void __iomem
*address
)
90 struct pci_controller
*hose
;
93 spin_lock(&hose_spinlock
);
94 list_for_each_entry(hose
, &hose_list
, list_node
) {
95 size
= pcibios_io_size(hose
);
96 if (address
>= hose
->io_base_virt
&&
97 address
< (hose
->io_base_virt
+ size
)) {
102 spin_unlock(&hose_spinlock
);
106 unsigned long pci_address_to_pio(phys_addr_t address
)
108 struct pci_controller
*hose
;
109 resource_size_t size
;
110 unsigned long ret
= ~0;
112 spin_lock(&hose_spinlock
);
113 list_for_each_entry(hose
, &hose_list
, list_node
) {
114 size
= pcibios_io_size(hose
);
115 if (address
>= hose
->io_base_phys
&&
116 address
< (hose
->io_base_phys
+ size
)) {
118 (unsigned long)hose
->io_base_virt
- _IO_BASE
;
119 ret
= base
+ (address
- hose
->io_base_phys
);
123 spin_unlock(&hose_spinlock
);
127 EXPORT_SYMBOL_GPL(pci_address_to_pio
);
129 /* This routine is meant to be used early during boot, when the
130 * PCI bus numbers have not yet been assigned, and you need to
131 * issue PCI config cycles to an OF device.
132 * It could also be used to "fix" RTAS config cycles if you want
133 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
136 struct pci_controller
*pci_find_hose_for_OF_device(struct device_node
*node
)
139 struct pci_controller
*hose
, *tmp
;
140 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
141 if (hose
->dn
== node
)
148 void pcibios_set_master(struct pci_dev
*dev
)
150 /* No special bus mastering setup handling */
154 * Platform support for /proc/bus/pci/X/Y mmap()s,
155 * modelled on the sparc64 implementation by Dave Miller.
160 * Adjust vm_pgoff of VMA such that it is the physical page offset
161 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
163 * Basically, the user finds the base address for his device which he wishes
164 * to mmap. They read the 32-bit value from the config space base register,
165 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
166 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
168 * Returns negative error code on failure, zero on success.
170 static struct resource
*__pci_mmap_make_offset(struct pci_dev
*dev
,
171 resource_size_t
*offset
,
172 enum pci_mmap_state mmap_state
)
174 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
175 unsigned long io_offset
= 0;
179 return NULL
; /* should never happen */
181 /* If memory, add on the PCI bridge address offset */
182 if (mmap_state
== pci_mmap_mem
) {
183 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
184 *offset
+= hose
->pci_mem_offset
;
186 res_bit
= IORESOURCE_MEM
;
188 io_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
189 *offset
+= io_offset
;
190 res_bit
= IORESOURCE_IO
;
194 * Check that the offset requested corresponds to one of the
195 * resources of the device.
197 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
198 struct resource
*rp
= &dev
->resource
[i
];
199 int flags
= rp
->flags
;
201 /* treat ROM as memory (should be already) */
202 if (i
== PCI_ROM_RESOURCE
)
203 flags
|= IORESOURCE_MEM
;
205 /* Active and same type? */
206 if ((flags
& res_bit
) == 0)
209 /* In the range of this resource? */
210 if (*offset
< (rp
->start
& PAGE_MASK
) || *offset
> rp
->end
)
213 /* found it! construct the final physical address */
214 if (mmap_state
== pci_mmap_io
)
215 *offset
+= hose
->io_base_phys
- io_offset
;
223 * This one is used by /dev/mem and fbdev who have no clue about the
224 * PCI device, it tries to find the PCI device first and calls the
227 pgprot_t
pci_phys_mem_access_prot(struct file
*file
,
232 struct pci_dev
*pdev
= NULL
;
233 struct resource
*found
= NULL
;
234 resource_size_t offset
= ((resource_size_t
)pfn
) << PAGE_SHIFT
;
237 if (page_is_ram(pfn
))
240 prot
= pgprot_noncached(prot
);
241 for_each_pci_dev(pdev
) {
242 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
243 struct resource
*rp
= &pdev
->resource
[i
];
244 int flags
= rp
->flags
;
246 /* Active and same type? */
247 if ((flags
& IORESOURCE_MEM
) == 0)
249 /* In the range of this resource? */
250 if (offset
< (rp
->start
& PAGE_MASK
) ||
260 if (found
->flags
& IORESOURCE_PREFETCH
)
261 prot
= pgprot_noncached_wc(prot
);
265 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
266 (unsigned long long)offset
, pgprot_val(prot
));
272 * Perform the actual remap of the pages for a PCI device mapping, as
273 * appropriate for this architecture. The region in the process to map
274 * is described by vm_start and vm_end members of VMA, the base physical
275 * address is found in vm_pgoff.
276 * The pci device structure is provided so that architectures may make mapping
277 * decisions on a per-device or per-bus basis.
279 * Returns a negative error code on failure, zero on success.
281 int pci_mmap_page_range(struct pci_dev
*dev
, int bar
, struct vm_area_struct
*vma
,
282 enum pci_mmap_state mmap_state
, int write_combine
)
284 resource_size_t offset
=
285 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
289 rp
= __pci_mmap_make_offset(dev
, &offset
, mmap_state
);
293 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
294 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
296 ret
= remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
297 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
302 /* This provides legacy IO read access on a bus */
303 int pci_legacy_read(struct pci_bus
*bus
, loff_t port
, u32
*val
, size_t size
)
305 unsigned long offset
;
306 struct pci_controller
*hose
= pci_bus_to_host(bus
);
307 struct resource
*rp
= &hose
->io_resource
;
310 /* Check if port can be supported by that bus. We only check
311 * the ranges of the PHB though, not the bus itself as the rules
312 * for forwarding legacy cycles down bridges are not our problem
313 * here. So if the host bridge supports it, we do it.
315 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
318 if (!(rp
->flags
& IORESOURCE_IO
))
320 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
322 addr
= hose
->io_base_virt
+ port
;
326 *((u8
*)val
) = in_8(addr
);
331 *((u16
*)val
) = in_le16(addr
);
336 *((u32
*)val
) = in_le32(addr
);
342 /* This provides legacy IO write access on a bus */
343 int pci_legacy_write(struct pci_bus
*bus
, loff_t port
, u32 val
, size_t size
)
345 unsigned long offset
;
346 struct pci_controller
*hose
= pci_bus_to_host(bus
);
347 struct resource
*rp
= &hose
->io_resource
;
350 /* Check if port can be supported by that bus. We only check
351 * the ranges of the PHB though, not the bus itself as the rules
352 * for forwarding legacy cycles down bridges are not our problem
353 * here. So if the host bridge supports it, we do it.
355 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
358 if (!(rp
->flags
& IORESOURCE_IO
))
360 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
362 addr
= hose
->io_base_virt
+ port
;
364 /* WARNING: The generic code is idiotic. It gets passed a pointer
365 * to what can be a 1, 2 or 4 byte quantity and always reads that
366 * as a u32, which means that we have to correct the location of
367 * the data read within those 32 bits for size 1 and 2
371 out_8(addr
, val
>> 24);
376 out_le16(addr
, val
>> 16);
387 /* This provides legacy IO or memory mmap access on a bus */
388 int pci_mmap_legacy_page_range(struct pci_bus
*bus
,
389 struct vm_area_struct
*vma
,
390 enum pci_mmap_state mmap_state
)
392 struct pci_controller
*hose
= pci_bus_to_host(bus
);
393 resource_size_t offset
=
394 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
395 resource_size_t size
= vma
->vm_end
- vma
->vm_start
;
398 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
399 pci_domain_nr(bus
), bus
->number
,
400 mmap_state
== pci_mmap_mem
? "MEM" : "IO",
401 (unsigned long long)offset
,
402 (unsigned long long)(offset
+ size
- 1));
404 if (mmap_state
== pci_mmap_mem
) {
407 * Because X is lame and can fail starting if it gets an error
408 * trying to mmap legacy_mem (instead of just moving on without
409 * legacy memory access) we fake it here by giving it anonymous
410 * memory, effectively behaving just like /dev/zero
412 if ((offset
+ size
) > hose
->isa_mem_size
) {
414 pr_debug("Process %s (pid:%d) mapped non-existing PCI",
415 current
->comm
, current
->pid
);
416 pr_debug("legacy memory for 0%04x:%02x\n",
417 pci_domain_nr(bus
), bus
->number
);
419 if (vma
->vm_flags
& VM_SHARED
)
420 return shmem_zero_setup(vma
);
423 offset
+= hose
->isa_mem_phys
;
425 unsigned long io_offset
= (unsigned long)hose
->io_base_virt
-
427 unsigned long roffset
= offset
+ io_offset
;
428 rp
= &hose
->io_resource
;
429 if (!(rp
->flags
& IORESOURCE_IO
))
431 if (roffset
< rp
->start
|| (roffset
+ size
) > rp
->end
)
433 offset
+= hose
->io_base_phys
;
435 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset
);
437 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
438 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
439 return remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
440 vma
->vm_end
- vma
->vm_start
,
444 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
445 const struct resource
*rsrc
,
446 resource_size_t
*start
, resource_size_t
*end
)
448 struct pci_bus_region region
;
450 if (rsrc
->flags
& IORESOURCE_IO
) {
451 pcibios_resource_to_bus(dev
->bus
, ®ion
,
452 (struct resource
*) rsrc
);
453 *start
= region
.start
;
458 /* We pass a CPU physical address to userland for MMIO instead of a
459 * BAR value because X is lame and expects to be able to use that
460 * to pass to /dev/mem!
462 * That means we may have 64-bit values where some apps only expect
463 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
465 *start
= rsrc
->start
;
470 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
471 * @hose: newly allocated pci_controller to be setup
472 * @dev: device node of the host bridge
473 * @primary: set if primary bus (32 bits only, soon to be deprecated)
475 * This function will parse the "ranges" property of a PCI host bridge device
476 * node and setup the resource mapping of a pci controller based on its
479 * Life would be boring if it wasn't for a few issues that we have to deal
482 * - We can only cope with one IO space range and up to 3 Memory space
483 * ranges. However, some machines (thanks Apple !) tend to split their
484 * space into lots of small contiguous ranges. So we have to coalesce.
486 * - We can only cope with all memory ranges having the same offset
487 * between CPU addresses and PCI addresses. Unfortunately, some bridges
488 * are setup for a large 1:1 mapping along with a small "window" which
489 * maps PCI address 0 to some arbitrary high address of the CPU space in
490 * order to give access to the ISA memory hole.
491 * The way out of here that I've chosen for now is to always set the
492 * offset based on the first resource found, then override it if we
493 * have a different offset and the previous was set by an ISA hole.
495 * - Some busses have IO space not starting at 0, which causes trouble with
496 * the way we do our IO resource renumbering. The code somewhat deals with
497 * it for 64 bits but I would expect problems on 32 bits.
499 * - Some 32 bits platforms such as 4xx can have physical space larger than
500 * 32 bits so we need to use 64 bits values for the parsing
502 void pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
503 struct device_node
*dev
, int primary
)
505 int memno
= 0, isa_hole
= -1;
506 unsigned long long isa_mb
= 0;
507 struct resource
*res
;
508 struct of_pci_range range
;
509 struct of_pci_range_parser parser
;
511 pr_info("PCI host bridge %pOF %s ranges:\n",
512 dev
, primary
? "(primary)" : "");
514 /* Check for ranges property */
515 if (of_pci_range_parser_init(&parser
, dev
))
518 pr_debug("Parsing ranges property...\n");
519 for_each_of_pci_range(&parser
, &range
) {
520 /* Read next ranges element */
521 pr_debug("pci_space: 0x%08x pci_addr:0x%016llx ",
522 range
.pci_space
, range
.pci_addr
);
523 pr_debug("cpu_addr:0x%016llx size:0x%016llx\n",
524 range
.cpu_addr
, range
.size
);
526 /* If we failed translation or got a zero-sized region
527 * (some FW try to feed us with non sensical zero sized regions
528 * such as power3 which look like some kind of attempt
529 * at exposing the VGA memory hole)
531 if (range
.cpu_addr
== OF_BAD_ADDR
|| range
.size
== 0)
534 /* Act based on address space type */
536 switch (range
.flags
& IORESOURCE_TYPE_BITS
) {
538 pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n",
539 range
.cpu_addr
, range
.cpu_addr
+ range
.size
- 1,
542 /* We support only one IO range */
543 if (hose
->pci_io_size
) {
544 pr_info(" \\--> Skipped (too many) !\n");
547 /* On 32 bits, limit I/O space to 16MB */
548 if (range
.size
> 0x01000000)
549 range
.size
= 0x01000000;
551 /* 32 bits needs to map IOs here */
552 hose
->io_base_virt
= ioremap(range
.cpu_addr
,
555 /* Expect trouble if pci_addr is not 0 */
558 (unsigned long)hose
->io_base_virt
;
559 /* pci_io_size and io_base_phys always represent IO
560 * space starting at 0 so we factor in pci_addr
562 hose
->pci_io_size
= range
.pci_addr
+ range
.size
;
563 hose
->io_base_phys
= range
.cpu_addr
- range
.pci_addr
;
566 res
= &hose
->io_resource
;
567 range
.cpu_addr
= range
.pci_addr
;
571 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
572 range
.cpu_addr
, range
.cpu_addr
+ range
.size
- 1,
574 (range
.pci_space
& 0x40000000) ?
577 /* We support only 3 memory ranges */
579 pr_info(" \\--> Skipped (too many) !\n");
582 /* Handles ISA memory hole space here */
583 if (range
.pci_addr
== 0) {
584 isa_mb
= range
.cpu_addr
;
586 if (primary
|| isa_mem_base
== 0)
587 isa_mem_base
= range
.cpu_addr
;
588 hose
->isa_mem_phys
= range
.cpu_addr
;
589 hose
->isa_mem_size
= range
.size
;
592 /* We get the PCI/Mem offset from the first range or
593 * the, current one if the offset came from an ISA
594 * hole. If they don't match, bugger.
597 (isa_hole
>= 0 && range
.pci_addr
!= 0 &&
598 hose
->pci_mem_offset
== isa_mb
))
599 hose
->pci_mem_offset
= range
.cpu_addr
-
601 else if (range
.pci_addr
!= 0 &&
602 hose
->pci_mem_offset
!= range
.cpu_addr
-
604 pr_info(" \\--> Skipped (offset mismatch) !\n");
609 res
= &hose
->mem_resources
[memno
++];
613 res
->name
= dev
->full_name
;
614 res
->flags
= range
.flags
;
615 res
->start
= range
.cpu_addr
;
616 res
->end
= range
.cpu_addr
+ range
.size
- 1;
617 res
->parent
= res
->child
= res
->sibling
= NULL
;
621 /* If there's an ISA hole and the pci_mem_offset is -not- matching
622 * the ISA hole offset, then we need to remove the ISA hole from
623 * the resource list for that brige
625 if (isa_hole
>= 0 && hose
->pci_mem_offset
!= isa_mb
) {
626 unsigned int next
= isa_hole
+ 1;
627 pr_info(" Removing ISA hole at 0x%016llx\n", isa_mb
);
629 memmove(&hose
->mem_resources
[isa_hole
],
630 &hose
->mem_resources
[next
],
631 sizeof(struct resource
) * (memno
- next
));
632 hose
->mem_resources
[--memno
].flags
= 0;
636 /* Display the domain number in /proc */
637 int pci_proc_domain(struct pci_bus
*bus
)
639 return pci_domain_nr(bus
);
642 /* This header fixup will do the resource fixup for all devices as they are
643 * probed, but not for bridge ranges
645 static void pcibios_fixup_resources(struct pci_dev
*dev
)
647 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
651 pr_err("No host bridge for PCI dev %s !\n",
655 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
656 struct resource
*res
= dev
->resource
+ i
;
659 if (res
->start
== 0) {
660 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]",
662 (unsigned long long)res
->start
,
663 (unsigned long long)res
->end
,
664 (unsigned int)res
->flags
);
665 pr_debug("is unassigned\n");
666 res
->end
-= res
->start
;
668 res
->flags
|= IORESOURCE_UNSET
;
672 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
674 (unsigned long long)res
->start
,
675 (unsigned long long)res
->end
,
676 (unsigned int)res
->flags
);
679 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, pcibios_fixup_resources
);
682 * We need to avoid collisions with `mirrored' VGA ports
683 * and other strange ISA hardware, so we always want the
684 * addresses to be allocated in the 0x000-0x0ff region
687 * Why? Because some silly external IO cards only decode
688 * the low 10 bits of the IO address. The 0x00-0xff region
689 * is reserved for motherboard devices that decode all 16
690 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
691 * but we want to try to avoid allocating at 0x2900-0x2bff
692 * which might have be mirrored at 0x0100-0x03ff..
694 int pcibios_add_device(struct pci_dev
*dev
)
696 dev
->irq
= of_irq_parse_and_map_pci(dev
, 0, 0);
700 EXPORT_SYMBOL(pcibios_add_device
);
703 * Reparent resource children of pr that conflict with res
704 * under res, and make res replace those children.
706 static int __init
reparent_resources(struct resource
*parent
,
707 struct resource
*res
)
709 struct resource
*p
, **pp
;
710 struct resource
**firstpp
= NULL
;
712 for (pp
= &parent
->child
; (p
= *pp
) != NULL
; pp
= &p
->sibling
) {
713 if (p
->end
< res
->start
)
715 if (res
->end
< p
->start
)
717 if (p
->start
< res
->start
|| p
->end
> res
->end
)
718 return -1; /* not completely contained */
723 return -1; /* didn't find any conflicting entries? */
724 res
->parent
= parent
;
725 res
->child
= *firstpp
;
729 for (p
= res
->child
; p
!= NULL
; p
= p
->sibling
) {
731 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
733 (unsigned long long)p
->start
,
734 (unsigned long long)p
->end
, res
->name
);
740 * Handle resources of PCI devices. If the world were perfect, we could
741 * just allocate all the resource regions and do nothing more. It isn't.
742 * On the other hand, we cannot just re-allocate all devices, as it would
743 * require us to know lots of host bridge internals. So we attempt to
744 * keep as much of the original configuration as possible, but tweak it
745 * when it's found to be wrong.
747 * Known BIOS problems we have to work around:
748 * - I/O or memory regions not configured
749 * - regions configured, but not enabled in the command register
750 * - bogus I/O addresses above 64K used
751 * - expansion ROMs left enabled (this may sound harmless, but given
752 * the fact the PCI specs explicitly allow address decoders to be
753 * shared between expansion ROMs and other resource regions, it's
754 * at least dangerous)
757 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
758 * This gives us fixed barriers on where we can allocate.
759 * (2) Allocate resources for all enabled devices. If there is
760 * a collision, just mark the resource as unallocated. Also
761 * disable expansion ROMs during this step.
762 * (3) Try to allocate resources for disabled devices. If the
763 * resources were assigned correctly, everything goes well,
764 * if they weren't, they won't disturb allocation of other
766 * (4) Assign new addresses to resources which were either
767 * not configured at all or misconfigured. If explicitly
768 * requested by the user, configure expansion ROM address
772 static void pcibios_allocate_bus_resources(struct pci_bus
*bus
)
776 struct resource
*res
, *pr
;
778 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
779 pci_domain_nr(bus
), bus
->number
);
781 pci_bus_for_each_resource(bus
, res
, i
) {
782 if (!res
|| !res
->flags
783 || res
->start
> res
->end
|| res
->parent
)
785 if (bus
->parent
== NULL
)
786 pr
= (res
->flags
& IORESOURCE_IO
) ?
787 &ioport_resource
: &iomem_resource
;
789 /* Don't bother with non-root busses when
790 * re-assigning all resources. We clear the
791 * resource flags as if they were colliding
792 * and as such ensure proper re-allocation
795 pr
= pci_find_parent_resource(bus
->self
, res
);
797 /* this happens when the generic PCI
798 * code (wrongly) decides that this
799 * bridge is transparent -- paulus
805 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ",
806 bus
->self
? pci_name(bus
->self
) : "PHB",
808 (unsigned long long)res
->start
,
809 (unsigned long long)res
->end
);
810 pr_debug("[0x%x], parent %p (%s)\n",
811 (unsigned int)res
->flags
,
812 pr
, (pr
&& pr
->name
) ? pr
->name
: "nil");
814 if (pr
&& !(pr
->flags
& IORESOURCE_UNSET
)) {
815 struct pci_dev
*dev
= bus
->self
;
817 if (request_resource(pr
, res
) == 0)
820 * Must be a conflict with an existing entry.
821 * Move that entry (or entries) under the
822 * bridge resource and try again.
824 if (reparent_resources(pr
, res
) == 0)
827 if (dev
&& i
< PCI_BRIDGE_RESOURCE_NUM
&&
828 pci_claim_bridge_resource(dev
,
829 i
+ PCI_BRIDGE_RESOURCES
) == 0)
833 pr_warn("PCI: Cannot allocate resource region ");
834 pr_cont("%d of PCI bridge %d, will remap\n", i
, bus
->number
);
835 res
->start
= res
->end
= 0;
839 list_for_each_entry(b
, &bus
->children
, node
)
840 pcibios_allocate_bus_resources(b
);
843 static inline void alloc_resource(struct pci_dev
*dev
, int idx
)
845 struct resource
*pr
, *r
= &dev
->resource
[idx
];
847 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
849 (unsigned long long)r
->start
,
850 (unsigned long long)r
->end
,
851 (unsigned int)r
->flags
);
853 pr
= pci_find_parent_resource(dev
, r
);
854 if (!pr
|| (pr
->flags
& IORESOURCE_UNSET
) ||
855 request_resource(pr
, r
) < 0) {
856 pr_warn("PCI: Cannot allocate resource region %d ", idx
);
857 pr_cont("of device %s, will remap\n", pci_name(dev
));
859 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
861 (unsigned long long)pr
->start
,
862 (unsigned long long)pr
->end
,
863 (unsigned int)pr
->flags
);
864 /* We'll assign a new address later */
865 r
->flags
|= IORESOURCE_UNSET
;
871 static void __init
pcibios_allocate_resources(int pass
)
873 struct pci_dev
*dev
= NULL
;
878 for_each_pci_dev(dev
) {
879 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
880 for (idx
= 0; idx
<= PCI_ROM_RESOURCE
; idx
++) {
881 r
= &dev
->resource
[idx
];
882 if (r
->parent
) /* Already allocated */
884 if (!r
->flags
|| (r
->flags
& IORESOURCE_UNSET
))
885 continue; /* Not assigned at all */
886 /* We only allocate ROMs on pass 1 just in case they
887 * have been screwed up by firmware
889 if (idx
== PCI_ROM_RESOURCE
)
891 if (r
->flags
& IORESOURCE_IO
)
892 disabled
= !(command
& PCI_COMMAND_IO
);
894 disabled
= !(command
& PCI_COMMAND_MEMORY
);
895 if (pass
== disabled
)
896 alloc_resource(dev
, idx
);
900 r
= &dev
->resource
[PCI_ROM_RESOURCE
];
902 /* Turn the ROM off, leave the resource region,
903 * but keep it unregistered.
906 pci_read_config_dword(dev
, dev
->rom_base_reg
, ®
);
907 if (reg
& PCI_ROM_ADDRESS_ENABLE
) {
908 pr_debug("PCI: Switching off ROM of %s\n",
910 r
->flags
&= ~IORESOURCE_ROM_ENABLE
;
911 pci_write_config_dword(dev
, dev
->rom_base_reg
,
912 reg
& ~PCI_ROM_ADDRESS_ENABLE
);
918 static void __init
pcibios_reserve_legacy_regions(struct pci_bus
*bus
)
920 struct pci_controller
*hose
= pci_bus_to_host(bus
);
921 resource_size_t offset
;
922 struct resource
*res
, *pres
;
925 pr_debug("Reserving legacy ranges for domain %04x\n",
929 if (!(hose
->io_resource
.flags
& IORESOURCE_IO
))
931 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
932 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
934 res
->name
= "Legacy IO";
935 res
->flags
= IORESOURCE_IO
;
937 res
->end
= (offset
+ 0xfff) & 0xfffffffful
;
938 pr_debug("Candidate legacy IO: %pR\n", res
);
939 if (request_resource(&hose
->io_resource
, res
)) {
940 pr_debug("PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
941 pci_domain_nr(bus
), bus
->number
, res
);
946 /* Check for memory */
947 offset
= hose
->pci_mem_offset
;
948 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset
);
949 for (i
= 0; i
< 3; i
++) {
950 pres
= &hose
->mem_resources
[i
];
951 if (!(pres
->flags
& IORESOURCE_MEM
))
953 pr_debug("hose mem res: %pR\n", pres
);
954 if ((pres
->start
- offset
) <= 0xa0000 &&
955 (pres
->end
- offset
) >= 0xbffff)
960 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
962 res
->name
= "Legacy VGA memory";
963 res
->flags
= IORESOURCE_MEM
;
964 res
->start
= 0xa0000 + offset
;
965 res
->end
= 0xbffff + offset
;
966 pr_debug("Candidate VGA memory: %pR\n", res
);
967 if (request_resource(pres
, res
)) {
968 pr_debug("PCI %04x:%02x Cannot reserve VGA memory %pR\n",
969 pci_domain_nr(bus
), bus
->number
, res
);
974 void __init
pcibios_resource_survey(void)
978 /* Allocate and assign resources. If we re-assign everything, then
979 * we skip the allocate phase
981 list_for_each_entry(b
, &pci_root_buses
, node
)
982 pcibios_allocate_bus_resources(b
);
984 pcibios_allocate_resources(0);
985 pcibios_allocate_resources(1);
987 /* Before we start assigning unassigned resource, we try to reserve
988 * the low IO area and the VGA memory area if they intersect the
989 * bus available resources to avoid allocating things on top of them
991 list_for_each_entry(b
, &pci_root_buses
, node
)
992 pcibios_reserve_legacy_regions(b
);
994 /* Now proceed to assigning things that were left unassigned */
995 pr_debug("PCI: Assigning unassigned resources...\n");
996 pci_assign_unassigned_resources();
999 /* This is used by the PCI hotplug driver to allocate resource
1000 * of newly plugged busses. We can try to consolidate with the
1001 * rest of the code later, for now, keep it as-is as our main
1002 * resource allocation function doesn't deal with sub-trees yet.
1004 void pcibios_claim_one_bus(struct pci_bus
*bus
)
1006 struct pci_dev
*dev
;
1007 struct pci_bus
*child_bus
;
1009 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1012 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
1013 struct resource
*r
= &dev
->resource
[i
];
1015 if (r
->parent
|| !r
->start
|| !r
->flags
)
1018 pr_debug("PCI: Claiming %s: ", pci_name(dev
));
1019 pr_debug("Resource %d: %016llx..%016llx [%x]\n",
1020 i
, (unsigned long long)r
->start
,
1021 (unsigned long long)r
->end
,
1022 (unsigned int)r
->flags
);
1024 if (pci_claim_resource(dev
, i
) == 0)
1027 pci_claim_bridge_resource(dev
, i
);
1031 list_for_each_entry(child_bus
, &bus
->children
, node
)
1032 pcibios_claim_one_bus(child_bus
);
1034 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus
);
1037 /* pcibios_finish_adding_to_bus
1039 * This is to be called by the hotplug code after devices have been
1040 * added to a bus, this include calling it for a PHB that is just
1043 void pcibios_finish_adding_to_bus(struct pci_bus
*bus
)
1045 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1046 pci_domain_nr(bus
), bus
->number
);
1048 /* Allocate bus and devices resources */
1049 pcibios_allocate_bus_resources(bus
);
1050 pcibios_claim_one_bus(bus
);
1052 /* Add new devices to global lists. Register in proc, sysfs. */
1053 pci_bus_add_devices(bus
);
1056 /* eeh_add_device_tree_late(bus); */
1058 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus
);
1060 static void pcibios_setup_phb_resources(struct pci_controller
*hose
,
1061 struct list_head
*resources
)
1063 unsigned long io_offset
;
1064 struct resource
*res
;
1067 /* Hookup PHB IO resource */
1068 res
= &hose
->io_resource
;
1070 /* Fixup IO space offset */
1071 io_offset
= (unsigned long)hose
->io_base_virt
- isa_io_base
;
1072 res
->start
= (res
->start
+ io_offset
) & 0xffffffffu
;
1073 res
->end
= (res
->end
+ io_offset
) & 0xffffffffu
;
1076 pr_warn("PCI: I/O resource not set for host ");
1077 pr_cont("bridge %pOF (domain %d)\n",
1078 hose
->dn
, hose
->global_number
);
1079 /* Workaround for lack of IO resource only on 32-bit */
1080 res
->start
= (unsigned long)hose
->io_base_virt
- isa_io_base
;
1081 res
->end
= res
->start
+ IO_SPACE_LIMIT
;
1082 res
->flags
= IORESOURCE_IO
;
1084 pci_add_resource_offset(resources
, res
,
1085 (__force resource_size_t
)(hose
->io_base_virt
- _IO_BASE
));
1087 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1088 (unsigned long long)res
->start
,
1089 (unsigned long long)res
->end
,
1090 (unsigned long)res
->flags
);
1092 /* Hookup PHB Memory resources */
1093 for (i
= 0; i
< 3; ++i
) {
1094 res
= &hose
->mem_resources
[i
];
1098 pr_err("PCI: Memory resource 0 not set for ");
1099 pr_cont("host bridge %pOF (domain %d)\n",
1100 hose
->dn
, hose
->global_number
);
1102 /* Workaround for lack of MEM resource only on 32-bit */
1103 res
->start
= hose
->pci_mem_offset
;
1104 res
->end
= (resource_size_t
)-1LL;
1105 res
->flags
= IORESOURCE_MEM
;
1108 pci_add_resource_offset(resources
, res
, hose
->pci_mem_offset
);
1110 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
1111 i
, (unsigned long long)res
->start
,
1112 (unsigned long long)res
->end
,
1113 (unsigned long)res
->flags
);
1116 pr_debug("PCI: PHB MEM offset = %016llx\n",
1117 (unsigned long long)hose
->pci_mem_offset
);
1118 pr_debug("PCI: PHB IO offset = %08lx\n",
1119 (unsigned long)hose
->io_base_virt
- _IO_BASE
);
1122 static void pcibios_scan_phb(struct pci_controller
*hose
)
1124 LIST_HEAD(resources
);
1125 struct pci_bus
*bus
;
1126 struct device_node
*node
= hose
->dn
;
1128 pr_debug("PCI: Scanning PHB %pOF\n", node
);
1130 pcibios_setup_phb_resources(hose
, &resources
);
1132 bus
= pci_scan_root_bus(hose
->parent
, hose
->first_busno
,
1133 hose
->ops
, hose
, &resources
);
1135 pr_err("Failed to create bus for PCI domain %04x\n",
1136 hose
->global_number
);
1137 pci_free_resource_list(&resources
);
1140 bus
->busn_res
.start
= hose
->first_busno
;
1143 hose
->last_busno
= bus
->busn_res
.end
;
1146 static int __init
pcibios_init(void)
1148 struct pci_controller
*hose
, *tmp
;
1151 pr_info("PCI: Probing PCI hardware\n");
1153 /* Scan all of the recorded PCI controllers. */
1154 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
1155 hose
->last_busno
= 0xff;
1156 pcibios_scan_phb(hose
);
1157 if (next_busno
<= hose
->last_busno
)
1158 next_busno
= hose
->last_busno
+ 1;
1160 pci_bus_count
= next_busno
;
1162 /* Call common code to handle resource allocation */
1163 pcibios_resource_survey();
1164 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
1166 pci_bus_add_devices(hose
->bus
);
1172 subsys_initcall(pcibios_init
);
1174 static struct pci_controller
*pci_bus_to_hose(int bus
)
1176 struct pci_controller
*hose
, *tmp
;
1178 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
1179 if (bus
>= hose
->first_busno
&& bus
<= hose
->last_busno
)
1184 /* Provide information on locations of various I/O regions in physical
1185 * memory. Do this on a per-card basis so that we choose the right
1187 * Note that the returned IO or memory base is a physical address
1190 long sys_pciconfig_iobase(long which
, unsigned long bus
, unsigned long devfn
)
1192 struct pci_controller
*hose
;
1193 long result
= -EOPNOTSUPP
;
1195 hose
= pci_bus_to_hose(bus
);
1200 case IOBASE_BRIDGE_NUMBER
:
1201 return (long)hose
->first_busno
;
1203 return (long)hose
->pci_mem_offset
;
1205 return (long)hose
->io_base_phys
;
1207 return (long)isa_io_base
;
1208 case IOBASE_ISA_MEM
:
1209 return (long)isa_mem_base
;
1216 * Null PCI config access functions, for the case when we can't
1219 #define NULL_PCI_OP(rw, size, type) \
1221 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1223 return PCIBIOS_DEVICE_NOT_FOUND; \
1227 null_read_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1230 return PCIBIOS_DEVICE_NOT_FOUND
;
1234 null_write_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1237 return PCIBIOS_DEVICE_NOT_FOUND
;
1240 static struct pci_ops null_pci_ops
= {
1241 .read
= null_read_config
,
1242 .write
= null_write_config
,
1246 * These functions are used early on before PCI scanning is done
1247 * and all of the pci_dev and pci_bus structures have been created.
1249 static struct pci_bus
*
1250 fake_pci_bus(struct pci_controller
*hose
, int busnr
)
1252 static struct pci_bus bus
;
1255 pr_err("Can't find hose for PCI bus %d!\n", busnr
);
1259 bus
.ops
= hose
? hose
->ops
: &null_pci_ops
;
1263 #define EARLY_PCI_OP(rw, size, type) \
1264 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1265 int devfn, int offset, type value) \
1267 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1268 devfn, offset, value); \
1271 EARLY_PCI_OP(read
, byte
, u8
*)
1272 EARLY_PCI_OP(read
, word
, u16
*)
1273 EARLY_PCI_OP(read
, dword
, u32
*)
1274 EARLY_PCI_OP(write
, byte
, u8
)
1275 EARLY_PCI_OP(write
, word
, u16
)
1276 EARLY_PCI_OP(write
, dword
, u32
)
1278 int early_find_capability(struct pci_controller
*hose
, int bus
, int devfn
,
1281 return pci_bus_find_capability(fake_pci_bus(hose
, bus
), devfn
, cap
);