1 /* This file is subject to the terms and conditions of the GNU General Public
2 * License. See the file "COPYING" in the main directory of this archive
5 * Copyright (C) 1999-2007 by Helge Deller <deller@gmx.de>
6 * Copyright 1999 SuSE GmbH (Philipp Rumpf)
7 * Copyright 1999 Philipp Rumpf (prumpf@tux.org)
8 * Copyright 2000 Hewlett Packard (Paul Bame, bame@puffin.external.hp.com)
9 * Copyright (C) 2001 Grant Grundler (Hewlett Packard)
10 * Copyright (C) 2004 Kyle McMartin <kyle@debian.org>
12 * Initial Version 04-23-1999 by Helge Deller <deller@gmx.de>
15 #include <asm/asm-offsets.h>
19 #include <asm/assembly.h>
20 #include <asm/pgtable.h>
22 #include <linux/linkage.h>
23 #include <linux/init.h>
38 .import init_thread_union,data
39 .import fault_vector_20,code /* IVA parisc 2.0 32 bit */
41 .import fault_vector_11,code /* IVA parisc 1.1 32 bit */
42 .import $global$ /* forward declaration */
43 #endif /*!CONFIG_64BIT*/
44 ENTRY(parisc_kernel_start)
48 /* Make sure sr4-sr7 are set to zero for the kernel address space */
54 /* Clear BSS (shouldn't the boot loader do this?) */
56 .import __bss_start,data
57 .import __bss_stop,data
59 load32 PA(__bss_start),%r3
60 load32 PA(__bss_stop),%r4
62 cmpb,<<,n %r3,%r4,$bss_loop
65 /* Save away the arguments the boot loader passed in (32 bit args) */
66 load32 PA(boot_args),%r1
72 /* Initialize startup VM. Just map first 16/32 MB of memory */
73 load32 PA(swapper_pg_dir),%r4
74 mtctl %r4,%cr24 /* Initialize kernel root pointer */
75 mtctl %r4,%cr25 /* Initialize user root pointer */
77 #if CONFIG_PGTABLE_LEVELS == 3
80 shrd %r5,PxD_VALUE_SHIFT,%r3
81 ldo (PxD_FLAG_PRESENT+PxD_FLAG_VALID)(%r3),%r3
82 stw %r3,ASM_PGD_ENTRY*ASM_PGD_ENTRY_SIZE(%r4)
83 ldo ASM_PMD_ENTRY*ASM_PMD_ENTRY_SIZE(%r5),%r4
85 /* 2-level page table, so pmd == pgd */
86 ldo ASM_PGD_ENTRY*ASM_PGD_ENTRY_SIZE(%r4),%r4
89 /* Fill in pmd with enough pte directories */
91 SHRREG %r1,PxD_VALUE_SHIFT,%r3
92 ldo (PxD_FLAG_PRESENT+PxD_FLAG_VALID)(%r3),%r3
94 ldi ASM_PT_INITIAL,%r1
98 ldo (PAGE_SIZE >> PxD_VALUE_SHIFT)(%r3),%r3
100 #if CONFIG_PGTABLE_LEVELS == 3
101 ldo ASM_PMD_ENTRY_SIZE(%r4),%r4
103 ldo ASM_PGD_ENTRY_SIZE(%r4),%r4
107 /* Now initialize the PTEs themselves. We use RWX for
108 * everything ... it will get remapped correctly later */
109 ldo 0+_PAGE_KERNEL_RWX(%r0),%r3 /* Hardwired 0 phys addr start */
110 load32 (1<<(KERNEL_INITIAL_ORDER-PAGE_SHIFT)),%r11 /* PFN count */
114 STREGM %r3,ASM_PTE_ENTRY_SIZE(%r1)
115 ldo (1<<PFN_PTE_SHIFT)(%r3),%r3 /* add one PFN */
116 addib,> -1,%r11,$pgt_fill_loop
119 /* Load the return address...er...crash 'n burn */
122 /* And the RFI Target address too */
123 load32 start_parisc,%r11
125 /* And the initial task pointer */
126 load32 init_thread_union,%r6
129 /* And the stack pointer too */
130 ldo THREAD_SZ_ALGN(%r6),%sp
132 #if defined(CONFIG_64BIT) && defined(CONFIG_FUNCTION_TRACER)
134 /* initialize mcount FPTR */
135 /* Get the global data pointer */
137 load32 PA(_mcount), %r10
142 /* Set the smp rendezvous address into page zero.
143 ** It would be safer to do this in init_smp_config() but
144 ** it's just way easier to deal with here because
145 ** of 64-bit function ptrs and the address is local to this file.
147 load32 PA(smp_slave_stext),%r10
148 stw %r10,0x10(%r0) /* MEM_RENDEZ */
149 stw %r0,0x28(%r0) /* MEM_RENDEZ_HI - assume addr < 4GB */
155 ** Code Common to both Monarch and Slave processors.
159 ** %r11 must contain RFI target address.
160 ** %r25/%r26 args to pass to target function
161 ** %r2 in case rfi target decides it didn't like something
164 ** %r3 PDCE_PROC address
165 ** %r11 RFI target address
167 ** Caller must init: SR4-7, %sp, %r10, %cr24/25,
173 /* Clear PDC entry point - we won't use it */
174 stw %r0,0x10(%r0) /* MEM_RENDEZ */
175 stw %r0,0x28(%r0) /* MEM_RENDEZ_HI */
176 #endif /*CONFIG_SMP*/
181 /* Save the rfi target address */
182 ldd TI_TASK-THREAD_SZ_ALGN(%sp), %r10
184 std %r11, TASK_PT_GR11(%r10)
185 /* Switch to wide mode Superdome doesn't support narrow PDC
188 1: mfia %rp /* clear upper part of pcoq */
194 /* Set Wide mode as the "Default" (eg for traps)
195 ** First trap occurs *right* after (or part of) rfi for slave CPUs.
196 ** Someday, palo might not do this for the Monarch either.
199 #define MEM_PDC_LO 0x388
200 #define MEM_PDC_HI 0x35C
201 ldw MEM_PDC_LO(%r0),%r3
202 ldw MEM_PDC_HI(%r0),%r6
203 depd %r6, 31, 32, %r3 /* move to upper word */
205 mfctl %cr30,%r6 /* PCX-W2 firmware bug */
207 ldo PDC_PSW(%r0),%arg0 /* 21 */
208 ldo PDC_PSW_SET_DEFAULTS(%r0),%arg1 /* 2 */
209 ldo PDC_PSW_WIDE_BIT(%r0),%arg2 /* 2 */
210 load32 PA(stext_pdc_ret), %rp
215 mtctl %r6,%cr30 /* restore task thread info */
217 /* restore rfi target address*/
218 ldd TI_TASK-THREAD_SZ_ALGN(%sp), %r10
220 ldd TASK_PT_GR11(%r10), %r11
224 /* PARANOID: clear user scratch/user space SR's */
230 /* Initialize Protection Registers */
236 /* Initialize the global data pointer */
239 /* Set up our interrupt table. HPMCs might not work after this!
241 * We need to install the correct iva for PA1.1 or PA2.0. The
242 * following short sequence of instructions can determine this
243 * (without being illegal on a PA1.1 machine).
251 comib,<>,n 0,%r10,$is_pa20
252 ldil L%PA(fault_vector_11),%r10
254 ldo R%PA(fault_vector_11)(%r10),%r10
257 .level PA_ASM_LEVEL /* restore 1.1 || 2.0w */
258 #endif /*!CONFIG_64BIT*/
259 load32 PA(fault_vector_20),%r10
264 b aligned_rfi /* Prepare to RFI! Man all the cannons! */
271 rsm PSW_SM_QUIET,%r0 /* off troublesome PSW bits */
272 /* Don't need NOPs, have 8 compliant insn before rfi */
274 mtctl %r0,%cr17 /* Clear IIASQ tail */
275 mtctl %r0,%cr17 /* Clear IIASQ head */
277 /* Load RFI target into PC queue */
278 mtctl %r11,%cr18 /* IIAOQ head */
280 mtctl %r11,%cr18 /* IIAOQ tail */
282 load32 KERNEL_PSW,%r10
285 /* Jump through hyperspace to Virt Mode */
293 .import smp_init_current_idle_task,data
294 .import smp_callin,code
300 break 1,1 /* Break if returned from start_secondary */
304 #endif /*!CONFIG_64BIT*/
306 /***************************************************************************
307 * smp_slave_stext is executed by all non-monarch Processors when the Monarch
308 * pokes the slave CPUs in smp.c:smp_boot_cpus().
310 * Once here, registers values are initialized in order to branch to virtual
311 * mode. Once all available/eligible CPUs are in virtual mode, all are
312 * released and start out by executing their own idle task.
313 *****************************************************************************/
319 ** Initialize Space registers
326 /* Initialize the SP - monarch sets up smp_init_current_idle_task */
327 load32 PA(smp_init_current_idle_task),%sp
328 LDREG 0(%sp),%sp /* load task address */
330 LDREG TASK_THREAD_INFO(%sp),%sp
331 mtctl %sp,%cr30 /* store in cr30 */
332 ldo THREAD_SZ_ALGN(%sp),%sp
334 /* point CPU to kernel page tables */
335 load32 PA(swapper_pg_dir),%r4
336 mtctl %r4,%cr24 /* Initialize kernel root pointer */
337 mtctl %r4,%cr25 /* Initialize user root pointer */
340 /* Setup PDCE_PROC entry */
343 /* Load RFI *return* address in case smp_callin bails */
344 load32 smp_callin_rtn,%r2
347 /* Load RFI target address. */
348 load32 smp_callin,%r11
350 /* ok...common code can handle the rest */
355 #endif /* CONFIG_SMP */
357 ENDPROC(parisc_kernel_start)
360 .section .data..read_mostly
363 .export $global$,data
365 .type $global$,@object
369 #endif /*!CONFIG_64BIT*/