2 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
4 * Floating-point emulation code
5 * Copyright (C) 2001 Hewlett-Packard (Paul Bame) <bame@debian.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2, or (at your option)
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 * @(#) pa/fp/fpudispatch.c $Revision: 1.1 $
28 * <<please update with a synopsis of the functionality provided by this file>>
30 * External Interfaces:
31 * <<the following list was autogenerated, please review>>
32 * emfpudispatch(ir, dummy1, dummy2, fpregs)
33 * fpudispatch(ir, excp_code, holder, fpregs)
35 * Internal Interfaces:
36 * <<the following list was autogenerated, please review>>
37 * static u_int decode_06(u_int, u_int *)
38 * static u_int decode_0c(u_int, u_int, u_int, u_int *)
39 * static u_int decode_0e(u_int, u_int, u_int, u_int *)
40 * static u_int decode_26(u_int, u_int *)
41 * static u_int decode_2e(u_int, u_int *)
42 * static void update_status_cbit(u_int *, u_int, u_int, u_int)
45 * <<please update with a overview of the operation of this file>>
53 #include <linux/bug.h>
54 #include <linux/kernel.h>
55 #include <asm/processor.h>
56 /* #include <sys/debug.h> */
57 /* #include <machine/sys/mdep_private.h> */
59 #define COPR_INST 0x30000000
62 * definition of extru macro. If pos and len are constants, the compiler
63 * will generate an extru instruction when optimized
65 #define extru(r,pos,len) (((r) >> (31-(pos))) & (( 1 << (len)) - 1))
66 /* definitions of bit field locations in the instruction */
72 #define fpclass1subpos 16
78 * the following are the extra bits for the 0E major op
86 * the following are for the multi-ops
95 * the following are for the fused FP instructions
105 #define fpfusedsubop 26
109 * offset to constant zero in the FP emulation registers
111 #define fpzeroreg (32*sizeof(double)/sizeof(u_int))
114 * extract the major opcode from the instruction
116 #define get_major(op) extru(op,fpmajorpos,6)
118 * extract the two bit class field from the FP instruction. The class is at bit
121 #define get_class(op) extru(op,fpclasspos,2)
123 * extract the 3 bit subop field. For all but class 1 instructions, it is
124 * located at bit positions 16-18
126 #define get_subop(op) extru(op,fpsubpos,3)
128 * extract the 2 or 3 bit subop field from class 1 instructions. It is located
129 * at bit positions 15-16 (PA1.1) or 14-16 (PA2.0)
131 #define get_subop1_PA1_1(op) extru(op,fpclass1subpos,2) /* PA89 (1.1) fmt */
132 #define get_subop1_PA2_0(op) extru(op,fpclass1subpos,3) /* PA 2.0 fmt */
134 /* definitions of unimplemented exceptions */
135 #define MAJOR_0C_EXCP 0x09
136 #define MAJOR_0E_EXCP 0x0b
137 #define MAJOR_06_EXCP 0x03
138 #define MAJOR_26_EXCP 0x23
139 #define MAJOR_2E_EXCP 0x2b
140 #define PA83_UNIMP_EXCP 0x01
143 * Special Defines for TIMEX specific code
146 #define FPU_TYPE_FLAG_POS (EM_FPU_TYPE_OFFSET>>2)
147 #define TIMEX_ROLEX_FPU_MASK (TIMEX_EXTEN_FLAG|ROLEX_EXTEN_FLAG)
150 * Static function definitions
153 #if defined(_PROTOTYPES) || defined(_lint)
154 static u_int
decode_0c(u_int
, u_int
, u_int
, u_int
*);
155 static u_int
decode_0e(u_int
, u_int
, u_int
, u_int
*);
156 static u_int
decode_06(u_int
, u_int
*);
157 static u_int
decode_26(u_int
, u_int
*);
158 static u_int
decode_2e(u_int
, u_int
*);
159 static void update_status_cbit(u_int
*, u_int
, u_int
, u_int
);
160 #else /* !_PROTOTYPES&&!_lint */
161 static u_int
decode_0c();
162 static u_int
decode_0e();
163 static u_int
decode_06();
164 static u_int
decode_26();
165 static u_int
decode_2e();
166 static void update_status_cbit();
167 #endif /* _PROTOTYPES&&!_lint */
171 static void parisc_linux_get_fpu_type(u_int fpregs
[])
173 /* on pa-linux the fpu type is not filled in by the
174 * caller; it is constructed here
176 if (boot_cpu_data
.cpu_type
== pcxs
)
177 fpregs
[FPU_TYPE_FLAG_POS
] = TIMEX_EXTEN_FLAG
;
178 else if (boot_cpu_data
.cpu_type
== pcxt
||
179 boot_cpu_data
.cpu_type
== pcxt_
)
180 fpregs
[FPU_TYPE_FLAG_POS
] = ROLEX_EXTEN_FLAG
;
181 else if (boot_cpu_data
.cpu_type
>= pcxu
)
182 fpregs
[FPU_TYPE_FLAG_POS
] = PA2_0_FPU_FLAG
;
186 * this routine will decode the excepting floating point instruction and
187 * call the appropriate emulation routine.
188 * It is called by decode_fpu with the following parameters:
189 * fpudispatch(current_ir, unimplemented_code, 0, &Fpu_register)
190 * where current_ir is the instruction to be emulated,
191 * unimplemented_code is the exception_code that the hardware generated
192 * and &Fpu_register is the address of emulated FP reg 0.
195 fpudispatch(u_int ir
, u_int excp_code
, u_int holder
, u_int fpregs
[])
198 u_int fpu_type_flags
;
200 /* All FP emulation code assumes that ints are 4-bytes in length */
201 VASSERT(sizeof(int) == 4);
203 parisc_linux_get_fpu_type(fpregs
);
205 fpu_type_flags
=fpregs
[FPU_TYPE_FLAG_POS
]; /* get fpu type flags */
207 class = get_class(ir
);
209 if (fpu_type_flags
& PA2_0_FPU_FLAG
)
210 subop
= get_subop1_PA2_0(ir
);
212 subop
= get_subop1_PA1_1(ir
);
215 subop
= get_subop(ir
);
217 if (FPUDEBUG
) printk("class %d subop %d\n", class, subop
);
221 case PA83_UNIMP_EXCP
:
222 return(decode_0c(ir
,class,subop
,fpregs
));
224 return(decode_0e(ir
,class,subop
,fpregs
));
226 return(decode_06(ir
,fpregs
));
228 return(decode_26(ir
,fpregs
));
230 return(decode_2e(ir
,fpregs
));
232 /* "crashme Night Gallery painting nr 2. (asm_crash.s).
233 * This was fixed for multi-user kernels, but
234 * workstation kernels had a panic here. This allowed
235 * any arbitrary user to panic the kernel by executing
236 * setting the FP exception registers to strange values
237 * and generating an emulation trap. The emulation and
238 * exception code must never be able to panic the
241 return(UNIMPLEMENTEDEXCEPTION
);
246 * this routine is called by $emulation_trap to emulate a coprocessor
247 * instruction if one doesn't exist
250 emfpudispatch(u_int ir
, u_int dummy1
, u_int dummy2
, u_int fpregs
[])
252 u_int
class, subop
, major
;
253 u_int fpu_type_flags
;
255 /* All FP emulation code assumes that ints are 4-bytes in length */
256 VASSERT(sizeof(int) == 4);
258 fpu_type_flags
=fpregs
[FPU_TYPE_FLAG_POS
]; /* get fpu type flags */
260 major
= get_major(ir
);
261 class = get_class(ir
);
263 if (fpu_type_flags
& PA2_0_FPU_FLAG
)
264 subop
= get_subop1_PA2_0(ir
);
266 subop
= get_subop1_PA1_1(ir
);
269 subop
= get_subop(ir
);
272 return(decode_0c(ir
,class,subop
,fpregs
));
274 return(decode_0e(ir
,class,subop
,fpregs
));
276 return(decode_06(ir
,fpregs
));
278 return(decode_26(ir
,fpregs
));
280 return(decode_2e(ir
,fpregs
));
282 return(PA83_UNIMP_EXCP
);
288 decode_0c(u_int ir
, u_int
class, u_int subop
, u_int fpregs
[])
290 u_int r1
,r2
,t
; /* operand register offsets */
291 u_int fmt
; /* also sf for class 1 conversions */
292 u_int df
; /* for class 1 conversions */
294 u_int retval
, local_status
;
295 u_int fpu_type_flags
;
297 if (ir
== COPR_INST
) {
298 fpregs
[0] = EMULATION_VERSION
<< 11;
301 status
= &fpregs
[0]; /* fp status register */
302 local_status
= fpregs
[0]; /* and local copy */
303 r1
= extru(ir
,fpr1pos
,5) * sizeof(double)/sizeof(u_int
);
304 if (r1
== 0) /* map fr0 source to constant zero */
306 t
= extru(ir
,fptpos
,5) * sizeof(double)/sizeof(u_int
);
307 if (t
== 0 && class != 2) /* don't allow fr0 as a dest */
308 return(MAJOR_0C_EXCP
);
309 fmt
= extru(ir
,fpfmtpos
,2); /* get fmt completer */
314 case 0: /* COPR 0,0 emulated above*/
316 return(MAJOR_0C_EXCP
);
319 case 2: /* illegal */
320 return(MAJOR_0C_EXCP
);
322 t
&= ~3; /* force to even reg #s */
324 fpregs
[t
+3] = fpregs
[r1
+3];
325 fpregs
[t
+2] = fpregs
[r1
+2];
327 fpregs
[t
+1] = fpregs
[r1
+1];
329 fpregs
[t
] = fpregs
[r1
];
334 case 2: /* illegal */
335 return(MAJOR_0C_EXCP
);
337 t
&= ~3; /* force to even reg #s */
339 fpregs
[t
+3] = fpregs
[r1
+3];
340 fpregs
[t
+2] = fpregs
[r1
+2];
342 fpregs
[t
+1] = fpregs
[r1
+1];
344 /* copy and clear sign bit */
345 fpregs
[t
] = fpregs
[r1
] & 0x7fffffff;
350 case 2: /* illegal */
351 return(MAJOR_0C_EXCP
);
353 t
&= ~3; /* force to even reg #s */
355 fpregs
[t
+3] = fpregs
[r1
+3];
356 fpregs
[t
+2] = fpregs
[r1
+2];
358 fpregs
[t
+1] = fpregs
[r1
+1];
360 /* copy and invert sign bit */
361 fpregs
[t
] = fpregs
[r1
] ^ 0x80000000;
364 case 7: /* FNEGABS */
366 case 2: /* illegal */
367 return(MAJOR_0C_EXCP
);
369 t
&= ~3; /* force to even reg #s */
371 fpregs
[t
+3] = fpregs
[r1
+3];
372 fpregs
[t
+2] = fpregs
[r1
+2];
374 fpregs
[t
+1] = fpregs
[r1
+1];
376 /* copy and set sign bit */
377 fpregs
[t
] = fpregs
[r1
] | 0x80000000;
383 return(sgl_fsqrt(&fpregs
[r1
],0,
386 return(dbl_fsqrt(&fpregs
[r1
],0,
389 case 3: /* quad not implemented */
390 return(MAJOR_0C_EXCP
);
395 return(sgl_frnd(&fpregs
[r1
],0,
398 return(dbl_frnd(&fpregs
[r1
],0,
401 case 3: /* quad not implemented */
402 return(MAJOR_0C_EXCP
);
404 } /* end of switch (subop) */
406 case 1: /* class 1 */
407 df
= extru(ir
,fpdfpos
,2); /* get dest format */
408 if ((df
& 2) || (fmt
& 2)) {
410 * fmt's 2 and 3 are illegal of not implemented
413 return(MAJOR_0C_EXCP
);
416 * encode source and dest formats into 2 bits.
417 * high bit is source, low bit is dest.
418 * bit = 1 --> double precision
420 fmt
= (fmt
<< 1) | df
;
424 case 0: /* sgl/sgl */
425 return(MAJOR_0C_EXCP
);
426 case 1: /* sgl/dbl */
427 return(sgl_to_dbl_fcnvff(&fpregs
[r1
],0,
429 case 2: /* dbl/sgl */
430 return(dbl_to_sgl_fcnvff(&fpregs
[r1
],0,
432 case 3: /* dbl/dbl */
433 return(MAJOR_0C_EXCP
);
437 case 0: /* sgl/sgl */
438 return(sgl_to_sgl_fcnvxf(&fpregs
[r1
],0,
440 case 1: /* sgl/dbl */
441 return(sgl_to_dbl_fcnvxf(&fpregs
[r1
],0,
443 case 2: /* dbl/sgl */
444 return(dbl_to_sgl_fcnvxf(&fpregs
[r1
],0,
446 case 3: /* dbl/dbl */
447 return(dbl_to_dbl_fcnvxf(&fpregs
[r1
],0,
452 case 0: /* sgl/sgl */
453 return(sgl_to_sgl_fcnvfx(&fpregs
[r1
],0,
455 case 1: /* sgl/dbl */
456 return(sgl_to_dbl_fcnvfx(&fpregs
[r1
],0,
458 case 2: /* dbl/sgl */
459 return(dbl_to_sgl_fcnvfx(&fpregs
[r1
],0,
461 case 3: /* dbl/dbl */
462 return(dbl_to_dbl_fcnvfx(&fpregs
[r1
],0,
465 case 3: /* FCNVFXT */
467 case 0: /* sgl/sgl */
468 return(sgl_to_sgl_fcnvfxt(&fpregs
[r1
],0,
470 case 1: /* sgl/dbl */
471 return(sgl_to_dbl_fcnvfxt(&fpregs
[r1
],0,
473 case 2: /* dbl/sgl */
474 return(dbl_to_sgl_fcnvfxt(&fpregs
[r1
],0,
476 case 3: /* dbl/dbl */
477 return(dbl_to_dbl_fcnvfxt(&fpregs
[r1
],0,
480 case 5: /* FCNVUF (PA2.0 only) */
482 case 0: /* sgl/sgl */
483 return(sgl_to_sgl_fcnvuf(&fpregs
[r1
],0,
485 case 1: /* sgl/dbl */
486 return(sgl_to_dbl_fcnvuf(&fpregs
[r1
],0,
488 case 2: /* dbl/sgl */
489 return(dbl_to_sgl_fcnvuf(&fpregs
[r1
],0,
491 case 3: /* dbl/dbl */
492 return(dbl_to_dbl_fcnvuf(&fpregs
[r1
],0,
495 case 6: /* FCNVFU (PA2.0 only) */
497 case 0: /* sgl/sgl */
498 return(sgl_to_sgl_fcnvfu(&fpregs
[r1
],0,
500 case 1: /* sgl/dbl */
501 return(sgl_to_dbl_fcnvfu(&fpregs
[r1
],0,
503 case 2: /* dbl/sgl */
504 return(dbl_to_sgl_fcnvfu(&fpregs
[r1
],0,
506 case 3: /* dbl/dbl */
507 return(dbl_to_dbl_fcnvfu(&fpregs
[r1
],0,
510 case 7: /* FCNVFUT (PA2.0 only) */
512 case 0: /* sgl/sgl */
513 return(sgl_to_sgl_fcnvfut(&fpregs
[r1
],0,
515 case 1: /* sgl/dbl */
516 return(sgl_to_dbl_fcnvfut(&fpregs
[r1
],0,
518 case 2: /* dbl/sgl */
519 return(dbl_to_sgl_fcnvfut(&fpregs
[r1
],0,
521 case 3: /* dbl/dbl */
522 return(dbl_to_dbl_fcnvfut(&fpregs
[r1
],0,
525 case 4: /* undefined */
526 return(MAJOR_0C_EXCP
);
527 } /* end of switch subop */
529 case 2: /* class 2 */
530 fpu_type_flags
=fpregs
[FPU_TYPE_FLAG_POS
];
531 r2
= extru(ir
, fpr2pos
, 5) * sizeof(double)/sizeof(u_int
);
534 if (fpu_type_flags
& PA2_0_FPU_FLAG
) {
535 /* FTEST if nullify bit set, otherwise FCMP */
536 if (extru(ir
, fpnulpos
, 1)) { /* FTEST */
541 * second param is the t field used for
542 * ftest,acc and ftest,rej
543 * third param is the subop (y-field)
547 * return(ftest(0L,extru(ir,fptpos,5),
548 * &fpregs[0],subop));
553 return(MAJOR_0C_EXCP
);
558 retval
= sgl_fcmp(&fpregs
[r1
],
559 &fpregs
[r2
],extru(ir
,fptpos
,5),
561 update_status_cbit(status
,local_status
,
562 fpu_type_flags
, subop
);
565 retval
= dbl_fcmp(&fpregs
[r1
],
566 &fpregs
[r2
],extru(ir
,fptpos
,5),
568 update_status_cbit(status
,local_status
,
569 fpu_type_flags
, subop
);
571 case 2: /* illegal */
572 case 3: /* quad not implemented */
573 return(MAJOR_0C_EXCP
);
576 } /* end of if for PA2.0 */
577 else { /* PA1.0 & PA1.1 */
585 return(MAJOR_0C_EXCP
);
589 retval
= sgl_fcmp(&fpregs
[r1
],
590 &fpregs
[r2
],extru(ir
,fptpos
,5),
592 update_status_cbit(status
,local_status
,
593 fpu_type_flags
, subop
);
596 retval
= dbl_fcmp(&fpregs
[r1
],
597 &fpregs
[r2
],extru(ir
,fptpos
,5),
599 update_status_cbit(status
,local_status
,
600 fpu_type_flags
, subop
);
602 case 2: /* illegal */
603 case 3: /* quad not implemented */
604 return(MAJOR_0C_EXCP
);
611 * second param is the t field used for
612 * ftest,acc and ftest,rej
613 * third param is the subop (y-field)
617 * return(ftest(0L,extru(ir,fptpos,5),
618 * &fpregs[0],subop));
623 return(MAJOR_0C_EXCP
);
625 } /* end of switch subop */
626 } /* end of else for PA1.0 & PA1.1 */
627 case 3: /* class 3 */
628 r2
= extru(ir
,fpr2pos
,5) * sizeof(double)/sizeof(u_int
);
635 return(MAJOR_0C_EXCP
);
640 return(sgl_fadd(&fpregs
[r1
],&fpregs
[r2
],
643 return(dbl_fadd(&fpregs
[r1
],&fpregs
[r2
],
645 case 2: /* illegal */
646 case 3: /* quad not implemented */
647 return(MAJOR_0C_EXCP
);
652 return(sgl_fsub(&fpregs
[r1
],&fpregs
[r2
],
655 return(dbl_fsub(&fpregs
[r1
],&fpregs
[r2
],
657 case 2: /* illegal */
658 case 3: /* quad not implemented */
659 return(MAJOR_0C_EXCP
);
664 return(sgl_fmpy(&fpregs
[r1
],&fpregs
[r2
],
667 return(dbl_fmpy(&fpregs
[r1
],&fpregs
[r2
],
669 case 2: /* illegal */
670 case 3: /* quad not implemented */
671 return(MAJOR_0C_EXCP
);
676 return(sgl_fdiv(&fpregs
[r1
],&fpregs
[r2
],
679 return(dbl_fdiv(&fpregs
[r1
],&fpregs
[r2
],
681 case 2: /* illegal */
682 case 3: /* quad not implemented */
683 return(MAJOR_0C_EXCP
);
688 return(sgl_frem(&fpregs
[r1
],&fpregs
[r2
],
691 return(dbl_frem(&fpregs
[r1
],&fpregs
[r2
],
693 case 2: /* illegal */
694 case 3: /* quad not implemented */
695 return(MAJOR_0C_EXCP
);
697 } /* end of class 3 switch */
698 } /* end of switch(class) */
700 /* If we get here, something is really wrong! */
701 return(MAJOR_0C_EXCP
);
705 decode_0e(ir
,class,subop
,fpregs
)
706 u_int ir
,class,subop
;
709 u_int r1
,r2
,t
; /* operand register offsets */
710 u_int fmt
; /* also sf for class 1 conversions */
711 u_int df
; /* dest format for class 1 conversions */
713 u_int retval
, local_status
;
714 u_int fpu_type_flags
;
717 local_status
= fpregs
[0];
718 r1
= ((extru(ir
,fpr1pos
,5)<<1)|(extru(ir
,fpxr1pos
,1)));
721 t
= ((extru(ir
,fptpos
,5)<<1)|(extru(ir
,fpxtpos
,1)));
722 if (t
== 0 && class != 2)
723 return(MAJOR_0E_EXCP
);
724 if (class < 2) /* class 0 or 1 has 2 bit fmt */
725 fmt
= extru(ir
,fpfmtpos
,2);
726 else /* class 2 and 3 have 1 bit fmt */
727 fmt
= extru(ir
,fp0efmtpos
,1);
729 * An undefined combination, double precision accessing the
730 * right half of a FPR, can get us into trouble.
731 * Let's just force proper alignment on it.
742 case 0: /* unimplemented */
744 return(MAJOR_0E_EXCP
);
749 return(MAJOR_0E_EXCP
);
751 fpregs
[t
+1] = fpregs
[r1
+1];
753 fpregs
[t
] = fpregs
[r1
];
760 return(MAJOR_0E_EXCP
);
762 fpregs
[t
+1] = fpregs
[r1
+1];
764 fpregs
[t
] = fpregs
[r1
] & 0x7fffffff;
771 return(MAJOR_0E_EXCP
);
773 fpregs
[t
+1] = fpregs
[r1
+1];
775 fpregs
[t
] = fpregs
[r1
] ^ 0x80000000;
778 case 7: /* FNEGABS */
782 return(MAJOR_0E_EXCP
);
784 fpregs
[t
+1] = fpregs
[r1
+1];
786 fpregs
[t
] = fpregs
[r1
] | 0x80000000;
792 return(sgl_fsqrt(&fpregs
[r1
],0,
793 &fpregs
[t
], status
));
795 return(dbl_fsqrt(&fpregs
[r1
],0,
796 &fpregs
[t
], status
));
799 return(MAJOR_0E_EXCP
);
804 return(sgl_frnd(&fpregs
[r1
],0,
805 &fpregs
[t
], status
));
807 return(dbl_frnd(&fpregs
[r1
],0,
808 &fpregs
[t
], status
));
811 return(MAJOR_0E_EXCP
);
813 } /* end of switch (subop */
815 case 1: /* class 1 */
816 df
= extru(ir
,fpdfpos
,2); /* get dest format */
818 * Fix Crashme problem (writing to 31R in double precision)
824 if ((df
& 2) || (fmt
& 2))
825 return(MAJOR_0E_EXCP
);
827 fmt
= (fmt
<< 1) | df
;
831 case 0: /* sgl/sgl */
832 return(MAJOR_0E_EXCP
);
833 case 1: /* sgl/dbl */
834 return(sgl_to_dbl_fcnvff(&fpregs
[r1
],0,
836 case 2: /* dbl/sgl */
837 return(dbl_to_sgl_fcnvff(&fpregs
[r1
],0,
839 case 3: /* dbl/dbl */
840 return(MAJOR_0E_EXCP
);
844 case 0: /* sgl/sgl */
845 return(sgl_to_sgl_fcnvxf(&fpregs
[r1
],0,
847 case 1: /* sgl/dbl */
848 return(sgl_to_dbl_fcnvxf(&fpregs
[r1
],0,
850 case 2: /* dbl/sgl */
851 return(dbl_to_sgl_fcnvxf(&fpregs
[r1
],0,
853 case 3: /* dbl/dbl */
854 return(dbl_to_dbl_fcnvxf(&fpregs
[r1
],0,
859 case 0: /* sgl/sgl */
860 return(sgl_to_sgl_fcnvfx(&fpregs
[r1
],0,
862 case 1: /* sgl/dbl */
863 return(sgl_to_dbl_fcnvfx(&fpregs
[r1
],0,
865 case 2: /* dbl/sgl */
866 return(dbl_to_sgl_fcnvfx(&fpregs
[r1
],0,
868 case 3: /* dbl/dbl */
869 return(dbl_to_dbl_fcnvfx(&fpregs
[r1
],0,
872 case 3: /* FCNVFXT */
874 case 0: /* sgl/sgl */
875 return(sgl_to_sgl_fcnvfxt(&fpregs
[r1
],0,
877 case 1: /* sgl/dbl */
878 return(sgl_to_dbl_fcnvfxt(&fpregs
[r1
],0,
880 case 2: /* dbl/sgl */
881 return(dbl_to_sgl_fcnvfxt(&fpregs
[r1
],0,
883 case 3: /* dbl/dbl */
884 return(dbl_to_dbl_fcnvfxt(&fpregs
[r1
],0,
887 case 5: /* FCNVUF (PA2.0 only) */
889 case 0: /* sgl/sgl */
890 return(sgl_to_sgl_fcnvuf(&fpregs
[r1
],0,
892 case 1: /* sgl/dbl */
893 return(sgl_to_dbl_fcnvuf(&fpregs
[r1
],0,
895 case 2: /* dbl/sgl */
896 return(dbl_to_sgl_fcnvuf(&fpregs
[r1
],0,
898 case 3: /* dbl/dbl */
899 return(dbl_to_dbl_fcnvuf(&fpregs
[r1
],0,
902 case 6: /* FCNVFU (PA2.0 only) */
904 case 0: /* sgl/sgl */
905 return(sgl_to_sgl_fcnvfu(&fpregs
[r1
],0,
907 case 1: /* sgl/dbl */
908 return(sgl_to_dbl_fcnvfu(&fpregs
[r1
],0,
910 case 2: /* dbl/sgl */
911 return(dbl_to_sgl_fcnvfu(&fpregs
[r1
],0,
913 case 3: /* dbl/dbl */
914 return(dbl_to_dbl_fcnvfu(&fpregs
[r1
],0,
917 case 7: /* FCNVFUT (PA2.0 only) */
919 case 0: /* sgl/sgl */
920 return(sgl_to_sgl_fcnvfut(&fpregs
[r1
],0,
922 case 1: /* sgl/dbl */
923 return(sgl_to_dbl_fcnvfut(&fpregs
[r1
],0,
925 case 2: /* dbl/sgl */
926 return(dbl_to_sgl_fcnvfut(&fpregs
[r1
],0,
928 case 3: /* dbl/dbl */
929 return(dbl_to_dbl_fcnvfut(&fpregs
[r1
],0,
932 case 4: /* undefined */
933 return(MAJOR_0C_EXCP
);
934 } /* end of switch subop */
935 case 2: /* class 2 */
937 * Be careful out there.
938 * Crashme can generate cases where FR31R is specified
939 * as the source or target of a double precision operation.
940 * Since we just pass the address of the floating-point
941 * register to the emulation routines, this can cause
942 * corruption of fpzeroreg.
945 r2
= (extru(ir
,fpr2pos
,5)<<1);
947 r2
= ((extru(ir
,fpr2pos
,5)<<1)|(extru(ir
,fpxr2pos
,1)));
948 fpu_type_flags
=fpregs
[FPU_TYPE_FLAG_POS
];
951 if (fpu_type_flags
& PA2_0_FPU_FLAG
) {
952 /* FTEST if nullify bit set, otherwise FCMP */
953 if (extru(ir
, fpnulpos
, 1)) { /* FTEST */
955 return(MAJOR_0E_EXCP
);
959 * fmt is only 1 bit long
962 retval
= sgl_fcmp(&fpregs
[r1
],
963 &fpregs
[r2
],extru(ir
,fptpos
,5),
965 update_status_cbit(status
,local_status
,
966 fpu_type_flags
, subop
);
969 retval
= dbl_fcmp(&fpregs
[r1
],
970 &fpregs
[r2
],extru(ir
,fptpos
,5),
972 update_status_cbit(status
,local_status
,
973 fpu_type_flags
, subop
);
977 } /* end of if for PA2.0 */
978 else { /* PA1.0 & PA1.1 */
987 return(MAJOR_0E_EXCP
);
991 * fmt is only 1 bit long
994 retval
= sgl_fcmp(&fpregs
[r1
],
995 &fpregs
[r2
],extru(ir
,fptpos
,5),
997 update_status_cbit(status
,local_status
,
998 fpu_type_flags
, subop
);
1001 retval
= dbl_fcmp(&fpregs
[r1
],
1002 &fpregs
[r2
],extru(ir
,fptpos
,5),
1004 update_status_cbit(status
,local_status
,
1005 fpu_type_flags
, subop
);
1008 } /* end of switch subop */
1009 } /* end of else for PA1.0 & PA1.1 */
1010 case 3: /* class 3 */
1012 * Be careful out there.
1013 * Crashme can generate cases where FR31R is specified
1014 * as the source or target of a double precision operation.
1015 * Since we just pass the address of the floating-point
1016 * register to the emulation routines, this can cause
1017 * corruption of fpzeroreg.
1020 r2
= (extru(ir
,fpr2pos
,5)<<1);
1022 r2
= ((extru(ir
,fpr2pos
,5)<<1)|(extru(ir
,fpxr2pos
,1)));
1029 return(MAJOR_0E_EXCP
);
1032 * Note that fmt is only 1 bit for class 3 */
1036 return(sgl_fadd(&fpregs
[r1
],&fpregs
[r2
],
1037 &fpregs
[t
],status
));
1039 return(dbl_fadd(&fpregs
[r1
],&fpregs
[r2
],
1040 &fpregs
[t
],status
));
1045 return(sgl_fsub(&fpregs
[r1
],&fpregs
[r2
],
1046 &fpregs
[t
],status
));
1048 return(dbl_fsub(&fpregs
[r1
],&fpregs
[r2
],
1049 &fpregs
[t
],status
));
1051 case 2: /* FMPY or XMPYU */
1053 * check for integer multiply (x bit set)
1055 if (extru(ir
,fpxpos
,1)) {
1062 * bad instruction if t specifies
1063 * the right half of a register
1066 return(MAJOR_0E_EXCP
);
1069 * impyu(&fpregs[r1],&fpregs[r2],
1072 return(NOEXCEPTION
);
1074 return(MAJOR_0E_EXCP
);
1080 return(sgl_fmpy(&fpregs
[r1
],
1081 &fpregs
[r2
],&fpregs
[t
],status
));
1083 return(dbl_fmpy(&fpregs
[r1
],
1084 &fpregs
[r2
],&fpregs
[t
],status
));
1090 return(sgl_fdiv(&fpregs
[r1
],&fpregs
[r2
],
1091 &fpregs
[t
],status
));
1093 return(dbl_fdiv(&fpregs
[r1
],&fpregs
[r2
],
1094 &fpregs
[t
],status
));
1099 return(sgl_frem(&fpregs
[r1
],&fpregs
[r2
],
1100 &fpregs
[t
],status
));
1102 return(dbl_frem(&fpregs
[r1
],&fpregs
[r2
],
1103 &fpregs
[t
],status
));
1105 } /* end of class 3 switch */
1106 } /* end of switch(class) */
1108 /* If we get here, something is really wrong! */
1109 return(MAJOR_0E_EXCP
);
1114 * routine to decode the 06 (FMPYADD and FMPYCFXT) instruction
1117 decode_06(ir
,fpregs
)
1121 u_int rm1
, rm2
, tm
, ra
, ta
; /* operands */
1125 u_int fpu_type_flags
;
1129 struct { u_int i1
; u_int i2
; } ints
;
1133 status
= fpregs
[0]; /* use a local copy of status reg */
1134 fpu_type_flags
=fpregs
[FPU_TYPE_FLAG_POS
]; /* get fpu type flags */
1135 fmt
= extru(ir
, fpmultifmt
, 1); /* get sgl/dbl flag */
1136 if (fmt
== 0) { /* DBL */
1137 rm1
= extru(ir
, fprm1pos
, 5) * sizeof(double)/sizeof(u_int
);
1140 rm2
= extru(ir
, fprm2pos
, 5) * sizeof(double)/sizeof(u_int
);
1143 tm
= extru(ir
, fptmpos
, 5) * sizeof(double)/sizeof(u_int
);
1145 return(MAJOR_06_EXCP
);
1146 ra
= extru(ir
, fprapos
, 5) * sizeof(double)/sizeof(u_int
);
1147 ta
= extru(ir
, fptapos
, 5) * sizeof(double)/sizeof(u_int
);
1149 return(MAJOR_06_EXCP
);
1151 if (fpu_type_flags
& TIMEX_ROLEX_FPU_MASK
) {
1154 /* special case FMPYCFXT, see sgl case below */
1155 if (dbl_fmpy(&fpregs
[rm1
],&fpregs
[rm2
],
1156 &mtmp
.ints
.i1
,&status
))
1158 if (dbl_to_sgl_fcnvfxt(&fpregs
[ta
],
1159 &atmp
.ints
.i1
,&atmp
.ints
.i1
,&status
))
1164 if (dbl_fmpy(&fpregs
[rm1
],&fpregs
[rm2
],&mtmp
.ints
.i1
,
1167 if (dbl_fadd(&fpregs
[ta
], &fpregs
[ra
], &atmp
.ints
.i1
,
1179 if (dbl_fmpy(&fpregs
[rm1
],&fpregs
[rm2
],&mtmp
.ints
.i1
,
1182 if (dbl_fadd(&fpregs
[ta
], &fpregs
[ra
], &atmp
.ints
.i1
,
1189 return(MAJOR_06_EXCP
);
1192 fpregs
[tm
] = mtmp
.ints
.i1
;
1193 fpregs
[tm
+1] = mtmp
.ints
.i2
;
1194 fpregs
[ta
] = atmp
.ints
.i1
;
1195 fpregs
[ta
+1] = atmp
.ints
.i2
;
1197 return(NOEXCEPTION
);
1202 * calculate offsets for single precision numbers
1203 * See table 6-14 in PA-89 architecture for mapping
1205 rm1
= (extru(ir
,fprm1pos
,4) | 0x10 ) << 1; /* get offset */
1206 rm1
|= extru(ir
,fprm1pos
-4,1); /* add right word offset */
1208 rm2
= (extru(ir
,fprm2pos
,4) | 0x10 ) << 1; /* get offset */
1209 rm2
|= extru(ir
,fprm2pos
-4,1); /* add right word offset */
1211 tm
= (extru(ir
,fptmpos
,4) | 0x10 ) << 1; /* get offset */
1212 tm
|= extru(ir
,fptmpos
-4,1); /* add right word offset */
1214 ra
= (extru(ir
,fprapos
,4) | 0x10 ) << 1; /* get offset */
1215 ra
|= extru(ir
,fprapos
-4,1); /* add right word offset */
1217 ta
= (extru(ir
,fptapos
,4) | 0x10 ) << 1; /* get offset */
1218 ta
|= extru(ir
,fptapos
-4,1); /* add right word offset */
1220 if (ra
== 0x20 &&(fpu_type_flags
& TIMEX_ROLEX_FPU_MASK
)) {
1221 /* special case FMPYCFXT (really 0)
1222 * This instruction is only present on the Timex and
1223 * Rolex fpu's in so if it is the special case and
1224 * one of these fpu's we run the FMPYCFXT instruction
1226 if (sgl_fmpy(&fpregs
[rm1
],&fpregs
[rm2
],&mtmp
.ints
.i1
,
1229 if (sgl_to_sgl_fcnvfxt(&fpregs
[ta
],&atmp
.ints
.i1
,
1230 &atmp
.ints
.i1
,&status
))
1234 if (sgl_fmpy(&fpregs
[rm1
],&fpregs
[rm2
],&mtmp
.ints
.i1
,
1237 if (sgl_fadd(&fpregs
[ta
], &fpregs
[ra
], &atmp
.ints
.i1
,
1242 return(MAJOR_06_EXCP
);
1245 fpregs
[tm
] = mtmp
.ints
.i1
;
1246 fpregs
[ta
] = atmp
.ints
.i1
;
1248 return(NOEXCEPTION
);
1254 * routine to decode the 26 (FMPYSUB) instruction
1257 decode_26(ir
,fpregs
)
1261 u_int rm1
, rm2
, tm
, ra
, ta
; /* operands */
1268 struct { u_int i1
; u_int i2
; } ints
;
1273 fmt
= extru(ir
, fpmultifmt
, 1); /* get sgl/dbl flag */
1274 if (fmt
== 0) { /* DBL */
1275 rm1
= extru(ir
, fprm1pos
, 5) * sizeof(double)/sizeof(u_int
);
1278 rm2
= extru(ir
, fprm2pos
, 5) * sizeof(double)/sizeof(u_int
);
1281 tm
= extru(ir
, fptmpos
, 5) * sizeof(double)/sizeof(u_int
);
1283 return(MAJOR_26_EXCP
);
1284 ra
= extru(ir
, fprapos
, 5) * sizeof(double)/sizeof(u_int
);
1286 return(MAJOR_26_EXCP
);
1287 ta
= extru(ir
, fptapos
, 5) * sizeof(double)/sizeof(u_int
);
1289 return(MAJOR_26_EXCP
);
1291 if (dbl_fmpy(&fpregs
[rm1
],&fpregs
[rm2
],&mtmp
.ints
.i1
,&status
))
1293 if (dbl_fsub(&fpregs
[ta
], &fpregs
[ra
], &atmp
.ints
.i1
,&status
))
1296 return(MAJOR_26_EXCP
);
1299 fpregs
[tm
] = mtmp
.ints
.i1
;
1300 fpregs
[tm
+1] = mtmp
.ints
.i2
;
1301 fpregs
[ta
] = atmp
.ints
.i1
;
1302 fpregs
[ta
+1] = atmp
.ints
.i2
;
1304 return(NOEXCEPTION
);
1309 * calculate offsets for single precision numbers
1310 * See table 6-14 in PA-89 architecture for mapping
1312 rm1
= (extru(ir
,fprm1pos
,4) | 0x10 ) << 1; /* get offset */
1313 rm1
|= extru(ir
,fprm1pos
-4,1); /* add right word offset */
1315 rm2
= (extru(ir
,fprm2pos
,4) | 0x10 ) << 1; /* get offset */
1316 rm2
|= extru(ir
,fprm2pos
-4,1); /* add right word offset */
1318 tm
= (extru(ir
,fptmpos
,4) | 0x10 ) << 1; /* get offset */
1319 tm
|= extru(ir
,fptmpos
-4,1); /* add right word offset */
1321 ra
= (extru(ir
,fprapos
,4) | 0x10 ) << 1; /* get offset */
1322 ra
|= extru(ir
,fprapos
-4,1); /* add right word offset */
1324 ta
= (extru(ir
,fptapos
,4) | 0x10 ) << 1; /* get offset */
1325 ta
|= extru(ir
,fptapos
-4,1); /* add right word offset */
1327 if (sgl_fmpy(&fpregs
[rm1
],&fpregs
[rm2
],&mtmp
.ints
.i1
,&status
))
1329 if (sgl_fsub(&fpregs
[ta
], &fpregs
[ra
], &atmp
.ints
.i1
,&status
))
1332 return(MAJOR_26_EXCP
);
1335 fpregs
[tm
] = mtmp
.ints
.i1
;
1336 fpregs
[ta
] = atmp
.ints
.i1
;
1338 return(NOEXCEPTION
);
1345 * routine to decode the 2E (FMPYFADD,FMPYNFADD) instructions
1348 decode_2e(ir
,fpregs
)
1352 u_int rm1
, rm2
, ra
, t
; /* operands */
1355 fmt
= extru(ir
,fpfmtpos
,1); /* get fmt completer */
1356 if (fmt
== DBL
) { /* DBL */
1357 rm1
= extru(ir
,fprm1pos
,5) * sizeof(double)/sizeof(u_int
);
1360 rm2
= extru(ir
,fprm2pos
,5) * sizeof(double)/sizeof(u_int
);
1363 ra
= ((extru(ir
,fpraupos
,3)<<2)|(extru(ir
,fpralpos
,3)>>1)) *
1364 sizeof(double)/sizeof(u_int
);
1367 t
= extru(ir
,fptpos
,5) * sizeof(double)/sizeof(u_int
);
1369 return(MAJOR_2E_EXCP
);
1371 if (extru(ir
,fpfusedsubop
,1)) { /* fmpyfadd or fmpynfadd? */
1372 return(dbl_fmpynfadd(&fpregs
[rm1
], &fpregs
[rm2
],
1373 &fpregs
[ra
], &fpregs
[0], &fpregs
[t
]));
1375 return(dbl_fmpyfadd(&fpregs
[rm1
], &fpregs
[rm2
],
1376 &fpregs
[ra
], &fpregs
[0], &fpregs
[t
]));
1380 rm1
= (extru(ir
,fprm1pos
,5)<<1)|(extru(ir
,fpxrm1pos
,1));
1383 rm2
= (extru(ir
,fprm2pos
,5)<<1)|(extru(ir
,fpxrm2pos
,1));
1386 ra
= (extru(ir
,fpraupos
,3)<<3)|extru(ir
,fpralpos
,3);
1389 t
= ((extru(ir
,fptpos
,5)<<1)|(extru(ir
,fpxtpos
,1)));
1391 return(MAJOR_2E_EXCP
);
1393 if (extru(ir
,fpfusedsubop
,1)) { /* fmpyfadd or fmpynfadd? */
1394 return(sgl_fmpynfadd(&fpregs
[rm1
], &fpregs
[rm2
],
1395 &fpregs
[ra
], &fpregs
[0], &fpregs
[t
]));
1397 return(sgl_fmpyfadd(&fpregs
[rm1
], &fpregs
[rm2
],
1398 &fpregs
[ra
], &fpregs
[0], &fpregs
[t
]));
1404 * update_status_cbit
1406 * This routine returns the correct FP status register value in
1407 * *status, based on the C-bit & V-bit returned by the FCMP
1408 * emulation routine in new_status. The architecture type
1409 * (PA83, PA89 or PA2.0) is available in fpu_type. The y_field
1410 * and the architecture type are used to determine what flavor
1411 * of FCMP is being emulated.
1414 update_status_cbit(status
, new_status
, fpu_type
, y_field
)
1415 u_int
*status
, new_status
;
1420 * For PA89 FPU's which implement the Compare Queue and
1421 * for PA2.0 FPU's, update the Compare Queue if the y-field = 0,
1422 * otherwise update the specified bit in the Compare Array.
1423 * Note that the y-field will always be 0 for non-PA2.0 FPU's.
1425 if ((fpu_type
& TIMEX_EXTEN_FLAG
) ||
1426 (fpu_type
& ROLEX_EXTEN_FLAG
) ||
1427 (fpu_type
& PA2_0_FPU_FLAG
)) {
1429 *status
= ((*status
& 0x04000000) >> 5) | /* old Cbit */
1430 ((*status
& 0x003ff000) >> 1) | /* old CQ */
1431 (new_status
& 0xffc007ff); /* all other bits*/
1433 *status
= (*status
& 0x04000000) | /* old Cbit */
1434 ((new_status
& 0x04000000) >> (y_field
+4)) |
1435 (new_status
& ~0x04000000 & /* other bits */
1436 ~(0x04000000 >> (y_field
+4)));
1439 /* if PA83, just update the C-bit */
1441 *status
= new_status
;