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mm: fix exec activate_mm vs TLB shootdown and lazy tlb switching race
[linux/fpc-iii.git] / arch / s390 / net / bpf_jit_comp.c
blobb8bd84104843480554f812bcca967858cbe33c89
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * BPF Jit compiler for s390.
4 *
5 * Minimum build requirements:
6 *
7 * - HAVE_MARCH_Z196_FEATURES: laal, laalg
8 * - HAVE_MARCH_Z10_FEATURES: msfi, cgrj, clgrj
9 * - HAVE_MARCH_Z9_109_FEATURES: alfi, llilf, clfi, oilf, nilf
10 * - PACK_STACK
11 * - 64BIT
12 *
13 * Copyright IBM Corp. 2012,2015
14 *
15 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
16 * Michael Holzheu <holzheu@linux.vnet.ibm.com>
17 */
18
19 #define KMSG_COMPONENT "bpf_jit"
20 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
21
22 #include <linux/netdevice.h>
23 #include <linux/filter.h>
24 #include <linux/init.h>
25 #include <linux/bpf.h>
26 #include <asm/cacheflush.h>
27 #include <asm/dis.h>
28 #include <asm/facility.h>
29 #include <asm/nospec-branch.h>
30 #include <asm/set_memory.h>
31 #include "bpf_jit.h"
32
33 struct bpf_jit {
34 u32 seen; /* Flags to remember seen eBPF instructions */
35 u32 seen_reg[16]; /* Array to remember which registers are used */
36 u32 *addrs; /* Array with relative instruction addresses */
37 u8 *prg_buf; /* Start of program */
38 int size; /* Size of program and literal pool */
39 int size_prg; /* Size of program */
40 int prg; /* Current position in program */
41 int lit_start; /* Start of literal pool */
42 int lit; /* Current position in literal pool */
43 int base_ip; /* Base address for literal pool */
44 int ret0_ip; /* Address of return 0 */
45 int exit_ip; /* Address of exit */
46 int r1_thunk_ip; /* Address of expoline thunk for 'br %r1' */
47 int r14_thunk_ip; /* Address of expoline thunk for 'br %r14' */
48 int tail_call_start; /* Tail call start offset */
49 int labels[1]; /* Labels for local jumps */
50 };
51
52 #define BPF_SIZE_MAX 0xffff /* Max size for program (16 bit branches) */
53
54 #define SEEN_SKB 1 /* skb access */
55 #define SEEN_MEM 2 /* use mem[] for temporary storage */
56 #define SEEN_RET0 4 /* ret0_ip points to a valid return 0 */
57 #define SEEN_LITERAL 8 /* code uses literals */
58 #define SEEN_FUNC 16 /* calls C functions */
59 #define SEEN_TAIL_CALL 32 /* code uses tail calls */
60 #define SEEN_REG_AX 64 /* code uses constant blinding */
61 #define SEEN_STACK (SEEN_FUNC | SEEN_MEM | SEEN_SKB)
62
63 /*
64 * s390 registers
65 */
66 #define REG_W0 (MAX_BPF_JIT_REG + 0) /* Work register 1 (even) */
67 #define REG_W1 (MAX_BPF_JIT_REG + 1) /* Work register 2 (odd) */
68 #define REG_SKB_DATA (MAX_BPF_JIT_REG + 2) /* SKB data register */
69 #define REG_L (MAX_BPF_JIT_REG + 3) /* Literal pool register */
70 #define REG_15 (MAX_BPF_JIT_REG + 4) /* Register 15 */
71 #define REG_0 REG_W0 /* Register 0 */
72 #define REG_1 REG_W1 /* Register 1 */
73 #define REG_2 BPF_REG_1 /* Register 2 */
74 #define REG_14 BPF_REG_0 /* Register 14 */
75
76 /*
77 * Mapping of BPF registers to s390 registers
78 */
79 static const int reg2hex[] = {
80 /* Return code */
81 [BPF_REG_0] = 14,
82 /* Function parameters */
83 [BPF_REG_1] = 2,
84 [BPF_REG_2] = 3,
85 [BPF_REG_3] = 4,
86 [BPF_REG_4] = 5,
87 [BPF_REG_5] = 6,
88 /* Call saved registers */
89 [BPF_REG_6] = 7,
90 [BPF_REG_7] = 8,
91 [BPF_REG_8] = 9,
92 [BPF_REG_9] = 10,
93 /* BPF stack pointer */
94 [BPF_REG_FP] = 13,
95 /* Register for blinding (shared with REG_SKB_DATA) */
96 [BPF_REG_AX] = 12,
97 /* SKB data pointer */
98 [REG_SKB_DATA] = 12,
99 /* Work registers for s390x backend */
100 [REG_W0] = 0,
101 [REG_W1] = 1,
102 [REG_L] = 11,
103 [REG_15] = 15,
104 };
105
106 static inline u32 reg(u32 dst_reg, u32 src_reg)
107 {
108 return reg2hex[dst_reg] << 4 | reg2hex[src_reg];
109 }
110
111 static inline u32 reg_high(u32 reg)
112 {
113 return reg2hex[reg] << 4;
114 }
115
116 static inline void reg_set_seen(struct bpf_jit *jit, u32 b1)
117 {
118 u32 r1 = reg2hex[b1];
119
120 if (!jit->seen_reg[r1] && r1 >= 6 && r1 <= 15)
121 jit->seen_reg[r1] = 1;
122 }
123
124 #define REG_SET_SEEN(b1) \
125 ({ \
126 reg_set_seen(jit, b1); \
127 })
128
129 #define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]]
130
131 /*
132 * EMIT macros for code generation
133 */
134
135 #define _EMIT2(op) \
136 ({ \
137 if (jit->prg_buf) \
138 *(u16 *) (jit->prg_buf + jit->prg) = op; \
139 jit->prg += 2; \
140 })
141
142 #define EMIT2(op, b1, b2) \
143 ({ \
144 _EMIT2(op | reg(b1, b2)); \
145 REG_SET_SEEN(b1); \
146 REG_SET_SEEN(b2); \
147 })
148
149 #define _EMIT4(op) \
150 ({ \
151 if (jit->prg_buf) \
152 *(u32 *) (jit->prg_buf + jit->prg) = op; \
153 jit->prg += 4; \
154 })
155
156 #define EMIT4(op, b1, b2) \
157 ({ \
158 _EMIT4(op | reg(b1, b2)); \
159 REG_SET_SEEN(b1); \
160 REG_SET_SEEN(b2); \
161 })
162
163 #define EMIT4_RRF(op, b1, b2, b3) \
164 ({ \
165 _EMIT4(op | reg_high(b3) << 8 | reg(b1, b2)); \
166 REG_SET_SEEN(b1); \
167 REG_SET_SEEN(b2); \
168 REG_SET_SEEN(b3); \
169 })
170
171 #define _EMIT4_DISP(op, disp) \
172 ({ \
173 unsigned int __disp = (disp) & 0xfff; \
174 _EMIT4(op | __disp); \
175 })
176
177 #define EMIT4_DISP(op, b1, b2, disp) \
178 ({ \
179 _EMIT4_DISP(op | reg_high(b1) << 16 | \
180 reg_high(b2) << 8, disp); \
181 REG_SET_SEEN(b1); \
182 REG_SET_SEEN(b2); \
183 })
184
185 #define EMIT4_IMM(op, b1, imm) \
186 ({ \
187 unsigned int __imm = (imm) & 0xffff; \
188 _EMIT4(op | reg_high(b1) << 16 | __imm); \
189 REG_SET_SEEN(b1); \
190 })
191
192 #define EMIT4_PCREL(op, pcrel) \
193 ({ \
194 long __pcrel = ((pcrel) >> 1) & 0xffff; \
195 _EMIT4(op | __pcrel); \
196 })
197
198 #define _EMIT6(op1, op2) \
199 ({ \
200 if (jit->prg_buf) { \
201 *(u32 *) (jit->prg_buf + jit->prg) = op1; \
202 *(u16 *) (jit->prg_buf + jit->prg + 4) = op2; \
203 } \
204 jit->prg += 6; \
205 })
206
207 #define _EMIT6_DISP(op1, op2, disp) \
208 ({ \
209 unsigned int __disp = (disp) & 0xfff; \
210 _EMIT6(op1 | __disp, op2); \
211 })
212
213 #define _EMIT6_DISP_LH(op1, op2, disp) \
214 ({ \
215 u32 _disp = (u32) disp; \
216 unsigned int __disp_h = _disp & 0xff000; \
217 unsigned int __disp_l = _disp & 0x00fff; \
218 _EMIT6(op1 | __disp_l, op2 | __disp_h >> 4); \
219 })
220
221 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \
222 ({ \
223 _EMIT6_DISP_LH(op1 | reg(b1, b2) << 16 | \
224 reg_high(b3) << 8, op2, disp); \
225 REG_SET_SEEN(b1); \
226 REG_SET_SEEN(b2); \
227 REG_SET_SEEN(b3); \
228 })
229
230 #define EMIT6_PCREL_LABEL(op1, op2, b1, b2, label, mask) \
231 ({ \
232 int rel = (jit->labels[label] - jit->prg) >> 1; \
233 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), \
234 op2 | mask << 12); \
235 REG_SET_SEEN(b1); \
236 REG_SET_SEEN(b2); \
237 })
238
239 #define EMIT6_PCREL_IMM_LABEL(op1, op2, b1, imm, label, mask) \
240 ({ \
241 int rel = (jit->labels[label] - jit->prg) >> 1; \
242 _EMIT6(op1 | (reg_high(b1) | mask) << 16 | \
243 (rel & 0xffff), op2 | (imm & 0xff) << 8); \
244 REG_SET_SEEN(b1); \
245 BUILD_BUG_ON(((unsigned long) imm) > 0xff); \
246 })
247
248 #define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \
249 ({ \
250 /* Branch instruction needs 6 bytes */ \
251 int rel = (addrs[i + off + 1] - (addrs[i + 1] - 6)) / 2;\
252 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), op2 | mask); \
253 REG_SET_SEEN(b1); \
254 REG_SET_SEEN(b2); \
255 })
256
257 #define EMIT6_PCREL_RILB(op, b, target) \
258 ({ \
259 int rel = (target - jit->prg) / 2; \
260 _EMIT6(op | reg_high(b) << 16 | rel >> 16, rel & 0xffff); \
261 REG_SET_SEEN(b); \
262 })
263
264 #define EMIT6_PCREL_RIL(op, target) \
265 ({ \
266 int rel = (target - jit->prg) / 2; \
267 _EMIT6(op | rel >> 16, rel & 0xffff); \
268 })
269
270 #define _EMIT6_IMM(op, imm) \
271 ({ \
272 unsigned int __imm = (imm); \
273 _EMIT6(op | (__imm >> 16), __imm & 0xffff); \
274 })
275
276 #define EMIT6_IMM(op, b1, imm) \
277 ({ \
278 _EMIT6_IMM(op | reg_high(b1) << 16, imm); \
279 REG_SET_SEEN(b1); \
280 })
281
282 #define EMIT_CONST_U32(val) \
283 ({ \
284 unsigned int ret; \
285 ret = jit->lit - jit->base_ip; \
286 jit->seen |= SEEN_LITERAL; \
287 if (jit->prg_buf) \
288 *(u32 *) (jit->prg_buf + jit->lit) = (u32) val; \
289 jit->lit += 4; \
290 ret; \
291 })
292
293 #define EMIT_CONST_U64(val) \
294 ({ \
295 unsigned int ret; \
296 ret = jit->lit - jit->base_ip; \
297 jit->seen |= SEEN_LITERAL; \
298 if (jit->prg_buf) \
299 *(u64 *) (jit->prg_buf + jit->lit) = (u64) val; \
300 jit->lit += 8; \
301 ret; \
302 })
303
304 #define EMIT_ZERO(b1) \
305 ({ \
306 /* llgfr %dst,%dst (zero extend to 64 bit) */ \
307 EMIT4(0xb9160000, b1, b1); \
308 REG_SET_SEEN(b1); \
309 })
310
311 /*
312 * Fill whole space with illegal instructions
313 */
314 static void jit_fill_hole(void *area, unsigned int size)
315 {
316 memset(area, 0, size);
317 }
318
319 /*
320 * Save registers from "rs" (register start) to "re" (register end) on stack
321 */
322 static void save_regs(struct bpf_jit *jit, u32 rs, u32 re)
323 {
324 u32 off = STK_OFF_R6 + (rs - 6) * 8;
325
326 if (rs == re)
327 /* stg %rs,off(%r15) */
328 _EMIT6(0xe300f000 | rs << 20 | off, 0x0024);
329 else
330 /* stmg %rs,%re,off(%r15) */
331 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0024, off);
332 }
333
334 /*
335 * Restore registers from "rs" (register start) to "re" (register end) on stack
336 */
337 static void restore_regs(struct bpf_jit *jit, u32 rs, u32 re)
338 {
339 u32 off = STK_OFF_R6 + (rs - 6) * 8;
340
341 if (jit->seen & SEEN_STACK)
342 off += STK_OFF;
343
344 if (rs == re)
345 /* lg %rs,off(%r15) */
346 _EMIT6(0xe300f000 | rs << 20 | off, 0x0004);
347 else
348 /* lmg %rs,%re,off(%r15) */
349 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0004, off);
350 }
351
352 /*
353 * Return first seen register (from start)
354 */
355 static int get_start(struct bpf_jit *jit, int start)
356 {
357 int i;
358
359 for (i = start; i <= 15; i++) {
360 if (jit->seen_reg[i])
361 return i;
362 }
363 return 0;
364 }
365
366 /*
367 * Return last seen register (from start) (gap >= 2)
368 */
369 static int get_end(struct bpf_jit *jit, int start)
370 {
371 int i;
372
373 for (i = start; i < 15; i++) {
374 if (!jit->seen_reg[i] && !jit->seen_reg[i + 1])
375 return i - 1;
376 }
377 return jit->seen_reg[15] ? 15 : 14;
378 }
379
380 #define REGS_SAVE 1
381 #define REGS_RESTORE 0
382 /*
383 * Save and restore clobbered registers (6-15) on stack.
384 * We save/restore registers in chunks with gap >= 2 registers.
385 */
386 static void save_restore_regs(struct bpf_jit *jit, int op)
387 {
388
389 int re = 6, rs;
390
391 do {
392 rs = get_start(jit, re);
393 if (!rs)
394 break;
395 re = get_end(jit, rs + 1);
396 if (op == REGS_SAVE)
397 save_regs(jit, rs, re);
398 else
399 restore_regs(jit, rs, re);
400 re++;
401 } while (re <= 15);
402 }
403
404 /*
405 * For SKB access %b1 contains the SKB pointer. For "bpf_jit.S"
406 * we store the SKB header length on the stack and the SKB data
407 * pointer in REG_SKB_DATA if BPF_REG_AX is not used.
408 */
409 static void emit_load_skb_data_hlen(struct bpf_jit *jit)
410 {
411 /* Header length: llgf %w1,<len>(%b1) */
412 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_1,
413 offsetof(struct sk_buff, len));
414 /* s %w1,<data_len>(%b1) */
415 EMIT4_DISP(0x5b000000, REG_W1, BPF_REG_1,
416 offsetof(struct sk_buff, data_len));
417 /* stg %w1,ST_OFF_HLEN(%r0,%r15) */
418 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0, REG_15, STK_OFF_HLEN);
419 if (!(jit->seen & SEEN_REG_AX))
420 /* lg %skb_data,data_off(%b1) */
421 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_SKB_DATA, REG_0,
422 BPF_REG_1, offsetof(struct sk_buff, data));
423 }
424
425 /*
426 * Emit function prologue
427 *
428 * Save registers and create stack frame if necessary.
429 * See stack frame layout desription in "bpf_jit.h"!
430 */
431 static void bpf_jit_prologue(struct bpf_jit *jit)
432 {
433 if (jit->seen & SEEN_TAIL_CALL) {
434 /* xc STK_OFF_TCCNT(4,%r15),STK_OFF_TCCNT(%r15) */
435 _EMIT6(0xd703f000 | STK_OFF_TCCNT, 0xf000 | STK_OFF_TCCNT);
436 } else {
437 /* j tail_call_start: NOP if no tail calls are used */
438 EMIT4_PCREL(0xa7f40000, 6);
439 _EMIT2(0);
440 }
441 /* Tail calls have to skip above initialization */
442 jit->tail_call_start = jit->prg;
443 /* Save registers */
444 save_restore_regs(jit, REGS_SAVE);
445 /* Setup literal pool */
446 if (jit->seen & SEEN_LITERAL) {
447 /* basr %r13,0 */
448 EMIT2(0x0d00, REG_L, REG_0);
449 jit->base_ip = jit->prg;
450 }
451 /* Setup stack and backchain */
452 if (jit->seen & SEEN_STACK) {
453 if (jit->seen & SEEN_FUNC)
454 /* lgr %w1,%r15 (backchain) */
455 EMIT4(0xb9040000, REG_W1, REG_15);
456 /* la %bfp,STK_160_UNUSED(%r15) (BPF frame pointer) */
457 EMIT4_DISP(0x41000000, BPF_REG_FP, REG_15, STK_160_UNUSED);
458 /* aghi %r15,-STK_OFF */
459 EMIT4_IMM(0xa70b0000, REG_15, -STK_OFF);
460 if (jit->seen & SEEN_FUNC)
461 /* stg %w1,152(%r15) (backchain) */
462 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0,
463 REG_15, 152);
464 }
465 if (jit->seen & SEEN_SKB) {
466 emit_load_skb_data_hlen(jit);
467 /* stg %b1,ST_OFF_SKBP(%r0,%r15) */
468 EMIT6_DISP_LH(0xe3000000, 0x0024, BPF_REG_1, REG_0, REG_15,
469 STK_OFF_SKBP);
470 }
471 }
472
473 /*
474 * Function epilogue
475 */
476 static void bpf_jit_epilogue(struct bpf_jit *jit)
477 {
478 /* Return 0 */
479 if (jit->seen & SEEN_RET0) {
480 jit->ret0_ip = jit->prg;
481 /* lghi %b0,0 */
482 EMIT4_IMM(0xa7090000, BPF_REG_0, 0);
483 }
484 jit->exit_ip = jit->prg;
485 /* Load exit code: lgr %r2,%b0 */
486 EMIT4(0xb9040000, REG_2, BPF_REG_0);
487 /* Restore registers */
488 save_restore_regs(jit, REGS_RESTORE);
489 if (IS_ENABLED(CC_USING_EXPOLINE) && !nospec_disable) {
490 jit->r14_thunk_ip = jit->prg;
491 /* Generate __s390_indirect_jump_r14 thunk */
492 if (test_facility(35)) {
493 /* exrl %r0,.+10 */
494 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10);
495 } else {
496 /* larl %r1,.+14 */
497 EMIT6_PCREL_RILB(0xc0000000, REG_1, jit->prg + 14);
498 /* ex 0,0(%r1) */
499 EMIT4_DISP(0x44000000, REG_0, REG_1, 0);
500 }
501 /* j . */
502 EMIT4_PCREL(0xa7f40000, 0);
503 }
504 /* br %r14 */
505 _EMIT2(0x07fe);
506
507 if (IS_ENABLED(CC_USING_EXPOLINE) && !nospec_disable &&
508 (jit->seen & SEEN_FUNC)) {
509 jit->r1_thunk_ip = jit->prg;
510 /* Generate __s390_indirect_jump_r1 thunk */
511 if (test_facility(35)) {
512 /* exrl %r0,.+10 */
513 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10);
514 /* j . */
515 EMIT4_PCREL(0xa7f40000, 0);
516 /* br %r1 */
517 _EMIT2(0x07f1);
518 } else {
519 /* ex 0,S390_lowcore.br_r1_tampoline */
520 EMIT4_DISP(0x44000000, REG_0, REG_0,
521 offsetof(struct lowcore, br_r1_trampoline));
522 /* j . */
523 EMIT4_PCREL(0xa7f40000, 0);
524 }
525 }
526 }
527
528 /*
529 * Compile one eBPF instruction into s390x code
530 *
531 * NOTE: Use noinline because for gcov (-fprofile-arcs) gcc allocates a lot of
532 * stack space for the large switch statement.
533 */
534 static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp, int i)
535 {
536 struct bpf_insn *insn = &fp->insnsi[i];
537 int jmp_off, last, insn_count = 1;
538 unsigned int func_addr, mask;
539 u32 dst_reg = insn->dst_reg;
540 u32 src_reg = insn->src_reg;
541 u32 *addrs = jit->addrs;
542 s32 imm = insn->imm;
543 s16 off = insn->off;
544
545 if (dst_reg == BPF_REG_AX || src_reg == BPF_REG_AX)
546 jit->seen |= SEEN_REG_AX;
547 switch (insn->code) {
548 /*
549 * BPF_MOV
550 */
551 case BPF_ALU | BPF_MOV | BPF_X: /* dst = (u32) src */
552 /* llgfr %dst,%src */
553 EMIT4(0xb9160000, dst_reg, src_reg);
554 break;
555 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */
556 /* lgr %dst,%src */
557 EMIT4(0xb9040000, dst_reg, src_reg);
558 break;
559 case BPF_ALU | BPF_MOV | BPF_K: /* dst = (u32) imm */
560 /* llilf %dst,imm */
561 EMIT6_IMM(0xc00f0000, dst_reg, imm);
562 break;
563 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = imm */
564 /* lgfi %dst,imm */
565 EMIT6_IMM(0xc0010000, dst_reg, imm);
566 break;
567 /*
568 * BPF_LD 64
569 */
570 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */
571 {
572 /* 16 byte instruction that uses two 'struct bpf_insn' */
573 u64 imm64;
574
575 imm64 = (u64)(u32) insn[0].imm | ((u64)(u32) insn[1].imm) << 32;
576 /* lg %dst,<d(imm)>(%l) */
577 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, REG_0, REG_L,
578 EMIT_CONST_U64(imm64));
579 insn_count = 2;
580 break;
581 }
582 /*
583 * BPF_ADD
584 */
585 case BPF_ALU | BPF_ADD | BPF_X: /* dst = (u32) dst + (u32) src */
586 /* ar %dst,%src */
587 EMIT2(0x1a00, dst_reg, src_reg);
588 EMIT_ZERO(dst_reg);
589 break;
590 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst = dst + src */
591 /* agr %dst,%src */
592 EMIT4(0xb9080000, dst_reg, src_reg);
593 break;
594 case BPF_ALU | BPF_ADD | BPF_K: /* dst = (u32) dst + (u32) imm */
595 if (!imm)
596 break;
597 /* alfi %dst,imm */
598 EMIT6_IMM(0xc20b0000, dst_reg, imm);
599 EMIT_ZERO(dst_reg);
600 break;
601 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst = dst + imm */
602 if (!imm)
603 break;
604 /* agfi %dst,imm */
605 EMIT6_IMM(0xc2080000, dst_reg, imm);
606 break;
607 /*
608 * BPF_SUB
609 */
610 case BPF_ALU | BPF_SUB | BPF_X: /* dst = (u32) dst - (u32) src */
611 /* sr %dst,%src */
612 EMIT2(0x1b00, dst_reg, src_reg);
613 EMIT_ZERO(dst_reg);
614 break;
615 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst = dst - src */
616 /* sgr %dst,%src */
617 EMIT4(0xb9090000, dst_reg, src_reg);
618 break;
619 case BPF_ALU | BPF_SUB | BPF_K: /* dst = (u32) dst - (u32) imm */
620 if (!imm)
621 break;
622 /* alfi %dst,-imm */
623 EMIT6_IMM(0xc20b0000, dst_reg, -imm);
624 EMIT_ZERO(dst_reg);
625 break;
626 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst = dst - imm */
627 if (!imm)
628 break;
629 /* agfi %dst,-imm */
630 EMIT6_IMM(0xc2080000, dst_reg, -imm);
631 break;
632 /*
633 * BPF_MUL
634 */
635 case BPF_ALU | BPF_MUL | BPF_X: /* dst = (u32) dst * (u32) src */
636 /* msr %dst,%src */
637 EMIT4(0xb2520000, dst_reg, src_reg);
638 EMIT_ZERO(dst_reg);
639 break;
640 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst = dst * src */
641 /* msgr %dst,%src */
642 EMIT4(0xb90c0000, dst_reg, src_reg);
643 break;
644 case BPF_ALU | BPF_MUL | BPF_K: /* dst = (u32) dst * (u32) imm */
645 if (imm == 1)
646 break;
647 /* msfi %r5,imm */
648 EMIT6_IMM(0xc2010000, dst_reg, imm);
649 EMIT_ZERO(dst_reg);
650 break;
651 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst = dst * imm */
652 if (imm == 1)
653 break;
654 /* msgfi %dst,imm */
655 EMIT6_IMM(0xc2000000, dst_reg, imm);
656 break;
657 /*
658 * BPF_DIV / BPF_MOD
659 */
660 case BPF_ALU | BPF_DIV | BPF_X: /* dst = (u32) dst / (u32) src */
661 case BPF_ALU | BPF_MOD | BPF_X: /* dst = (u32) dst % (u32) src */
662 {
663 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
664
665 jit->seen |= SEEN_RET0;
666 /* ltr %src,%src (if src == 0 goto fail) */
667 EMIT2(0x1200, src_reg, src_reg);
668 /* jz <ret0> */
669 EMIT4_PCREL(0xa7840000, jit->ret0_ip - jit->prg);
670 /* lhi %w0,0 */
671 EMIT4_IMM(0xa7080000, REG_W0, 0);
672 /* lr %w1,%dst */
673 EMIT2(0x1800, REG_W1, dst_reg);
674 /* dlr %w0,%src */
675 EMIT4(0xb9970000, REG_W0, src_reg);
676 /* llgfr %dst,%rc */
677 EMIT4(0xb9160000, dst_reg, rc_reg);
678 break;
679 }
680 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst = dst / src */
681 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst = dst % src */
682 {
683 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
684
685 jit->seen |= SEEN_RET0;
686 /* ltgr %src,%src (if src == 0 goto fail) */
687 EMIT4(0xb9020000, src_reg, src_reg);
688 /* jz <ret0> */
689 EMIT4_PCREL(0xa7840000, jit->ret0_ip - jit->prg);
690 /* lghi %w0,0 */
691 EMIT4_IMM(0xa7090000, REG_W0, 0);
692 /* lgr %w1,%dst */
693 EMIT4(0xb9040000, REG_W1, dst_reg);
694 /* dlgr %w0,%dst */
695 EMIT4(0xb9870000, REG_W0, src_reg);
696 /* lgr %dst,%rc */
697 EMIT4(0xb9040000, dst_reg, rc_reg);
698 break;
699 }
700 case BPF_ALU | BPF_DIV | BPF_K: /* dst = (u32) dst / (u32) imm */
701 case BPF_ALU | BPF_MOD | BPF_K: /* dst = (u32) dst % (u32) imm */
702 {
703 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
704
705 if (imm == 1) {
706 if (BPF_OP(insn->code) == BPF_MOD)
707 /* lhgi %dst,0 */
708 EMIT4_IMM(0xa7090000, dst_reg, 0);
709 break;
710 }
711 /* lhi %w0,0 */
712 EMIT4_IMM(0xa7080000, REG_W0, 0);
713 /* lr %w1,%dst */
714 EMIT2(0x1800, REG_W1, dst_reg);
715 /* dl %w0,<d(imm)>(%l) */
716 EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0, REG_L,
717 EMIT_CONST_U32(imm));
718 /* llgfr %dst,%rc */
719 EMIT4(0xb9160000, dst_reg, rc_reg);
720 break;
721 }
722 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst = dst / imm */
723 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst = dst % imm */
724 {
725 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
726
727 if (imm == 1) {
728 if (BPF_OP(insn->code) == BPF_MOD)
729 /* lhgi %dst,0 */
730 EMIT4_IMM(0xa7090000, dst_reg, 0);
731 break;
732 }
733 /* lghi %w0,0 */
734 EMIT4_IMM(0xa7090000, REG_W0, 0);
735 /* lgr %w1,%dst */
736 EMIT4(0xb9040000, REG_W1, dst_reg);
737 /* dlg %w0,<d(imm)>(%l) */
738 EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0, REG_L,
739 EMIT_CONST_U64(imm));
740 /* lgr %dst,%rc */
741 EMIT4(0xb9040000, dst_reg, rc_reg);
742 break;
743 }
744 /*
745 * BPF_AND
746 */
747 case BPF_ALU | BPF_AND | BPF_X: /* dst = (u32) dst & (u32) src */
748 /* nr %dst,%src */
749 EMIT2(0x1400, dst_reg, src_reg);
750 EMIT_ZERO(dst_reg);
751 break;
752 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */
753 /* ngr %dst,%src */
754 EMIT4(0xb9800000, dst_reg, src_reg);
755 break;
756 case BPF_ALU | BPF_AND | BPF_K: /* dst = (u32) dst & (u32) imm */
757 /* nilf %dst,imm */
758 EMIT6_IMM(0xc00b0000, dst_reg, imm);
759 EMIT_ZERO(dst_reg);
760 break;
761 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */
762 /* ng %dst,<d(imm)>(%l) */
763 EMIT6_DISP_LH(0xe3000000, 0x0080, dst_reg, REG_0, REG_L,
764 EMIT_CONST_U64(imm));
765 break;
766 /*
767 * BPF_OR
768 */
769 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */
770 /* or %dst,%src */
771 EMIT2(0x1600, dst_reg, src_reg);
772 EMIT_ZERO(dst_reg);
773 break;
774 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */
775 /* ogr %dst,%src */
776 EMIT4(0xb9810000, dst_reg, src_reg);
777 break;
778 case BPF_ALU | BPF_OR | BPF_K: /* dst = (u32) dst | (u32) imm */
779 /* oilf %dst,imm */
780 EMIT6_IMM(0xc00d0000, dst_reg, imm);
781 EMIT_ZERO(dst_reg);
782 break;
783 case BPF_ALU64 | BPF_OR | BPF_K: /* dst = dst | imm */
784 /* og %dst,<d(imm)>(%l) */
785 EMIT6_DISP_LH(0xe3000000, 0x0081, dst_reg, REG_0, REG_L,
786 EMIT_CONST_U64(imm));
787 break;
788 /*
789 * BPF_XOR
790 */
791 case BPF_ALU | BPF_XOR | BPF_X: /* dst = (u32) dst ^ (u32) src */
792 /* xr %dst,%src */
793 EMIT2(0x1700, dst_reg, src_reg);
794 EMIT_ZERO(dst_reg);
795 break;
796 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst = dst ^ src */
797 /* xgr %dst,%src */
798 EMIT4(0xb9820000, dst_reg, src_reg);
799 break;
800 case BPF_ALU | BPF_XOR | BPF_K: /* dst = (u32) dst ^ (u32) imm */
801 if (!imm)
802 break;
803 /* xilf %dst,imm */
804 EMIT6_IMM(0xc0070000, dst_reg, imm);
805 EMIT_ZERO(dst_reg);
806 break;
807 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst = dst ^ imm */
808 /* xg %dst,<d(imm)>(%l) */
809 EMIT6_DISP_LH(0xe3000000, 0x0082, dst_reg, REG_0, REG_L,
810 EMIT_CONST_U64(imm));
811 break;
812 /*
813 * BPF_LSH
814 */
815 case BPF_ALU | BPF_LSH | BPF_X: /* dst = (u32) dst << (u32) src */
816 /* sll %dst,0(%src) */
817 EMIT4_DISP(0x89000000, dst_reg, src_reg, 0);
818 EMIT_ZERO(dst_reg);
819 break;
820 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst = dst << src */
821 /* sllg %dst,%dst,0(%src) */
822 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, src_reg, 0);
823 break;
824 case BPF_ALU | BPF_LSH | BPF_K: /* dst = (u32) dst << (u32) imm */
825 if (imm == 0)
826 break;
827 /* sll %dst,imm(%r0) */
828 EMIT4_DISP(0x89000000, dst_reg, REG_0, imm);
829 EMIT_ZERO(dst_reg);
830 break;
831 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst = dst << imm */
832 if (imm == 0)
833 break;
834 /* sllg %dst,%dst,imm(%r0) */
835 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, REG_0, imm);
836 break;
837 /*
838 * BPF_RSH
839 */
840 case BPF_ALU | BPF_RSH | BPF_X: /* dst = (u32) dst >> (u32) src */
841 /* srl %dst,0(%src) */
842 EMIT4_DISP(0x88000000, dst_reg, src_reg, 0);
843 EMIT_ZERO(dst_reg);
844 break;
845 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst = dst >> src */
846 /* srlg %dst,%dst,0(%src) */
847 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, src_reg, 0);
848 break;
849 case BPF_ALU | BPF_RSH | BPF_K: /* dst = (u32) dst >> (u32) imm */
850 if (imm == 0)
851 break;
852 /* srl %dst,imm(%r0) */
853 EMIT4_DISP(0x88000000, dst_reg, REG_0, imm);
854 EMIT_ZERO(dst_reg);
855 break;
856 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst = dst >> imm */
857 if (imm == 0)
858 break;
859 /* srlg %dst,%dst,imm(%r0) */
860 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, REG_0, imm);
861 break;
862 /*
863 * BPF_ARSH
864 */
865 case BPF_ALU64 | BPF_ARSH | BPF_X: /* ((s64) dst) >>= src */
866 /* srag %dst,%dst,0(%src) */
867 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, src_reg, 0);
868 break;
869 case BPF_ALU64 | BPF_ARSH | BPF_K: /* ((s64) dst) >>= imm */
870 if (imm == 0)
871 break;
872 /* srag %dst,%dst,imm(%r0) */
873 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, REG_0, imm);
874 break;
875 /*
876 * BPF_NEG
877 */
878 case BPF_ALU | BPF_NEG: /* dst = (u32) -dst */
879 /* lcr %dst,%dst */
880 EMIT2(0x1300, dst_reg, dst_reg);
881 EMIT_ZERO(dst_reg);
882 break;
883 case BPF_ALU64 | BPF_NEG: /* dst = -dst */
884 /* lcgr %dst,%dst */
885 EMIT4(0xb9030000, dst_reg, dst_reg);
886 break;
887 /*
888 * BPF_FROM_BE/LE
889 */
890 case BPF_ALU | BPF_END | BPF_FROM_BE:
891 /* s390 is big endian, therefore only clear high order bytes */
892 switch (imm) {
893 case 16: /* dst = (u16) cpu_to_be16(dst) */
894 /* llghr %dst,%dst */
895 EMIT4(0xb9850000, dst_reg, dst_reg);
896 break;
897 case 32: /* dst = (u32) cpu_to_be32(dst) */
898 /* llgfr %dst,%dst */
899 EMIT4(0xb9160000, dst_reg, dst_reg);
900 break;
901 case 64: /* dst = (u64) cpu_to_be64(dst) */
902 break;
903 }
904 break;
905 case BPF_ALU | BPF_END | BPF_FROM_LE:
906 switch (imm) {
907 case 16: /* dst = (u16) cpu_to_le16(dst) */
908 /* lrvr %dst,%dst */
909 EMIT4(0xb91f0000, dst_reg, dst_reg);
910 /* srl %dst,16(%r0) */
911 EMIT4_DISP(0x88000000, dst_reg, REG_0, 16);
912 /* llghr %dst,%dst */
913 EMIT4(0xb9850000, dst_reg, dst_reg);
914 break;
915 case 32: /* dst = (u32) cpu_to_le32(dst) */
916 /* lrvr %dst,%dst */
917 EMIT4(0xb91f0000, dst_reg, dst_reg);
918 /* llgfr %dst,%dst */
919 EMIT4(0xb9160000, dst_reg, dst_reg);
920 break;
921 case 64: /* dst = (u64) cpu_to_le64(dst) */
922 /* lrvgr %dst,%dst */
923 EMIT4(0xb90f0000, dst_reg, dst_reg);
924 break;
925 }
926 break;
927 /*
928 * BPF_ST(X)
929 */
930 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src_reg */
931 /* stcy %src,off(%dst) */
932 EMIT6_DISP_LH(0xe3000000, 0x0072, src_reg, dst_reg, REG_0, off);
933 jit->seen |= SEEN_MEM;
934 break;
935 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */
936 /* sthy %src,off(%dst) */
937 EMIT6_DISP_LH(0xe3000000, 0x0070, src_reg, dst_reg, REG_0, off);
938 jit->seen |= SEEN_MEM;
939 break;
940 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */
941 /* sty %src,off(%dst) */
942 EMIT6_DISP_LH(0xe3000000, 0x0050, src_reg, dst_reg, REG_0, off);
943 jit->seen |= SEEN_MEM;
944 break;
945 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */
946 /* stg %src,off(%dst) */
947 EMIT6_DISP_LH(0xe3000000, 0x0024, src_reg, dst_reg, REG_0, off);
948 jit->seen |= SEEN_MEM;
949 break;
950 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */
951 /* lhi %w0,imm */
952 EMIT4_IMM(0xa7080000, REG_W0, (u8) imm);
953 /* stcy %w0,off(dst) */
954 EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg, REG_0, off);
955 jit->seen |= SEEN_MEM;
956 break;
957 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */
958 /* lhi %w0,imm */
959 EMIT4_IMM(0xa7080000, REG_W0, (u16) imm);
960 /* sthy %w0,off(dst) */
961 EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg, REG_0, off);
962 jit->seen |= SEEN_MEM;
963 break;
964 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */
965 /* llilf %w0,imm */
966 EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm);
967 /* sty %w0,off(%dst) */
968 EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg, REG_0, off);
969 jit->seen |= SEEN_MEM;
970 break;
971 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */
972 /* lgfi %w0,imm */
973 EMIT6_IMM(0xc0010000, REG_W0, imm);
974 /* stg %w0,off(%dst) */
975 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg, REG_0, off);
976 jit->seen |= SEEN_MEM;
977 break;
978 /*
979 * BPF_STX XADD (atomic_add)
980 */
981 case BPF_STX | BPF_XADD | BPF_W: /* *(u32 *)(dst + off) += src */
982 /* laal %w0,%src,off(%dst) */
983 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W0, src_reg,
984 dst_reg, off);
985 jit->seen |= SEEN_MEM;
986 break;
987 case BPF_STX | BPF_XADD | BPF_DW: /* *(u64 *)(dst + off) += src */
988 /* laalg %w0,%src,off(%dst) */
989 EMIT6_DISP_LH(0xeb000000, 0x00ea, REG_W0, src_reg,
990 dst_reg, off);
991 jit->seen |= SEEN_MEM;
992 break;
993 /*
994 * BPF_LDX
995 */
996 case BPF_LDX | BPF_MEM | BPF_B: /* dst = *(u8 *)(ul) (src + off) */
997 /* llgc %dst,0(off,%src) */
998 EMIT6_DISP_LH(0xe3000000, 0x0090, dst_reg, src_reg, REG_0, off);
999 jit->seen |= SEEN_MEM;
1000 break;
1001 case BPF_LDX | BPF_MEM | BPF_H: /* dst = *(u16 *)(ul) (src + off) */
1002 /* llgh %dst,0(off,%src) */
1003 EMIT6_DISP_LH(0xe3000000, 0x0091, dst_reg, src_reg, REG_0, off);
1004 jit->seen |= SEEN_MEM;
1005 break;
1006 case BPF_LDX | BPF_MEM | BPF_W: /* dst = *(u32 *)(ul) (src + off) */
1007 /* llgf %dst,off(%src) */
1008 jit->seen |= SEEN_MEM;
1009 EMIT6_DISP_LH(0xe3000000, 0x0016, dst_reg, src_reg, REG_0, off);
1010 break;
1011 case BPF_LDX | BPF_MEM | BPF_DW: /* dst = *(u64 *)(ul) (src + off) */
1012 /* lg %dst,0(off,%src) */
1013 jit->seen |= SEEN_MEM;
1014 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, src_reg, REG_0, off);
1015 break;
1016 /*
1017 * BPF_JMP / CALL
1018 */
1019 case BPF_JMP | BPF_CALL:
1020 {
1021 /*
1022 * b0 = (__bpf_call_base + imm)(b1, b2, b3, b4, b5)
1023 */
1024 const u64 func = (u64)__bpf_call_base + imm;
1025
1026 REG_SET_SEEN(BPF_REG_5);
1027 jit->seen |= SEEN_FUNC;
1028 /* lg %w1,<d(imm)>(%l) */
1029 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_W1, REG_0, REG_L,
1030 EMIT_CONST_U64(func));
1031 if (IS_ENABLED(CC_USING_EXPOLINE) && !nospec_disable) {
1032 /* brasl %r14,__s390_indirect_jump_r1 */
1033 EMIT6_PCREL_RILB(0xc0050000, REG_14, jit->r1_thunk_ip);
1034 } else {
1035 /* basr %r14,%w1 */
1036 EMIT2(0x0d00, REG_14, REG_W1);
1037 }
1038 /* lgr %b0,%r2: load return value into %b0 */
1039 EMIT4(0xb9040000, BPF_REG_0, REG_2);
1040 if ((jit->seen & SEEN_SKB) &&
1041 bpf_helper_changes_pkt_data((void *)func)) {
1042 /* lg %b1,ST_OFF_SKBP(%r15) */
1043 EMIT6_DISP_LH(0xe3000000, 0x0004, BPF_REG_1, REG_0,
1044 REG_15, STK_OFF_SKBP);
1045 emit_load_skb_data_hlen(jit);
1046 }
1047 break;
1048 }
1049 case BPF_JMP | BPF_TAIL_CALL:
1050 /*
1051 * Implicit input:
1052 * B1: pointer to ctx
1053 * B2: pointer to bpf_array
1054 * B3: index in bpf_array
1055 */
1056 jit->seen |= SEEN_TAIL_CALL;
1057
1058 /*
1059 * if (index >= array->map.max_entries)
1060 * goto out;
1061 */
1062
1063 /* llgf %w1,map.max_entries(%b2) */
1064 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_2,
1065 offsetof(struct bpf_array, map.max_entries));
1066 /* clrj %b3,%w1,0xa,label0: if (u32)%b3 >= (u32)%w1 goto out */
1067 EMIT6_PCREL_LABEL(0xec000000, 0x0077, BPF_REG_3,
1068 REG_W1, 0, 0xa);
1069
1070 /*
1071 * if (tail_call_cnt++ > MAX_TAIL_CALL_CNT)
1072 * goto out;
1073 */
1074
1075 if (jit->seen & SEEN_STACK)
1076 off = STK_OFF_TCCNT + STK_OFF;
1077 else
1078 off = STK_OFF_TCCNT;
1079 /* lhi %w0,1 */
1080 EMIT4_IMM(0xa7080000, REG_W0, 1);
1081 /* laal %w1,%w0,off(%r15) */
1082 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1, REG_W0, REG_15, off);
1083 /* clij %w1,MAX_TAIL_CALL_CNT,0x2,label0 */
1084 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007f, REG_W1,
1085 MAX_TAIL_CALL_CNT, 0, 0x2);
1086
1087 /*
1088 * prog = array->ptrs[index];
1089 * if (prog == NULL)
1090 * goto out;
1091 */
1092
1093 /* llgfr %r1,%b3: %r1 = (u32) index */
1094 EMIT4(0xb9160000, REG_1, BPF_REG_3);
1095 /* sllg %r1,%r1,3: %r1 *= 8 */
1096 EMIT6_DISP_LH(0xeb000000, 0x000d, REG_1, REG_1, REG_0, 3);
1097 /* lg %r1,prog(%b2,%r1) */
1098 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, BPF_REG_2,
1099 REG_1, offsetof(struct bpf_array, ptrs));
1100 /* clgij %r1,0,0x8,label0 */
1101 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007d, REG_1, 0, 0, 0x8);
1102
1103 /*
1104 * Restore registers before calling function
1105 */
1106 save_restore_regs(jit, REGS_RESTORE);
1107
1108 /*
1109 * goto *(prog->bpf_func + tail_call_start);
1110 */
1111
1112 /* lg %r1,bpf_func(%r1) */
1113 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, REG_1, REG_0,
1114 offsetof(struct bpf_prog, bpf_func));
1115 /* bc 0xf,tail_call_start(%r1) */
1116 _EMIT4(0x47f01000 + jit->tail_call_start);
1117 /* out: */
1118 jit->labels[0] = jit->prg;
1119 break;
1120 case BPF_JMP | BPF_EXIT: /* return b0 */
1121 last = (i == fp->len - 1) ? 1 : 0;
1122 if (last && !(jit->seen & SEEN_RET0))
1123 break;
1124 /* j <exit> */
1125 EMIT4_PCREL(0xa7f40000, jit->exit_ip - jit->prg);
1126 break;
1127 /*
1128 * Branch relative (number of skipped instructions) to offset on
1129 * condition.
1130 *
1131 * Condition code to mask mapping:
1132 *
1133 * CC | Description | Mask
1134 * ------------------------------
1135 * 0 | Operands equal | 8
1136 * 1 | First operand low | 4
1137 * 2 | First operand high | 2
1138 * 3 | Unused | 1
1139 *
1140 * For s390x relative branches: ip = ip + off_bytes
1141 * For BPF relative branches: insn = insn + off_insns + 1
1142 *
1143 * For example for s390x with offset 0 we jump to the branch
1144 * instruction itself (loop) and for BPF with offset 0 we
1145 * branch to the instruction behind the branch.
1146 */
1147 case BPF_JMP | BPF_JA: /* if (true) */
1148 mask = 0xf000; /* j */
1149 goto branch_oc;
1150 case BPF_JMP | BPF_JSGT | BPF_K: /* ((s64) dst > (s64) imm) */
1151 mask = 0x2000; /* jh */
1152 goto branch_ks;
1153 case BPF_JMP | BPF_JSLT | BPF_K: /* ((s64) dst < (s64) imm) */
1154 mask = 0x4000; /* jl */
1155 goto branch_ks;
1156 case BPF_JMP | BPF_JSGE | BPF_K: /* ((s64) dst >= (s64) imm) */
1157 mask = 0xa000; /* jhe */
1158 goto branch_ks;
1159 case BPF_JMP | BPF_JSLE | BPF_K: /* ((s64) dst <= (s64) imm) */
1160 mask = 0xc000; /* jle */
1161 goto branch_ks;
1162 case BPF_JMP | BPF_JGT | BPF_K: /* (dst_reg > imm) */
1163 mask = 0x2000; /* jh */
1164 goto branch_ku;
1165 case BPF_JMP | BPF_JLT | BPF_K: /* (dst_reg < imm) */
1166 mask = 0x4000; /* jl */
1167 goto branch_ku;
1168 case BPF_JMP | BPF_JGE | BPF_K: /* (dst_reg >= imm) */
1169 mask = 0xa000; /* jhe */
1170 goto branch_ku;
1171 case BPF_JMP | BPF_JLE | BPF_K: /* (dst_reg <= imm) */
1172 mask = 0xc000; /* jle */
1173 goto branch_ku;
1174 case BPF_JMP | BPF_JNE | BPF_K: /* (dst_reg != imm) */
1175 mask = 0x7000; /* jne */
1176 goto branch_ku;
1177 case BPF_JMP | BPF_JEQ | BPF_K: /* (dst_reg == imm) */
1178 mask = 0x8000; /* je */
1179 goto branch_ku;
1180 case BPF_JMP | BPF_JSET | BPF_K: /* (dst_reg & imm) */
1181 mask = 0x7000; /* jnz */
1182 /* lgfi %w1,imm (load sign extend imm) */
1183 EMIT6_IMM(0xc0010000, REG_W1, imm);
1184 /* ngr %w1,%dst */
1185 EMIT4(0xb9800000, REG_W1, dst_reg);
1186 goto branch_oc;
1187
1188 case BPF_JMP | BPF_JSGT | BPF_X: /* ((s64) dst > (s64) src) */
1189 mask = 0x2000; /* jh */
1190 goto branch_xs;
1191 case BPF_JMP | BPF_JSLT | BPF_X: /* ((s64) dst < (s64) src) */
1192 mask = 0x4000; /* jl */
1193 goto branch_xs;
1194 case BPF_JMP | BPF_JSGE | BPF_X: /* ((s64) dst >= (s64) src) */
1195 mask = 0xa000; /* jhe */
1196 goto branch_xs;
1197 case BPF_JMP | BPF_JSLE | BPF_X: /* ((s64) dst <= (s64) src) */
1198 mask = 0xc000; /* jle */
1199 goto branch_xs;
1200 case BPF_JMP | BPF_JGT | BPF_X: /* (dst > src) */
1201 mask = 0x2000; /* jh */
1202 goto branch_xu;
1203 case BPF_JMP | BPF_JLT | BPF_X: /* (dst < src) */
1204 mask = 0x4000; /* jl */
1205 goto branch_xu;
1206 case BPF_JMP | BPF_JGE | BPF_X: /* (dst >= src) */
1207 mask = 0xa000; /* jhe */
1208 goto branch_xu;
1209 case BPF_JMP | BPF_JLE | BPF_X: /* (dst <= src) */
1210 mask = 0xc000; /* jle */
1211 goto branch_xu;
1212 case BPF_JMP | BPF_JNE | BPF_X: /* (dst != src) */
1213 mask = 0x7000; /* jne */
1214 goto branch_xu;
1215 case BPF_JMP | BPF_JEQ | BPF_X: /* (dst == src) */
1216 mask = 0x8000; /* je */
1217 goto branch_xu;
1218 case BPF_JMP | BPF_JSET | BPF_X: /* (dst & src) */
1219 mask = 0x7000; /* jnz */
1220 /* ngrk %w1,%dst,%src */
1221 EMIT4_RRF(0xb9e40000, REG_W1, dst_reg, src_reg);
1222 goto branch_oc;
1223 branch_ks:
1224 /* lgfi %w1,imm (load sign extend imm) */
1225 EMIT6_IMM(0xc0010000, REG_W1, imm);
1226 /* cgrj %dst,%w1,mask,off */
1227 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, REG_W1, i, off, mask);
1228 break;
1229 branch_ku:
1230 /* lgfi %w1,imm (load sign extend imm) */
1231 EMIT6_IMM(0xc0010000, REG_W1, imm);
1232 /* clgrj %dst,%w1,mask,off */
1233 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, REG_W1, i, off, mask);
1234 break;
1235 branch_xs:
1236 /* cgrj %dst,%src,mask,off */
1237 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, src_reg, i, off, mask);
1238 break;
1239 branch_xu:
1240 /* clgrj %dst,%src,mask,off */
1241 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, src_reg, i, off, mask);
1242 break;
1243 branch_oc:
1244 /* brc mask,jmp_off (branch instruction needs 4 bytes) */
1245 jmp_off = addrs[i + off + 1] - (addrs[i + 1] - 4);
1246 EMIT4_PCREL(0xa7040000 | mask << 8, jmp_off);
1247 break;
1248 /*
1249 * BPF_LD
1250 */
1251 case BPF_LD | BPF_ABS | BPF_B: /* b0 = *(u8 *) (skb->data+imm) */
1252 case BPF_LD | BPF_IND | BPF_B: /* b0 = *(u8 *) (skb->data+imm+src) */
1253 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1254 func_addr = __pa(sk_load_byte_pos);
1255 else
1256 func_addr = __pa(sk_load_byte);
1257 goto call_fn;
1258 case BPF_LD | BPF_ABS | BPF_H: /* b0 = *(u16 *) (skb->data+imm) */
1259 case BPF_LD | BPF_IND | BPF_H: /* b0 = *(u16 *) (skb->data+imm+src) */
1260 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1261 func_addr = __pa(sk_load_half_pos);
1262 else
1263 func_addr = __pa(sk_load_half);
1264 goto call_fn;
1265 case BPF_LD | BPF_ABS | BPF_W: /* b0 = *(u32 *) (skb->data+imm) */
1266 case BPF_LD | BPF_IND | BPF_W: /* b0 = *(u32 *) (skb->data+imm+src) */
1267 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1268 func_addr = __pa(sk_load_word_pos);
1269 else
1270 func_addr = __pa(sk_load_word);
1271 goto call_fn;
1272 call_fn:
1273 jit->seen |= SEEN_SKB | SEEN_RET0 | SEEN_FUNC;
1274 REG_SET_SEEN(REG_14); /* Return address of possible func call */
1275
1276 /*
1277 * Implicit input:
1278 * BPF_REG_6 (R7) : skb pointer
1279 * REG_SKB_DATA (R12): skb data pointer (if no BPF_REG_AX)
1280 *
1281 * Calculated input:
1282 * BPF_REG_2 (R3) : offset of byte(s) to fetch in skb
1283 * BPF_REG_5 (R6) : return address
1284 *
1285 * Output:
1286 * BPF_REG_0 (R14): data read from skb
1287 *
1288 * Scratch registers (BPF_REG_1-5)
1289 */
1290
1291 /* Call function: llilf %w1,func_addr */
1292 EMIT6_IMM(0xc00f0000, REG_W1, func_addr);
1293
1294 /* Offset: lgfi %b2,imm */
1295 EMIT6_IMM(0xc0010000, BPF_REG_2, imm);
1296 if (BPF_MODE(insn->code) == BPF_IND)
1297 /* agfr %b2,%src (%src is s32 here) */
1298 EMIT4(0xb9180000, BPF_REG_2, src_reg);
1299
1300 /* Reload REG_SKB_DATA if BPF_REG_AX is used */
1301 if (jit->seen & SEEN_REG_AX)
1302 /* lg %skb_data,data_off(%b6) */
1303 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_SKB_DATA, REG_0,
1304 BPF_REG_6, offsetof(struct sk_buff, data));
1305 /* basr %b5,%w1 (%b5 is call saved) */
1306 EMIT2(0x0d00, BPF_REG_5, REG_W1);
1307
1308 /*
1309 * Note: For fast access we jump directly after the
1310 * jnz instruction from bpf_jit.S
1311 */
1312 /* jnz <ret0> */
1313 EMIT4_PCREL(0xa7740000, jit->ret0_ip - jit->prg);
1314 break;
1315 default: /* too complex, give up */
1316 pr_err("Unknown opcode %02x\n", insn->code);
1317 return -1;
1318 }
1319 return insn_count;
1320 }
1321
1322 /*
1323 * Compile eBPF program into s390x code
1324 */
1325 static int bpf_jit_prog(struct bpf_jit *jit, struct bpf_prog *fp)
1326 {
1327 int i, insn_count;
1328
1329 jit->lit = jit->lit_start;
1330 jit->prg = 0;
1331
1332 bpf_jit_prologue(jit);
1333 for (i = 0; i < fp->len; i += insn_count) {
1334 insn_count = bpf_jit_insn(jit, fp, i);
1335 if (insn_count < 0)
1336 return -1;
1337 /* Next instruction address */
1338 jit->addrs[i + insn_count] = jit->prg;
1339 }
1340 bpf_jit_epilogue(jit);
1341
1342 jit->lit_start = jit->prg;
1343 jit->size = jit->lit;
1344 jit->size_prg = jit->prg;
1345 return 0;
1346 }
1347
1348 /*
1349 * Compile eBPF program "fp"
1350 */
1351 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *fp)
1352 {
1353 struct bpf_prog *tmp, *orig_fp = fp;
1354 struct bpf_binary_header *header;
1355 bool tmp_blinded = false;
1356 struct bpf_jit jit;
1357 int pass;
1358
1359 if (!bpf_jit_enable)
1360 return orig_fp;
1361
1362 tmp = bpf_jit_blind_constants(fp);
1363 /*
1364 * If blinding was requested and we failed during blinding,
1365 * we must fall back to the interpreter.
1366 */
1367 if (IS_ERR(tmp))
1368 return orig_fp;
1369 if (tmp != fp) {
1370 tmp_blinded = true;
1371 fp = tmp;
1372 }
1373
1374 memset(&jit, 0, sizeof(jit));
1375 jit.addrs = kcalloc(fp->len + 1, sizeof(*jit.addrs), GFP_KERNEL);
1376 if (jit.addrs == NULL) {
1377 fp = orig_fp;
1378 goto out;
1379 }
1380 /*
1381 * Three initial passes:
1382 * - 1/2: Determine clobbered registers
1383 * - 3: Calculate program size and addrs arrray
1384 */
1385 for (pass = 1; pass <= 3; pass++) {
1386 if (bpf_jit_prog(&jit, fp)) {
1387 fp = orig_fp;
1388 goto free_addrs;
1389 }
1390 }
1391 /*
1392 * Final pass: Allocate and generate program
1393 */
1394 if (jit.size >= BPF_SIZE_MAX) {
1395 fp = orig_fp;
1396 goto free_addrs;
1397 }
1398 header = bpf_jit_binary_alloc(jit.size, &jit.prg_buf, 2, jit_fill_hole);
1399 if (!header) {
1400 fp = orig_fp;
1401 goto free_addrs;
1402 }
1403 if (bpf_jit_prog(&jit, fp)) {
1404 bpf_jit_binary_free(header);
1405 fp = orig_fp;
1406 goto free_addrs;
1407 }
1408 if (bpf_jit_enable > 1) {
1409 bpf_jit_dump(fp->len, jit.size, pass, jit.prg_buf);
1410 print_fn_code(jit.prg_buf, jit.size_prg);
1411 }
1412 bpf_jit_binary_lock_ro(header);
1413 fp->bpf_func = (void *) jit.prg_buf;
1414 fp->jited = 1;
1415 fp->jited_len = jit.size;
1416 free_addrs:
1417 kfree(jit.addrs);
1418 out:
1419 if (tmp_blinded)
1420 bpf_jit_prog_release_other(fp, fp == orig_fp ?
1421 tmp : orig_fp);
1422 return fp;
1423 }
Linux with added FPC-III support