mm: fix exec activate_mm vs TLB shootdown and lazy tlb switching race
[linux/fpc-iii.git] / arch / x86 / events / amd / core.c
blobc3ec535fd36b84d4e92c1ccea8d6d3ce64073ce9
1 #include <linux/perf_event.h>
2 #include <linux/export.h>
3 #include <linux/types.h>
4 #include <linux/init.h>
5 #include <linux/slab.h>
6 #include <linux/delay.h>
7 #include <linux/jiffies.h>
8 #include <asm/apicdef.h>
9 #include <asm/nmi.h>
11 #include "../perf_event.h"
13 static DEFINE_PER_CPU(unsigned long, perf_nmi_tstamp);
14 static unsigned long perf_nmi_window;
16 static __initconst const u64 amd_hw_cache_event_ids
17 [PERF_COUNT_HW_CACHE_MAX]
18 [PERF_COUNT_HW_CACHE_OP_MAX]
19 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
21 [ C(L1D) ] = {
22 [ C(OP_READ) ] = {
23 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
24 [ C(RESULT_MISS) ] = 0x0141, /* Data Cache Misses */
26 [ C(OP_WRITE) ] = {
27 [ C(RESULT_ACCESS) ] = 0,
28 [ C(RESULT_MISS) ] = 0,
30 [ C(OP_PREFETCH) ] = {
31 [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */
32 [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */
35 [ C(L1I ) ] = {
36 [ C(OP_READ) ] = {
37 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches */
38 [ C(RESULT_MISS) ] = 0x0081, /* Instruction cache misses */
40 [ C(OP_WRITE) ] = {
41 [ C(RESULT_ACCESS) ] = -1,
42 [ C(RESULT_MISS) ] = -1,
44 [ C(OP_PREFETCH) ] = {
45 [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */
46 [ C(RESULT_MISS) ] = 0,
49 [ C(LL ) ] = {
50 [ C(OP_READ) ] = {
51 [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */
52 [ C(RESULT_MISS) ] = 0x037E, /* L2 Cache Misses : IC+DC */
54 [ C(OP_WRITE) ] = {
55 [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback */
56 [ C(RESULT_MISS) ] = 0,
58 [ C(OP_PREFETCH) ] = {
59 [ C(RESULT_ACCESS) ] = 0,
60 [ C(RESULT_MISS) ] = 0,
63 [ C(DTLB) ] = {
64 [ C(OP_READ) ] = {
65 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
66 [ C(RESULT_MISS) ] = 0x0746, /* L1_DTLB_AND_L2_DLTB_MISS.ALL */
68 [ C(OP_WRITE) ] = {
69 [ C(RESULT_ACCESS) ] = 0,
70 [ C(RESULT_MISS) ] = 0,
72 [ C(OP_PREFETCH) ] = {
73 [ C(RESULT_ACCESS) ] = 0,
74 [ C(RESULT_MISS) ] = 0,
77 [ C(ITLB) ] = {
78 [ C(OP_READ) ] = {
79 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes */
80 [ C(RESULT_MISS) ] = 0x0385, /* L1_ITLB_AND_L2_ITLB_MISS.ALL */
82 [ C(OP_WRITE) ] = {
83 [ C(RESULT_ACCESS) ] = -1,
84 [ C(RESULT_MISS) ] = -1,
86 [ C(OP_PREFETCH) ] = {
87 [ C(RESULT_ACCESS) ] = -1,
88 [ C(RESULT_MISS) ] = -1,
91 [ C(BPU ) ] = {
92 [ C(OP_READ) ] = {
93 [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr. */
94 [ C(RESULT_MISS) ] = 0x00c3, /* Retired Mispredicted BI */
96 [ C(OP_WRITE) ] = {
97 [ C(RESULT_ACCESS) ] = -1,
98 [ C(RESULT_MISS) ] = -1,
100 [ C(OP_PREFETCH) ] = {
101 [ C(RESULT_ACCESS) ] = -1,
102 [ C(RESULT_MISS) ] = -1,
105 [ C(NODE) ] = {
106 [ C(OP_READ) ] = {
107 [ C(RESULT_ACCESS) ] = 0xb8e9, /* CPU Request to Memory, l+r */
108 [ C(RESULT_MISS) ] = 0x98e9, /* CPU Request to Memory, r */
110 [ C(OP_WRITE) ] = {
111 [ C(RESULT_ACCESS) ] = -1,
112 [ C(RESULT_MISS) ] = -1,
114 [ C(OP_PREFETCH) ] = {
115 [ C(RESULT_ACCESS) ] = -1,
116 [ C(RESULT_MISS) ] = -1,
121 static __initconst const u64 amd_hw_cache_event_ids_f17h
122 [PERF_COUNT_HW_CACHE_MAX]
123 [PERF_COUNT_HW_CACHE_OP_MAX]
124 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
125 [C(L1D)] = {
126 [C(OP_READ)] = {
127 [C(RESULT_ACCESS)] = 0x0040, /* Data Cache Accesses */
128 [C(RESULT_MISS)] = 0xc860, /* L2$ access from DC Miss */
130 [C(OP_WRITE)] = {
131 [C(RESULT_ACCESS)] = 0,
132 [C(RESULT_MISS)] = 0,
134 [C(OP_PREFETCH)] = {
135 [C(RESULT_ACCESS)] = 0xff5a, /* h/w prefetch DC Fills */
136 [C(RESULT_MISS)] = 0,
139 [C(L1I)] = {
140 [C(OP_READ)] = {
141 [C(RESULT_ACCESS)] = 0x0080, /* Instruction cache fetches */
142 [C(RESULT_MISS)] = 0x0081, /* Instruction cache misses */
144 [C(OP_WRITE)] = {
145 [C(RESULT_ACCESS)] = -1,
146 [C(RESULT_MISS)] = -1,
148 [C(OP_PREFETCH)] = {
149 [C(RESULT_ACCESS)] = 0,
150 [C(RESULT_MISS)] = 0,
153 [C(LL)] = {
154 [C(OP_READ)] = {
155 [C(RESULT_ACCESS)] = 0,
156 [C(RESULT_MISS)] = 0,
158 [C(OP_WRITE)] = {
159 [C(RESULT_ACCESS)] = 0,
160 [C(RESULT_MISS)] = 0,
162 [C(OP_PREFETCH)] = {
163 [C(RESULT_ACCESS)] = 0,
164 [C(RESULT_MISS)] = 0,
167 [C(DTLB)] = {
168 [C(OP_READ)] = {
169 [C(RESULT_ACCESS)] = 0xff45, /* All L2 DTLB accesses */
170 [C(RESULT_MISS)] = 0xf045, /* L2 DTLB misses (PT walks) */
172 [C(OP_WRITE)] = {
173 [C(RESULT_ACCESS)] = 0,
174 [C(RESULT_MISS)] = 0,
176 [C(OP_PREFETCH)] = {
177 [C(RESULT_ACCESS)] = 0,
178 [C(RESULT_MISS)] = 0,
181 [C(ITLB)] = {
182 [C(OP_READ)] = {
183 [C(RESULT_ACCESS)] = 0x0084, /* L1 ITLB misses, L2 ITLB hits */
184 [C(RESULT_MISS)] = 0xff85, /* L1 ITLB misses, L2 misses */
186 [C(OP_WRITE)] = {
187 [C(RESULT_ACCESS)] = -1,
188 [C(RESULT_MISS)] = -1,
190 [C(OP_PREFETCH)] = {
191 [C(RESULT_ACCESS)] = -1,
192 [C(RESULT_MISS)] = -1,
195 [C(BPU)] = {
196 [C(OP_READ)] = {
197 [C(RESULT_ACCESS)] = 0x00c2, /* Retired Branch Instr. */
198 [C(RESULT_MISS)] = 0x00c3, /* Retired Mispredicted BI */
200 [C(OP_WRITE)] = {
201 [C(RESULT_ACCESS)] = -1,
202 [C(RESULT_MISS)] = -1,
204 [C(OP_PREFETCH)] = {
205 [C(RESULT_ACCESS)] = -1,
206 [C(RESULT_MISS)] = -1,
209 [C(NODE)] = {
210 [C(OP_READ)] = {
211 [C(RESULT_ACCESS)] = 0,
212 [C(RESULT_MISS)] = 0,
214 [C(OP_WRITE)] = {
215 [C(RESULT_ACCESS)] = -1,
216 [C(RESULT_MISS)] = -1,
218 [C(OP_PREFETCH)] = {
219 [C(RESULT_ACCESS)] = -1,
220 [C(RESULT_MISS)] = -1,
226 * AMD Performance Monitor K7 and later, up to and including Family 16h:
228 static const u64 amd_perfmon_event_map[PERF_COUNT_HW_MAX] =
230 [PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
231 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
232 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x077d,
233 [PERF_COUNT_HW_CACHE_MISSES] = 0x077e,
234 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2,
235 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3,
236 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00d0, /* "Decoder empty" event */
237 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x00d1, /* "Dispatch stalls" event */
241 * AMD Performance Monitor Family 17h and later:
243 static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] =
245 [PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
246 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
247 [PERF_COUNT_HW_CACHE_REFERENCES] = 0xff60,
248 [PERF_COUNT_HW_CACHE_MISSES] = 0x0964,
249 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2,
250 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3,
251 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x0287,
252 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x0187,
255 static u64 amd_pmu_event_map(int hw_event)
257 if (boot_cpu_data.x86 >= 0x17)
258 return amd_f17h_perfmon_event_map[hw_event];
260 return amd_perfmon_event_map[hw_event];
264 * Previously calculated offsets
266 static unsigned int event_offsets[X86_PMC_IDX_MAX] __read_mostly;
267 static unsigned int count_offsets[X86_PMC_IDX_MAX] __read_mostly;
270 * Legacy CPUs:
271 * 4 counters starting at 0xc0010000 each offset by 1
273 * CPUs with core performance counter extensions:
274 * 6 counters starting at 0xc0010200 each offset by 2
276 static inline int amd_pmu_addr_offset(int index, bool eventsel)
278 int offset;
280 if (!index)
281 return index;
283 if (eventsel)
284 offset = event_offsets[index];
285 else
286 offset = count_offsets[index];
288 if (offset)
289 return offset;
291 if (!boot_cpu_has(X86_FEATURE_PERFCTR_CORE))
292 offset = index;
293 else
294 offset = index << 1;
296 if (eventsel)
297 event_offsets[index] = offset;
298 else
299 count_offsets[index] = offset;
301 return offset;
304 static int amd_core_hw_config(struct perf_event *event)
306 if (event->attr.exclude_host && event->attr.exclude_guest)
308 * When HO == GO == 1 the hardware treats that as GO == HO == 0
309 * and will count in both modes. We don't want to count in that
310 * case so we emulate no-counting by setting US = OS = 0.
312 event->hw.config &= ~(ARCH_PERFMON_EVENTSEL_USR |
313 ARCH_PERFMON_EVENTSEL_OS);
314 else if (event->attr.exclude_host)
315 event->hw.config |= AMD64_EVENTSEL_GUESTONLY;
316 else if (event->attr.exclude_guest)
317 event->hw.config |= AMD64_EVENTSEL_HOSTONLY;
319 return 0;
323 * AMD64 events are detected based on their event codes.
325 static inline unsigned int amd_get_event_code(struct hw_perf_event *hwc)
327 return ((hwc->config >> 24) & 0x0f00) | (hwc->config & 0x00ff);
330 static inline int amd_is_nb_event(struct hw_perf_event *hwc)
332 return (hwc->config & 0xe0) == 0xe0;
335 static inline int amd_has_nb(struct cpu_hw_events *cpuc)
337 struct amd_nb *nb = cpuc->amd_nb;
339 return nb && nb->nb_id != -1;
342 static int amd_pmu_hw_config(struct perf_event *event)
344 int ret;
346 /* pass precise event sampling to ibs: */
347 if (event->attr.precise_ip && get_ibs_caps())
348 return -ENOENT;
350 if (has_branch_stack(event))
351 return -EOPNOTSUPP;
353 ret = x86_pmu_hw_config(event);
354 if (ret)
355 return ret;
357 if (event->attr.type == PERF_TYPE_RAW)
358 event->hw.config |= event->attr.config & AMD64_RAW_EVENT_MASK;
360 return amd_core_hw_config(event);
363 static void __amd_put_nb_event_constraints(struct cpu_hw_events *cpuc,
364 struct perf_event *event)
366 struct amd_nb *nb = cpuc->amd_nb;
367 int i;
370 * need to scan whole list because event may not have
371 * been assigned during scheduling
373 * no race condition possible because event can only
374 * be removed on one CPU at a time AND PMU is disabled
375 * when we come here
377 for (i = 0; i < x86_pmu.num_counters; i++) {
378 if (cmpxchg(nb->owners + i, event, NULL) == event)
379 break;
384 * AMD64 NorthBridge events need special treatment because
385 * counter access needs to be synchronized across all cores
386 * of a package. Refer to BKDG section 3.12
388 * NB events are events measuring L3 cache, Hypertransport
389 * traffic. They are identified by an event code >= 0xe00.
390 * They measure events on the NorthBride which is shared
391 * by all cores on a package. NB events are counted on a
392 * shared set of counters. When a NB event is programmed
393 * in a counter, the data actually comes from a shared
394 * counter. Thus, access to those counters needs to be
395 * synchronized.
397 * We implement the synchronization such that no two cores
398 * can be measuring NB events using the same counters. Thus,
399 * we maintain a per-NB allocation table. The available slot
400 * is propagated using the event_constraint structure.
402 * We provide only one choice for each NB event based on
403 * the fact that only NB events have restrictions. Consequently,
404 * if a counter is available, there is a guarantee the NB event
405 * will be assigned to it. If no slot is available, an empty
406 * constraint is returned and scheduling will eventually fail
407 * for this event.
409 * Note that all cores attached the same NB compete for the same
410 * counters to host NB events, this is why we use atomic ops. Some
411 * multi-chip CPUs may have more than one NB.
413 * Given that resources are allocated (cmpxchg), they must be
414 * eventually freed for others to use. This is accomplished by
415 * calling __amd_put_nb_event_constraints()
417 * Non NB events are not impacted by this restriction.
419 static struct event_constraint *
420 __amd_get_nb_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
421 struct event_constraint *c)
423 struct hw_perf_event *hwc = &event->hw;
424 struct amd_nb *nb = cpuc->amd_nb;
425 struct perf_event *old;
426 int idx, new = -1;
428 if (!c)
429 c = &unconstrained;
431 if (cpuc->is_fake)
432 return c;
435 * detect if already present, if so reuse
437 * cannot merge with actual allocation
438 * because of possible holes
440 * event can already be present yet not assigned (in hwc->idx)
441 * because of successive calls to x86_schedule_events() from
442 * hw_perf_group_sched_in() without hw_perf_enable()
444 for_each_set_bit(idx, c->idxmsk, x86_pmu.num_counters) {
445 if (new == -1 || hwc->idx == idx)
446 /* assign free slot, prefer hwc->idx */
447 old = cmpxchg(nb->owners + idx, NULL, event);
448 else if (nb->owners[idx] == event)
449 /* event already present */
450 old = event;
451 else
452 continue;
454 if (old && old != event)
455 continue;
457 /* reassign to this slot */
458 if (new != -1)
459 cmpxchg(nb->owners + new, event, NULL);
460 new = idx;
462 /* already present, reuse */
463 if (old == event)
464 break;
467 if (new == -1)
468 return &emptyconstraint;
470 return &nb->event_constraints[new];
473 static struct amd_nb *amd_alloc_nb(int cpu)
475 struct amd_nb *nb;
476 int i;
478 nb = kzalloc_node(sizeof(struct amd_nb), GFP_KERNEL, cpu_to_node(cpu));
479 if (!nb)
480 return NULL;
482 nb->nb_id = -1;
485 * initialize all possible NB constraints
487 for (i = 0; i < x86_pmu.num_counters; i++) {
488 __set_bit(i, nb->event_constraints[i].idxmsk);
489 nb->event_constraints[i].weight = 1;
491 return nb;
494 static int amd_pmu_cpu_prepare(int cpu)
496 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
498 WARN_ON_ONCE(cpuc->amd_nb);
500 if (!x86_pmu.amd_nb_constraints)
501 return 0;
503 cpuc->amd_nb = amd_alloc_nb(cpu);
504 if (!cpuc->amd_nb)
505 return -ENOMEM;
507 return 0;
510 static void amd_pmu_cpu_starting(int cpu)
512 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
513 void **onln = &cpuc->kfree_on_online[X86_PERF_KFREE_SHARED];
514 struct amd_nb *nb;
515 int i, nb_id;
517 cpuc->perf_ctr_virt_mask = AMD64_EVENTSEL_HOSTONLY;
519 if (!x86_pmu.amd_nb_constraints)
520 return;
522 nb_id = amd_get_nb_id(cpu);
523 WARN_ON_ONCE(nb_id == BAD_APICID);
525 for_each_online_cpu(i) {
526 nb = per_cpu(cpu_hw_events, i).amd_nb;
527 if (WARN_ON_ONCE(!nb))
528 continue;
530 if (nb->nb_id == nb_id) {
531 *onln = cpuc->amd_nb;
532 cpuc->amd_nb = nb;
533 break;
537 cpuc->amd_nb->nb_id = nb_id;
538 cpuc->amd_nb->refcnt++;
541 static void amd_pmu_cpu_dead(int cpu)
543 struct cpu_hw_events *cpuhw;
545 if (!x86_pmu.amd_nb_constraints)
546 return;
548 cpuhw = &per_cpu(cpu_hw_events, cpu);
550 if (cpuhw->amd_nb) {
551 struct amd_nb *nb = cpuhw->amd_nb;
553 if (nb->nb_id == -1 || --nb->refcnt == 0)
554 kfree(nb);
556 cpuhw->amd_nb = NULL;
561 * When a PMC counter overflows, an NMI is used to process the event and
562 * reset the counter. NMI latency can result in the counter being updated
563 * before the NMI can run, which can result in what appear to be spurious
564 * NMIs. This function is intended to wait for the NMI to run and reset
565 * the counter to avoid possible unhandled NMI messages.
567 #define OVERFLOW_WAIT_COUNT 50
569 static void amd_pmu_wait_on_overflow(int idx)
571 unsigned int i;
572 u64 counter;
575 * Wait for the counter to be reset if it has overflowed. This loop
576 * should exit very, very quickly, but just in case, don't wait
577 * forever...
579 for (i = 0; i < OVERFLOW_WAIT_COUNT; i++) {
580 rdmsrl(x86_pmu_event_addr(idx), counter);
581 if (counter & (1ULL << (x86_pmu.cntval_bits - 1)))
582 break;
584 /* Might be in IRQ context, so can't sleep */
585 udelay(1);
589 static void amd_pmu_disable_all(void)
591 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
592 int idx;
594 x86_pmu_disable_all();
597 * This shouldn't be called from NMI context, but add a safeguard here
598 * to return, since if we're in NMI context we can't wait for an NMI
599 * to reset an overflowed counter value.
601 if (in_nmi())
602 return;
605 * Check each counter for overflow and wait for it to be reset by the
606 * NMI if it has overflowed. This relies on the fact that all active
607 * counters are always enabled when this function is caled and
608 * ARCH_PERFMON_EVENTSEL_INT is always set.
610 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
611 if (!test_bit(idx, cpuc->active_mask))
612 continue;
614 amd_pmu_wait_on_overflow(idx);
618 static void amd_pmu_disable_event(struct perf_event *event)
620 x86_pmu_disable_event(event);
623 * This can be called from NMI context (via x86_pmu_stop). The counter
624 * may have overflowed, but either way, we'll never see it get reset
625 * by the NMI if we're already in the NMI. And the NMI latency support
626 * below will take care of any pending NMI that might have been
627 * generated by the overflow.
629 if (in_nmi())
630 return;
632 amd_pmu_wait_on_overflow(event->hw.idx);
636 * Because of NMI latency, if multiple PMC counters are active or other sources
637 * of NMIs are received, the perf NMI handler can handle one or more overflowed
638 * PMC counters outside of the NMI associated with the PMC overflow. If the NMI
639 * doesn't arrive at the LAPIC in time to become a pending NMI, then the kernel
640 * back-to-back NMI support won't be active. This PMC handler needs to take into
641 * account that this can occur, otherwise this could result in unknown NMI
642 * messages being issued. Examples of this is PMC overflow while in the NMI
643 * handler when multiple PMCs are active or PMC overflow while handling some
644 * other source of an NMI.
646 * Attempt to mitigate this by creating an NMI window in which un-handled NMIs
647 * received during this window will be claimed. This prevents extending the
648 * window past when it is possible that latent NMIs should be received. The
649 * per-CPU perf_nmi_tstamp will be set to the window end time whenever perf has
650 * handled a counter. When an un-handled NMI is received, it will be claimed
651 * only if arriving within that window.
653 static int amd_pmu_handle_irq(struct pt_regs *regs)
655 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
656 int active, handled;
659 * Obtain the active count before calling x86_pmu_handle_irq() since
660 * it is possible that x86_pmu_handle_irq() may make a counter
661 * inactive (through x86_pmu_stop).
663 active = __bitmap_weight(cpuc->active_mask, X86_PMC_IDX_MAX);
665 /* Process any counter overflows */
666 handled = x86_pmu_handle_irq(regs);
669 * If a counter was handled, record a timestamp such that un-handled
670 * NMIs will be claimed if arriving within that window.
672 if (handled) {
673 this_cpu_write(perf_nmi_tstamp,
674 jiffies + perf_nmi_window);
676 return handled;
679 if (time_after(jiffies, this_cpu_read(perf_nmi_tstamp)))
680 return NMI_DONE;
682 return NMI_HANDLED;
685 static struct event_constraint *
686 amd_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
687 struct perf_event *event)
690 * if not NB event or no NB, then no constraints
692 if (!(amd_has_nb(cpuc) && amd_is_nb_event(&event->hw)))
693 return &unconstrained;
695 return __amd_get_nb_event_constraints(cpuc, event, NULL);
698 static void amd_put_event_constraints(struct cpu_hw_events *cpuc,
699 struct perf_event *event)
701 if (amd_has_nb(cpuc) && amd_is_nb_event(&event->hw))
702 __amd_put_nb_event_constraints(cpuc, event);
705 PMU_FORMAT_ATTR(event, "config:0-7,32-35");
706 PMU_FORMAT_ATTR(umask, "config:8-15" );
707 PMU_FORMAT_ATTR(edge, "config:18" );
708 PMU_FORMAT_ATTR(inv, "config:23" );
709 PMU_FORMAT_ATTR(cmask, "config:24-31" );
711 static struct attribute *amd_format_attr[] = {
712 &format_attr_event.attr,
713 &format_attr_umask.attr,
714 &format_attr_edge.attr,
715 &format_attr_inv.attr,
716 &format_attr_cmask.attr,
717 NULL,
720 /* AMD Family 15h */
722 #define AMD_EVENT_TYPE_MASK 0x000000F0ULL
724 #define AMD_EVENT_FP 0x00000000ULL ... 0x00000010ULL
725 #define AMD_EVENT_LS 0x00000020ULL ... 0x00000030ULL
726 #define AMD_EVENT_DC 0x00000040ULL ... 0x00000050ULL
727 #define AMD_EVENT_CU 0x00000060ULL ... 0x00000070ULL
728 #define AMD_EVENT_IC_DE 0x00000080ULL ... 0x00000090ULL
729 #define AMD_EVENT_EX_LS 0x000000C0ULL
730 #define AMD_EVENT_DE 0x000000D0ULL
731 #define AMD_EVENT_NB 0x000000E0ULL ... 0x000000F0ULL
734 * AMD family 15h event code/PMC mappings:
736 * type = event_code & 0x0F0:
738 * 0x000 FP PERF_CTL[5:3]
739 * 0x010 FP PERF_CTL[5:3]
740 * 0x020 LS PERF_CTL[5:0]
741 * 0x030 LS PERF_CTL[5:0]
742 * 0x040 DC PERF_CTL[5:0]
743 * 0x050 DC PERF_CTL[5:0]
744 * 0x060 CU PERF_CTL[2:0]
745 * 0x070 CU PERF_CTL[2:0]
746 * 0x080 IC/DE PERF_CTL[2:0]
747 * 0x090 IC/DE PERF_CTL[2:0]
748 * 0x0A0 ---
749 * 0x0B0 ---
750 * 0x0C0 EX/LS PERF_CTL[5:0]
751 * 0x0D0 DE PERF_CTL[2:0]
752 * 0x0E0 NB NB_PERF_CTL[3:0]
753 * 0x0F0 NB NB_PERF_CTL[3:0]
755 * Exceptions:
757 * 0x000 FP PERF_CTL[3], PERF_CTL[5:3] (*)
758 * 0x003 FP PERF_CTL[3]
759 * 0x004 FP PERF_CTL[3], PERF_CTL[5:3] (*)
760 * 0x00B FP PERF_CTL[3]
761 * 0x00D FP PERF_CTL[3]
762 * 0x023 DE PERF_CTL[2:0]
763 * 0x02D LS PERF_CTL[3]
764 * 0x02E LS PERF_CTL[3,0]
765 * 0x031 LS PERF_CTL[2:0] (**)
766 * 0x043 CU PERF_CTL[2:0]
767 * 0x045 CU PERF_CTL[2:0]
768 * 0x046 CU PERF_CTL[2:0]
769 * 0x054 CU PERF_CTL[2:0]
770 * 0x055 CU PERF_CTL[2:0]
771 * 0x08F IC PERF_CTL[0]
772 * 0x187 DE PERF_CTL[0]
773 * 0x188 DE PERF_CTL[0]
774 * 0x0DB EX PERF_CTL[5:0]
775 * 0x0DC LS PERF_CTL[5:0]
776 * 0x0DD LS PERF_CTL[5:0]
777 * 0x0DE LS PERF_CTL[5:0]
778 * 0x0DF LS PERF_CTL[5:0]
779 * 0x1C0 EX PERF_CTL[5:3]
780 * 0x1D6 EX PERF_CTL[5:0]
781 * 0x1D8 EX PERF_CTL[5:0]
783 * (*) depending on the umask all FPU counters may be used
784 * (**) only one unitmask enabled at a time
787 static struct event_constraint amd_f15_PMC0 = EVENT_CONSTRAINT(0, 0x01, 0);
788 static struct event_constraint amd_f15_PMC20 = EVENT_CONSTRAINT(0, 0x07, 0);
789 static struct event_constraint amd_f15_PMC3 = EVENT_CONSTRAINT(0, 0x08, 0);
790 static struct event_constraint amd_f15_PMC30 = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
791 static struct event_constraint amd_f15_PMC50 = EVENT_CONSTRAINT(0, 0x3F, 0);
792 static struct event_constraint amd_f15_PMC53 = EVENT_CONSTRAINT(0, 0x38, 0);
794 static struct event_constraint *
795 amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, int idx,
796 struct perf_event *event)
798 struct hw_perf_event *hwc = &event->hw;
799 unsigned int event_code = amd_get_event_code(hwc);
801 switch (event_code & AMD_EVENT_TYPE_MASK) {
802 case AMD_EVENT_FP:
803 switch (event_code) {
804 case 0x000:
805 if (!(hwc->config & 0x0000F000ULL))
806 break;
807 if (!(hwc->config & 0x00000F00ULL))
808 break;
809 return &amd_f15_PMC3;
810 case 0x004:
811 if (hweight_long(hwc->config & ARCH_PERFMON_EVENTSEL_UMASK) <= 1)
812 break;
813 return &amd_f15_PMC3;
814 case 0x003:
815 case 0x00B:
816 case 0x00D:
817 return &amd_f15_PMC3;
819 return &amd_f15_PMC53;
820 case AMD_EVENT_LS:
821 case AMD_EVENT_DC:
822 case AMD_EVENT_EX_LS:
823 switch (event_code) {
824 case 0x023:
825 case 0x043:
826 case 0x045:
827 case 0x046:
828 case 0x054:
829 case 0x055:
830 return &amd_f15_PMC20;
831 case 0x02D:
832 return &amd_f15_PMC3;
833 case 0x02E:
834 return &amd_f15_PMC30;
835 case 0x031:
836 if (hweight_long(hwc->config & ARCH_PERFMON_EVENTSEL_UMASK) <= 1)
837 return &amd_f15_PMC20;
838 return &emptyconstraint;
839 case 0x1C0:
840 return &amd_f15_PMC53;
841 default:
842 return &amd_f15_PMC50;
844 case AMD_EVENT_CU:
845 case AMD_EVENT_IC_DE:
846 case AMD_EVENT_DE:
847 switch (event_code) {
848 case 0x08F:
849 case 0x187:
850 case 0x188:
851 return &amd_f15_PMC0;
852 case 0x0DB ... 0x0DF:
853 case 0x1D6:
854 case 0x1D8:
855 return &amd_f15_PMC50;
856 default:
857 return &amd_f15_PMC20;
859 case AMD_EVENT_NB:
860 /* moved to uncore.c */
861 return &emptyconstraint;
862 default:
863 return &emptyconstraint;
867 static ssize_t amd_event_sysfs_show(char *page, u64 config)
869 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT) |
870 (config & AMD64_EVENTSEL_EVENT) >> 24;
872 return x86_event_sysfs_show(page, config, event);
875 static __initconst const struct x86_pmu amd_pmu = {
876 .name = "AMD",
877 .handle_irq = amd_pmu_handle_irq,
878 .disable_all = amd_pmu_disable_all,
879 .enable_all = x86_pmu_enable_all,
880 .enable = x86_pmu_enable_event,
881 .disable = amd_pmu_disable_event,
882 .hw_config = amd_pmu_hw_config,
883 .schedule_events = x86_schedule_events,
884 .eventsel = MSR_K7_EVNTSEL0,
885 .perfctr = MSR_K7_PERFCTR0,
886 .addr_offset = amd_pmu_addr_offset,
887 .event_map = amd_pmu_event_map,
888 .max_events = ARRAY_SIZE(amd_perfmon_event_map),
889 .num_counters = AMD64_NUM_COUNTERS,
890 .cntval_bits = 48,
891 .cntval_mask = (1ULL << 48) - 1,
892 .apic = 1,
893 /* use highest bit to detect overflow */
894 .max_period = (1ULL << 47) - 1,
895 .get_event_constraints = amd_get_event_constraints,
896 .put_event_constraints = amd_put_event_constraints,
898 .format_attrs = amd_format_attr,
899 .events_sysfs_show = amd_event_sysfs_show,
901 .cpu_prepare = amd_pmu_cpu_prepare,
902 .cpu_starting = amd_pmu_cpu_starting,
903 .cpu_dead = amd_pmu_cpu_dead,
905 .amd_nb_constraints = 1,
908 static int __init amd_core_pmu_init(void)
910 if (!boot_cpu_has(X86_FEATURE_PERFCTR_CORE))
911 return 0;
913 /* Avoid calulating the value each time in the NMI handler */
914 perf_nmi_window = msecs_to_jiffies(100);
916 switch (boot_cpu_data.x86) {
917 case 0x15:
918 pr_cont("Fam15h ");
919 x86_pmu.get_event_constraints = amd_get_event_constraints_f15h;
920 break;
921 case 0x17:
922 pr_cont("Fam17h ");
924 * In family 17h, there are no event constraints in the PMC hardware.
925 * We fallback to using default amd_get_event_constraints.
927 break;
928 default:
929 pr_err("core perfctr but no constraints; unknown hardware!\n");
930 return -ENODEV;
934 * If core performance counter extensions exists, we must use
935 * MSR_F15H_PERF_CTL/MSR_F15H_PERF_CTR msrs. See also
936 * amd_pmu_addr_offset().
938 x86_pmu.eventsel = MSR_F15H_PERF_CTL;
939 x86_pmu.perfctr = MSR_F15H_PERF_CTR;
940 x86_pmu.num_counters = AMD64_NUM_COUNTERS_CORE;
942 * AMD Core perfctr has separate MSRs for the NB events, see
943 * the amd/uncore.c driver.
945 x86_pmu.amd_nb_constraints = 0;
947 pr_cont("core perfctr, ");
948 return 0;
951 __init int amd_pmu_init(void)
953 int ret;
955 /* Performance-monitoring supported from K7 and later: */
956 if (boot_cpu_data.x86 < 6)
957 return -ENODEV;
959 x86_pmu = amd_pmu;
961 ret = amd_core_pmu_init();
962 if (ret)
963 return ret;
965 if (num_possible_cpus() == 1) {
967 * No point in allocating data structures to serialize
968 * against other CPUs, when there is only the one CPU.
970 x86_pmu.amd_nb_constraints = 0;
973 if (boot_cpu_data.x86 >= 0x17)
974 memcpy(hw_cache_event_ids, amd_hw_cache_event_ids_f17h, sizeof(hw_cache_event_ids));
975 else
976 memcpy(hw_cache_event_ids, amd_hw_cache_event_ids, sizeof(hw_cache_event_ids));
978 return 0;
981 void amd_pmu_enable_virt(void)
983 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
985 cpuc->perf_ctr_virt_mask = 0;
987 /* Reload all events */
988 amd_pmu_disable_all();
989 x86_pmu_enable_all(0);
991 EXPORT_SYMBOL_GPL(amd_pmu_enable_virt);
993 void amd_pmu_disable_virt(void)
995 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
998 * We only mask out the Host-only bit so that host-only counting works
999 * when SVM is disabled. If someone sets up a guest-only counter when
1000 * SVM is disabled the Guest-only bits still gets set and the counter
1001 * will not count anything.
1003 cpuc->perf_ctr_virt_mask = AMD64_EVENTSEL_HOSTONLY;
1005 /* Reload all events */
1006 amd_pmu_disable_all();
1007 x86_pmu_enable_all(0);
1009 EXPORT_SYMBOL_GPL(amd_pmu_disable_virt);