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mm: fix exec activate_mm vs TLB shootdown and lazy tlb switching race
[linux/fpc-iii.git] / arch / x86 / events / core.c
blobc1f7b3cb84a9bace4767bc227a253953c96a8cb2
1 /*
2 * Performance events x86 architecture code
3 *
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
11 *
12 * For licencing details see kernel-base/COPYING
13 */
14
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/export.h>
21 #include <linux/init.h>
22 #include <linux/kdebug.h>
23 #include <linux/sched/mm.h>
24 #include <linux/sched/clock.h>
25 #include <linux/uaccess.h>
26 #include <linux/slab.h>
27 #include <linux/cpu.h>
28 #include <linux/bitops.h>
29 #include <linux/device.h>
30 #include <linux/nospec.h>
31
32 #include <asm/apic.h>
33 #include <asm/stacktrace.h>
34 #include <asm/nmi.h>
35 #include <asm/smp.h>
36 #include <asm/alternative.h>
37 #include <asm/mmu_context.h>
38 #include <asm/tlbflush.h>
39 #include <asm/timer.h>
40 #include <asm/desc.h>
41 #include <asm/ldt.h>
42 #include <asm/unwind.h>
43
44 #include "perf_event.h"
45
46 struct x86_pmu x86_pmu __read_mostly;
47
48 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
49 .enabled = 1,
50 };
51
52 struct static_key rdpmc_always_available = STATIC_KEY_INIT_FALSE;
53
54 u64 __read_mostly hw_cache_event_ids
55 [PERF_COUNT_HW_CACHE_MAX]
56 [PERF_COUNT_HW_CACHE_OP_MAX]
57 [PERF_COUNT_HW_CACHE_RESULT_MAX];
58 u64 __read_mostly hw_cache_extra_regs
59 [PERF_COUNT_HW_CACHE_MAX]
60 [PERF_COUNT_HW_CACHE_OP_MAX]
61 [PERF_COUNT_HW_CACHE_RESULT_MAX];
62
63 /*
64 * Propagate event elapsed time into the generic event.
65 * Can only be executed on the CPU where the event is active.
66 * Returns the delta events processed.
67 */
68 u64 x86_perf_event_update(struct perf_event *event)
69 {
70 struct hw_perf_event *hwc = &event->hw;
71 int shift = 64 - x86_pmu.cntval_bits;
72 u64 prev_raw_count, new_raw_count;
73 int idx = hwc->idx;
74 u64 delta;
75
76 if (idx == INTEL_PMC_IDX_FIXED_BTS)
77 return 0;
78
79 /*
80 * Careful: an NMI might modify the previous event value.
81 *
82 * Our tactic to handle this is to first atomically read and
83 * exchange a new raw count - then add that new-prev delta
84 * count to the generic event atomically:
85 */
86 again:
87 prev_raw_count = local64_read(&hwc->prev_count);
88 rdpmcl(hwc->event_base_rdpmc, new_raw_count);
89
90 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
91 new_raw_count) != prev_raw_count)
92 goto again;
93
94 /*
95 * Now we have the new raw value and have updated the prev
96 * timestamp already. We can now calculate the elapsed delta
97 * (event-)time and add that to the generic event.
98 *
99 * Careful, not all hw sign-extends above the physical width
100 * of the count.
101 */
102 delta = (new_raw_count << shift) - (prev_raw_count << shift);
103 delta >>= shift;
104
105 local64_add(delta, &event->count);
106 local64_sub(delta, &hwc->period_left);
107
108 return new_raw_count;
109 }
110
111 /*
112 * Find and validate any extra registers to set up.
113 */
114 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
115 {
116 struct hw_perf_event_extra *reg;
117 struct extra_reg *er;
118
119 reg = &event->hw.extra_reg;
120
121 if (!x86_pmu.extra_regs)
122 return 0;
123
124 for (er = x86_pmu.extra_regs; er->msr; er++) {
125 if (er->event != (config & er->config_mask))
126 continue;
127 if (event->attr.config1 & ~er->valid_mask)
128 return -EINVAL;
129 /* Check if the extra msrs can be safely accessed*/
130 if (!er->extra_msr_access)
131 return -ENXIO;
132
133 reg->idx = er->idx;
134 reg->config = event->attr.config1;
135 reg->reg = er->msr;
136 break;
137 }
138 return 0;
139 }
140
141 static atomic_t active_events;
142 static atomic_t pmc_refcount;
143 static DEFINE_MUTEX(pmc_reserve_mutex);
144
145 #ifdef CONFIG_X86_LOCAL_APIC
146
147 static bool reserve_pmc_hardware(void)
148 {
149 int i;
150
151 for (i = 0; i < x86_pmu.num_counters; i++) {
152 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
153 goto perfctr_fail;
154 }
155
156 for (i = 0; i < x86_pmu.num_counters; i++) {
157 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
158 goto eventsel_fail;
159 }
160
161 return true;
162
163 eventsel_fail:
164 for (i--; i >= 0; i--)
165 release_evntsel_nmi(x86_pmu_config_addr(i));
166
167 i = x86_pmu.num_counters;
168
169 perfctr_fail:
170 for (i--; i >= 0; i--)
171 release_perfctr_nmi(x86_pmu_event_addr(i));
172
173 return false;
174 }
175
176 static void release_pmc_hardware(void)
177 {
178 int i;
179
180 for (i = 0; i < x86_pmu.num_counters; i++) {
181 release_perfctr_nmi(x86_pmu_event_addr(i));
182 release_evntsel_nmi(x86_pmu_config_addr(i));
183 }
184 }
185
186 #else
187
188 static bool reserve_pmc_hardware(void) { return true; }
189 static void release_pmc_hardware(void) {}
190
191 #endif
192
193 static bool check_hw_exists(void)
194 {
195 u64 val, val_fail = -1, val_new= ~0;
196 int i, reg, reg_fail = -1, ret = 0;
197 int bios_fail = 0;
198 int reg_safe = -1;
199
200 /*
201 * Check to see if the BIOS enabled any of the counters, if so
202 * complain and bail.
203 */
204 for (i = 0; i < x86_pmu.num_counters; i++) {
205 reg = x86_pmu_config_addr(i);
206 ret = rdmsrl_safe(reg, &val);
207 if (ret)
208 goto msr_fail;
209 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
210 bios_fail = 1;
211 val_fail = val;
212 reg_fail = reg;
213 } else {
214 reg_safe = i;
215 }
216 }
217
218 if (x86_pmu.num_counters_fixed) {
219 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
220 ret = rdmsrl_safe(reg, &val);
221 if (ret)
222 goto msr_fail;
223 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
224 if (val & (0x03 << i*4)) {
225 bios_fail = 1;
226 val_fail = val;
227 reg_fail = reg;
228 }
229 }
230 }
231
232 /*
233 * If all the counters are enabled, the below test will always
234 * fail. The tools will also become useless in this scenario.
235 * Just fail and disable the hardware counters.
236 */
237
238 if (reg_safe == -1) {
239 reg = reg_safe;
240 goto msr_fail;
241 }
242
243 /*
244 * Read the current value, change it and read it back to see if it
245 * matches, this is needed to detect certain hardware emulators
246 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
247 */
248 reg = x86_pmu_event_addr(reg_safe);
249 if (rdmsrl_safe(reg, &val))
250 goto msr_fail;
251 val ^= 0xffffUL;
252 ret = wrmsrl_safe(reg, val);
253 ret |= rdmsrl_safe(reg, &val_new);
254 if (ret || val != val_new)
255 goto msr_fail;
256
257 /*
258 * We still allow the PMU driver to operate:
259 */
260 if (bios_fail) {
261 pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
262 pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
263 reg_fail, val_fail);
264 }
265
266 return true;
267
268 msr_fail:
269 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
270 pr_cont("PMU not available due to virtualization, using software events only.\n");
271 } else {
272 pr_cont("Broken PMU hardware detected, using software events only.\n");
273 pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n",
274 reg, val_new);
275 }
276
277 return false;
278 }
279
280 static void hw_perf_event_destroy(struct perf_event *event)
281 {
282 x86_release_hardware();
283 atomic_dec(&active_events);
284 }
285
286 void hw_perf_lbr_event_destroy(struct perf_event *event)
287 {
288 hw_perf_event_destroy(event);
289
290 /* undo the lbr/bts event accounting */
291 x86_del_exclusive(x86_lbr_exclusive_lbr);
292 }
293
294 static inline int x86_pmu_initialized(void)
295 {
296 return x86_pmu.handle_irq != NULL;
297 }
298
299 static inline int
300 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
301 {
302 struct perf_event_attr *attr = &event->attr;
303 unsigned int cache_type, cache_op, cache_result;
304 u64 config, val;
305
306 config = attr->config;
307
308 cache_type = (config >> 0) & 0xff;
309 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
310 return -EINVAL;
311 cache_type = array_index_nospec(cache_type, PERF_COUNT_HW_CACHE_MAX);
312
313 cache_op = (config >> 8) & 0xff;
314 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
315 return -EINVAL;
316 cache_op = array_index_nospec(cache_op, PERF_COUNT_HW_CACHE_OP_MAX);
317
318 cache_result = (config >> 16) & 0xff;
319 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
320 return -EINVAL;
321 cache_result = array_index_nospec(cache_result, PERF_COUNT_HW_CACHE_RESULT_MAX);
322
323 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
324
325 if (val == 0)
326 return -ENOENT;
327
328 if (val == -1)
329 return -EINVAL;
330
331 hwc->config |= val;
332 attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
333 return x86_pmu_extra_regs(val, event);
334 }
335
336 int x86_reserve_hardware(void)
337 {
338 int err = 0;
339
340 if (!atomic_inc_not_zero(&pmc_refcount)) {
341 mutex_lock(&pmc_reserve_mutex);
342 if (atomic_read(&pmc_refcount) == 0) {
343 if (!reserve_pmc_hardware())
344 err = -EBUSY;
345 else
346 reserve_ds_buffers();
347 }
348 if (!err)
349 atomic_inc(&pmc_refcount);
350 mutex_unlock(&pmc_reserve_mutex);
351 }
352
353 return err;
354 }
355
356 void x86_release_hardware(void)
357 {
358 if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) {
359 release_pmc_hardware();
360 release_ds_buffers();
361 mutex_unlock(&pmc_reserve_mutex);
362 }
363 }
364
365 /*
366 * Check if we can create event of a certain type (that no conflicting events
367 * are present).
368 */
369 int x86_add_exclusive(unsigned int what)
370 {
371 int i;
372
373 /*
374 * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
375 * LBR and BTS are still mutually exclusive.
376 */
377 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
378 goto out;
379
380 if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
381 mutex_lock(&pmc_reserve_mutex);
382 for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) {
383 if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i]))
384 goto fail_unlock;
385 }
386 atomic_inc(&x86_pmu.lbr_exclusive[what]);
387 mutex_unlock(&pmc_reserve_mutex);
388 }
389
390 out:
391 atomic_inc(&active_events);
392 return 0;
393
394 fail_unlock:
395 mutex_unlock(&pmc_reserve_mutex);
396 return -EBUSY;
397 }
398
399 void x86_del_exclusive(unsigned int what)
400 {
401 atomic_dec(&active_events);
402
403 /*
404 * See the comment in x86_add_exclusive().
405 */
406 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
407 return;
408
409 atomic_dec(&x86_pmu.lbr_exclusive[what]);
410 }
411
412 int x86_setup_perfctr(struct perf_event *event)
413 {
414 struct perf_event_attr *attr = &event->attr;
415 struct hw_perf_event *hwc = &event->hw;
416 u64 config;
417
418 if (!is_sampling_event(event)) {
419 hwc->sample_period = x86_pmu.max_period;
420 hwc->last_period = hwc->sample_period;
421 local64_set(&hwc->period_left, hwc->sample_period);
422 }
423
424 if (attr->type == PERF_TYPE_RAW)
425 return x86_pmu_extra_regs(event->attr.config, event);
426
427 if (attr->type == PERF_TYPE_HW_CACHE)
428 return set_ext_hw_attr(hwc, event);
429
430 if (attr->config >= x86_pmu.max_events)
431 return -EINVAL;
432
433 attr->config = array_index_nospec((unsigned long)attr->config, x86_pmu.max_events);
434
435 /*
436 * The generic map:
437 */
438 config = x86_pmu.event_map(attr->config);
439
440 if (config == 0)
441 return -ENOENT;
442
443 if (config == -1LL)
444 return -EINVAL;
445
446 hwc->config |= config;
447
448 return 0;
449 }
450
451 /*
452 * check that branch_sample_type is compatible with
453 * settings needed for precise_ip > 1 which implies
454 * using the LBR to capture ALL taken branches at the
455 * priv levels of the measurement
456 */
457 static inline int precise_br_compat(struct perf_event *event)
458 {
459 u64 m = event->attr.branch_sample_type;
460 u64 b = 0;
461
462 /* must capture all branches */
463 if (!(m & PERF_SAMPLE_BRANCH_ANY))
464 return 0;
465
466 m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
467
468 if (!event->attr.exclude_user)
469 b |= PERF_SAMPLE_BRANCH_USER;
470
471 if (!event->attr.exclude_kernel)
472 b |= PERF_SAMPLE_BRANCH_KERNEL;
473
474 /*
475 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
476 */
477
478 return m == b;
479 }
480
481 int x86_pmu_max_precise(void)
482 {
483 int precise = 0;
484
485 /* Support for constant skid */
486 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
487 precise++;
488
489 /* Support for IP fixup */
490 if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
491 precise++;
492
493 if (x86_pmu.pebs_prec_dist)
494 precise++;
495 }
496 return precise;
497 }
498
499 int x86_pmu_hw_config(struct perf_event *event)
500 {
501 if (event->attr.precise_ip) {
502 int precise = x86_pmu_max_precise();
503
504 if (event->attr.precise_ip > precise)
505 return -EOPNOTSUPP;
506
507 /* There's no sense in having PEBS for non sampling events: */
508 if (!is_sampling_event(event))
509 return -EINVAL;
510 }
511 /*
512 * check that PEBS LBR correction does not conflict with
513 * whatever the user is asking with attr->branch_sample_type
514 */
515 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
516 u64 *br_type = &event->attr.branch_sample_type;
517
518 if (has_branch_stack(event)) {
519 if (!precise_br_compat(event))
520 return -EOPNOTSUPP;
521
522 /* branch_sample_type is compatible */
523
524 } else {
525 /*
526 * user did not specify branch_sample_type
527 *
528 * For PEBS fixups, we capture all
529 * the branches at the priv level of the
530 * event.
531 */
532 *br_type = PERF_SAMPLE_BRANCH_ANY;
533
534 if (!event->attr.exclude_user)
535 *br_type |= PERF_SAMPLE_BRANCH_USER;
536
537 if (!event->attr.exclude_kernel)
538 *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
539 }
540 }
541
542 if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK)
543 event->attach_state |= PERF_ATTACH_TASK_DATA;
544
545 /*
546 * Generate PMC IRQs:
547 * (keep 'enabled' bit clear for now)
548 */
549 event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
550
551 /*
552 * Count user and OS events unless requested not to
553 */
554 if (!event->attr.exclude_user)
555 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
556 if (!event->attr.exclude_kernel)
557 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
558
559 if (event->attr.type == PERF_TYPE_RAW)
560 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
561
562 if (event->attr.sample_period && x86_pmu.limit_period) {
563 if (x86_pmu.limit_period(event, event->attr.sample_period) >
564 event->attr.sample_period)
565 return -EINVAL;
566 }
567
568 return x86_setup_perfctr(event);
569 }
570
571 /*
572 * Setup the hardware configuration for a given attr_type
573 */
574 static int __x86_pmu_event_init(struct perf_event *event)
575 {
576 int err;
577
578 if (!x86_pmu_initialized())
579 return -ENODEV;
580
581 err = x86_reserve_hardware();
582 if (err)
583 return err;
584
585 atomic_inc(&active_events);
586 event->destroy = hw_perf_event_destroy;
587
588 event->hw.idx = -1;
589 event->hw.last_cpu = -1;
590 event->hw.last_tag = ~0ULL;
591
592 /* mark unused */
593 event->hw.extra_reg.idx = EXTRA_REG_NONE;
594 event->hw.branch_reg.idx = EXTRA_REG_NONE;
595
596 return x86_pmu.hw_config(event);
597 }
598
599 void x86_pmu_disable_all(void)
600 {
601 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
602 int idx;
603
604 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
605 u64 val;
606
607 if (!test_bit(idx, cpuc->active_mask))
608 continue;
609 rdmsrl(x86_pmu_config_addr(idx), val);
610 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
611 continue;
612 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
613 wrmsrl(x86_pmu_config_addr(idx), val);
614 }
615 }
616
617 /*
618 * There may be PMI landing after enabled=0. The PMI hitting could be before or
619 * after disable_all.
620 *
621 * If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
622 * It will not be re-enabled in the NMI handler again, because enabled=0. After
623 * handling the NMI, disable_all will be called, which will not change the
624 * state either. If PMI hits after disable_all, the PMU is already disabled
625 * before entering NMI handler. The NMI handler will not change the state
626 * either.
627 *
628 * So either situation is harmless.
629 */
630 static void x86_pmu_disable(struct pmu *pmu)
631 {
632 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
633
634 if (!x86_pmu_initialized())
635 return;
636
637 if (!cpuc->enabled)
638 return;
639
640 cpuc->n_added = 0;
641 cpuc->enabled = 0;
642 barrier();
643
644 x86_pmu.disable_all();
645 }
646
647 void x86_pmu_enable_all(int added)
648 {
649 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
650 int idx;
651
652 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
653 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
654
655 if (!test_bit(idx, cpuc->active_mask))
656 continue;
657
658 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
659 }
660 }
661
662 static struct pmu pmu;
663
664 static inline int is_x86_event(struct perf_event *event)
665 {
666 return event->pmu == &pmu;
667 }
668
669 /*
670 * Event scheduler state:
671 *
672 * Assign events iterating over all events and counters, beginning
673 * with events with least weights first. Keep the current iterator
674 * state in struct sched_state.
675 */
676 struct sched_state {
677 int weight;
678 int event; /* event index */
679 int counter; /* counter index */
680 int unassigned; /* number of events to be assigned left */
681 int nr_gp; /* number of GP counters used */
682 unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
683 };
684
685 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
686 #define SCHED_STATES_MAX 2
687
688 struct perf_sched {
689 int max_weight;
690 int max_events;
691 int max_gp;
692 int saved_states;
693 struct event_constraint **constraints;
694 struct sched_state state;
695 struct sched_state saved[SCHED_STATES_MAX];
696 };
697
698 /*
699 * Initialize interator that runs through all events and counters.
700 */
701 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
702 int num, int wmin, int wmax, int gpmax)
703 {
704 int idx;
705
706 memset(sched, 0, sizeof(*sched));
707 sched->max_events = num;
708 sched->max_weight = wmax;
709 sched->max_gp = gpmax;
710 sched->constraints = constraints;
711
712 for (idx = 0; idx < num; idx++) {
713 if (constraints[idx]->weight == wmin)
714 break;
715 }
716
717 sched->state.event = idx; /* start with min weight */
718 sched->state.weight = wmin;
719 sched->state.unassigned = num;
720 }
721
722 static void perf_sched_save_state(struct perf_sched *sched)
723 {
724 if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
725 return;
726
727 sched->saved[sched->saved_states] = sched->state;
728 sched->saved_states++;
729 }
730
731 static bool perf_sched_restore_state(struct perf_sched *sched)
732 {
733 if (!sched->saved_states)
734 return false;
735
736 sched->saved_states--;
737 sched->state = sched->saved[sched->saved_states];
738
739 /* continue with next counter: */
740 clear_bit(sched->state.counter++, sched->state.used);
741
742 return true;
743 }
744
745 /*
746 * Select a counter for the current event to schedule. Return true on
747 * success.
748 */
749 static bool __perf_sched_find_counter(struct perf_sched *sched)
750 {
751 struct event_constraint *c;
752 int idx;
753
754 if (!sched->state.unassigned)
755 return false;
756
757 if (sched->state.event >= sched->max_events)
758 return false;
759
760 c = sched->constraints[sched->state.event];
761 /* Prefer fixed purpose counters */
762 if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
763 idx = INTEL_PMC_IDX_FIXED;
764 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
765 if (!__test_and_set_bit(idx, sched->state.used))
766 goto done;
767 }
768 }
769
770 /* Grab the first unused counter starting with idx */
771 idx = sched->state.counter;
772 for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
773 if (!__test_and_set_bit(idx, sched->state.used)) {
774 if (sched->state.nr_gp++ >= sched->max_gp)
775 return false;
776
777 goto done;
778 }
779 }
780
781 return false;
782
783 done:
784 sched->state.counter = idx;
785
786 if (c->overlap)
787 perf_sched_save_state(sched);
788
789 return true;
790 }
791
792 static bool perf_sched_find_counter(struct perf_sched *sched)
793 {
794 while (!__perf_sched_find_counter(sched)) {
795 if (!perf_sched_restore_state(sched))
796 return false;
797 }
798
799 return true;
800 }
801
802 /*
803 * Go through all unassigned events and find the next one to schedule.
804 * Take events with the least weight first. Return true on success.
805 */
806 static bool perf_sched_next_event(struct perf_sched *sched)
807 {
808 struct event_constraint *c;
809
810 if (!sched->state.unassigned || !--sched->state.unassigned)
811 return false;
812
813 do {
814 /* next event */
815 sched->state.event++;
816 if (sched->state.event >= sched->max_events) {
817 /* next weight */
818 sched->state.event = 0;
819 sched->state.weight++;
820 if (sched->state.weight > sched->max_weight)
821 return false;
822 }
823 c = sched->constraints[sched->state.event];
824 } while (c->weight != sched->state.weight);
825
826 sched->state.counter = 0; /* start with first counter */
827
828 return true;
829 }
830
831 /*
832 * Assign a counter for each event.
833 */
834 int perf_assign_events(struct event_constraint **constraints, int n,
835 int wmin, int wmax, int gpmax, int *assign)
836 {
837 struct perf_sched sched;
838
839 perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax);
840
841 do {
842 if (!perf_sched_find_counter(&sched))
843 break; /* failed */
844 if (assign)
845 assign[sched.state.event] = sched.state.counter;
846 } while (perf_sched_next_event(&sched));
847
848 return sched.state.unassigned;
849 }
850 EXPORT_SYMBOL_GPL(perf_assign_events);
851
852 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
853 {
854 struct event_constraint *c;
855 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
856 struct perf_event *e;
857 int i, wmin, wmax, unsched = 0;
858 struct hw_perf_event *hwc;
859
860 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
861
862 if (x86_pmu.start_scheduling)
863 x86_pmu.start_scheduling(cpuc);
864
865 for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
866 cpuc->event_constraint[i] = NULL;
867 c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]);
868 cpuc->event_constraint[i] = c;
869
870 wmin = min(wmin, c->weight);
871 wmax = max(wmax, c->weight);
872 }
873
874 /*
875 * fastpath, try to reuse previous register
876 */
877 for (i = 0; i < n; i++) {
878 hwc = &cpuc->event_list[i]->hw;
879 c = cpuc->event_constraint[i];
880
881 /* never assigned */
882 if (hwc->idx == -1)
883 break;
884
885 /* constraint still honored */
886 if (!test_bit(hwc->idx, c->idxmsk))
887 break;
888
889 /* not already used */
890 if (test_bit(hwc->idx, used_mask))
891 break;
892
893 __set_bit(hwc->idx, used_mask);
894 if (assign)
895 assign[i] = hwc->idx;
896 }
897
898 /* slow path */
899 if (i != n) {
900 int gpmax = x86_pmu.num_counters;
901
902 /*
903 * Do not allow scheduling of more than half the available
904 * generic counters.
905 *
906 * This helps avoid counter starvation of sibling thread by
907 * ensuring at most half the counters cannot be in exclusive
908 * mode. There is no designated counters for the limits. Any
909 * N/2 counters can be used. This helps with events with
910 * specific counter constraints.
911 */
912 if (is_ht_workaround_enabled() && !cpuc->is_fake &&
913 READ_ONCE(cpuc->excl_cntrs->exclusive_present))
914 gpmax /= 2;
915
916 unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
917 wmax, gpmax, assign);
918 }
919
920 /*
921 * In case of success (unsched = 0), mark events as committed,
922 * so we do not put_constraint() in case new events are added
923 * and fail to be scheduled
924 *
925 * We invoke the lower level commit callback to lock the resource
926 *
927 * We do not need to do all of this in case we are called to
928 * validate an event group (assign == NULL)
929 */
930 if (!unsched && assign) {
931 for (i = 0; i < n; i++) {
932 e = cpuc->event_list[i];
933 e->hw.flags |= PERF_X86_EVENT_COMMITTED;
934 if (x86_pmu.commit_scheduling)
935 x86_pmu.commit_scheduling(cpuc, i, assign[i]);
936 }
937 } else {
938 for (i = 0; i < n; i++) {
939 e = cpuc->event_list[i];
940 /*
941 * do not put_constraint() on comitted events,
942 * because they are good to go
943 */
944 if ((e->hw.flags & PERF_X86_EVENT_COMMITTED))
945 continue;
946
947 /*
948 * release events that failed scheduling
949 */
950 if (x86_pmu.put_event_constraints)
951 x86_pmu.put_event_constraints(cpuc, e);
952 }
953 }
954
955 if (x86_pmu.stop_scheduling)
956 x86_pmu.stop_scheduling(cpuc);
957
958 return unsched ? -EINVAL : 0;
959 }
960
961 /*
962 * dogrp: true if must collect siblings events (group)
963 * returns total number of events and error code
964 */
965 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
966 {
967 struct perf_event *event;
968 int n, max_count;
969
970 max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
971
972 /* current number of events already accepted */
973 n = cpuc->n_events;
974
975 if (is_x86_event(leader)) {
976 if (n >= max_count)
977 return -EINVAL;
978 cpuc->event_list[n] = leader;
979 n++;
980 }
981 if (!dogrp)
982 return n;
983
984 list_for_each_entry(event, &leader->sibling_list, group_entry) {
985 if (!is_x86_event(event) ||
986 event->state <= PERF_EVENT_STATE_OFF)
987 continue;
988
989 if (n >= max_count)
990 return -EINVAL;
991
992 cpuc->event_list[n] = event;
993 n++;
994 }
995 return n;
996 }
997
998 static inline void x86_assign_hw_event(struct perf_event *event,
999 struct cpu_hw_events *cpuc, int i)
1000 {
1001 struct hw_perf_event *hwc = &event->hw;
1002
1003 hwc->idx = cpuc->assign[i];
1004 hwc->last_cpu = smp_processor_id();
1005 hwc->last_tag = ++cpuc->tags[i];
1006
1007 if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
1008 hwc->config_base = 0;
1009 hwc->event_base = 0;
1010 } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
1011 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1012 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
1013 hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
1014 } else {
1015 hwc->config_base = x86_pmu_config_addr(hwc->idx);
1016 hwc->event_base = x86_pmu_event_addr(hwc->idx);
1017 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
1018 }
1019 }
1020
1021 static inline int match_prev_assignment(struct hw_perf_event *hwc,
1022 struct cpu_hw_events *cpuc,
1023 int i)
1024 {
1025 return hwc->idx == cpuc->assign[i] &&
1026 hwc->last_cpu == smp_processor_id() &&
1027 hwc->last_tag == cpuc->tags[i];
1028 }
1029
1030 static void x86_pmu_start(struct perf_event *event, int flags);
1031
1032 static void x86_pmu_enable(struct pmu *pmu)
1033 {
1034 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1035 struct perf_event *event;
1036 struct hw_perf_event *hwc;
1037 int i, added = cpuc->n_added;
1038
1039 if (!x86_pmu_initialized())
1040 return;
1041
1042 if (cpuc->enabled)
1043 return;
1044
1045 if (cpuc->n_added) {
1046 int n_running = cpuc->n_events - cpuc->n_added;
1047 /*
1048 * apply assignment obtained either from
1049 * hw_perf_group_sched_in() or x86_pmu_enable()
1050 *
1051 * step1: save events moving to new counters
1052 */
1053 for (i = 0; i < n_running; i++) {
1054 event = cpuc->event_list[i];
1055 hwc = &event->hw;
1056
1057 /*
1058 * we can avoid reprogramming counter if:
1059 * - assigned same counter as last time
1060 * - running on same CPU as last time
1061 * - no other event has used the counter since
1062 */
1063 if (hwc->idx == -1 ||
1064 match_prev_assignment(hwc, cpuc, i))
1065 continue;
1066
1067 /*
1068 * Ensure we don't accidentally enable a stopped
1069 * counter simply because we rescheduled.
1070 */
1071 if (hwc->state & PERF_HES_STOPPED)
1072 hwc->state |= PERF_HES_ARCH;
1073
1074 x86_pmu_stop(event, PERF_EF_UPDATE);
1075 }
1076
1077 /*
1078 * step2: reprogram moved events into new counters
1079 */
1080 for (i = 0; i < cpuc->n_events; i++) {
1081 event = cpuc->event_list[i];
1082 hwc = &event->hw;
1083
1084 if (!match_prev_assignment(hwc, cpuc, i))
1085 x86_assign_hw_event(event, cpuc, i);
1086 else if (i < n_running)
1087 continue;
1088
1089 if (hwc->state & PERF_HES_ARCH)
1090 continue;
1091
1092 x86_pmu_start(event, PERF_EF_RELOAD);
1093 }
1094 cpuc->n_added = 0;
1095 perf_events_lapic_init();
1096 }
1097
1098 cpuc->enabled = 1;
1099 barrier();
1100
1101 x86_pmu.enable_all(added);
1102 }
1103
1104 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1105
1106 /*
1107 * Set the next IRQ period, based on the hwc->period_left value.
1108 * To be called with the event disabled in hw:
1109 */
1110 int x86_perf_event_set_period(struct perf_event *event)
1111 {
1112 struct hw_perf_event *hwc = &event->hw;
1113 s64 left = local64_read(&hwc->period_left);
1114 s64 period = hwc->sample_period;
1115 int ret = 0, idx = hwc->idx;
1116
1117 if (idx == INTEL_PMC_IDX_FIXED_BTS)
1118 return 0;
1119
1120 /*
1121 * If we are way outside a reasonable range then just skip forward:
1122 */
1123 if (unlikely(left <= -period)) {
1124 left = period;
1125 local64_set(&hwc->period_left, left);
1126 hwc->last_period = period;
1127 ret = 1;
1128 }
1129
1130 if (unlikely(left <= 0)) {
1131 left += period;
1132 local64_set(&hwc->period_left, left);
1133 hwc->last_period = period;
1134 ret = 1;
1135 }
1136 /*
1137 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1138 */
1139 if (unlikely(left < 2))
1140 left = 2;
1141
1142 if (left > x86_pmu.max_period)
1143 left = x86_pmu.max_period;
1144
1145 if (x86_pmu.limit_period)
1146 left = x86_pmu.limit_period(event, left);
1147
1148 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1149
1150 /*
1151 * The hw event starts counting from this event offset,
1152 * mark it to be able to extra future deltas:
1153 */
1154 local64_set(&hwc->prev_count, (u64)-left);
1155
1156 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1157
1158 /*
1159 * Due to erratum on certan cpu we need
1160 * a second write to be sure the register
1161 * is updated properly
1162 */
1163 if (x86_pmu.perfctr_second_write) {
1164 wrmsrl(hwc->event_base,
1165 (u64)(-left) & x86_pmu.cntval_mask);
1166 }
1167
1168 perf_event_update_userpage(event);
1169
1170 return ret;
1171 }
1172
1173 void x86_pmu_enable_event(struct perf_event *event)
1174 {
1175 if (__this_cpu_read(cpu_hw_events.enabled))
1176 __x86_pmu_enable_event(&event->hw,
1177 ARCH_PERFMON_EVENTSEL_ENABLE);
1178 }
1179
1180 /*
1181 * Add a single event to the PMU.
1182 *
1183 * The event is added to the group of enabled events
1184 * but only if it can be scehduled with existing events.
1185 */
1186 static int x86_pmu_add(struct perf_event *event, int flags)
1187 {
1188 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1189 struct hw_perf_event *hwc;
1190 int assign[X86_PMC_IDX_MAX];
1191 int n, n0, ret;
1192
1193 hwc = &event->hw;
1194
1195 n0 = cpuc->n_events;
1196 ret = n = collect_events(cpuc, event, false);
1197 if (ret < 0)
1198 goto out;
1199
1200 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1201 if (!(flags & PERF_EF_START))
1202 hwc->state |= PERF_HES_ARCH;
1203
1204 /*
1205 * If group events scheduling transaction was started,
1206 * skip the schedulability test here, it will be performed
1207 * at commit time (->commit_txn) as a whole.
1208 *
1209 * If commit fails, we'll call ->del() on all events
1210 * for which ->add() was called.
1211 */
1212 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1213 goto done_collect;
1214
1215 ret = x86_pmu.schedule_events(cpuc, n, assign);
1216 if (ret)
1217 goto out;
1218 /*
1219 * copy new assignment, now we know it is possible
1220 * will be used by hw_perf_enable()
1221 */
1222 memcpy(cpuc->assign, assign, n*sizeof(int));
1223
1224 done_collect:
1225 /*
1226 * Commit the collect_events() state. See x86_pmu_del() and
1227 * x86_pmu_*_txn().
1228 */
1229 cpuc->n_events = n;
1230 cpuc->n_added += n - n0;
1231 cpuc->n_txn += n - n0;
1232
1233 if (x86_pmu.add) {
1234 /*
1235 * This is before x86_pmu_enable() will call x86_pmu_start(),
1236 * so we enable LBRs before an event needs them etc..
1237 */
1238 x86_pmu.add(event);
1239 }
1240
1241 ret = 0;
1242 out:
1243 return ret;
1244 }
1245
1246 static void x86_pmu_start(struct perf_event *event, int flags)
1247 {
1248 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1249 int idx = event->hw.idx;
1250
1251 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1252 return;
1253
1254 if (WARN_ON_ONCE(idx == -1))
1255 return;
1256
1257 if (flags & PERF_EF_RELOAD) {
1258 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1259 x86_perf_event_set_period(event);
1260 }
1261
1262 event->hw.state = 0;
1263
1264 cpuc->events[idx] = event;
1265 __set_bit(idx, cpuc->active_mask);
1266 __set_bit(idx, cpuc->running);
1267 x86_pmu.enable(event);
1268 perf_event_update_userpage(event);
1269 }
1270
1271 void perf_event_print_debug(void)
1272 {
1273 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1274 u64 pebs, debugctl;
1275 struct cpu_hw_events *cpuc;
1276 unsigned long flags;
1277 int cpu, idx;
1278
1279 if (!x86_pmu.num_counters)
1280 return;
1281
1282 local_irq_save(flags);
1283
1284 cpu = smp_processor_id();
1285 cpuc = &per_cpu(cpu_hw_events, cpu);
1286
1287 if (x86_pmu.version >= 2) {
1288 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1289 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1290 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1291 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1292
1293 pr_info("\n");
1294 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1295 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1296 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1297 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1298 if (x86_pmu.pebs_constraints) {
1299 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1300 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1301 }
1302 if (x86_pmu.lbr_nr) {
1303 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1304 pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl);
1305 }
1306 }
1307 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1308
1309 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1310 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1311 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1312
1313 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1314
1315 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1316 cpu, idx, pmc_ctrl);
1317 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1318 cpu, idx, pmc_count);
1319 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1320 cpu, idx, prev_left);
1321 }
1322 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1323 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1324
1325 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1326 cpu, idx, pmc_count);
1327 }
1328 local_irq_restore(flags);
1329 }
1330
1331 void x86_pmu_stop(struct perf_event *event, int flags)
1332 {
1333 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1334 struct hw_perf_event *hwc = &event->hw;
1335
1336 if (test_bit(hwc->idx, cpuc->active_mask)) {
1337 x86_pmu.disable(event);
1338 __clear_bit(hwc->idx, cpuc->active_mask);
1339 cpuc->events[hwc->idx] = NULL;
1340 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1341 hwc->state |= PERF_HES_STOPPED;
1342 }
1343
1344 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1345 /*
1346 * Drain the remaining delta count out of a event
1347 * that we are disabling:
1348 */
1349 x86_perf_event_update(event);
1350 hwc->state |= PERF_HES_UPTODATE;
1351 }
1352 }
1353
1354 static void x86_pmu_del(struct perf_event *event, int flags)
1355 {
1356 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1357 int i;
1358
1359 /*
1360 * event is descheduled
1361 */
1362 event->hw.flags &= ~PERF_X86_EVENT_COMMITTED;
1363
1364 /*
1365 * If we're called during a txn, we only need to undo x86_pmu.add.
1366 * The events never got scheduled and ->cancel_txn will truncate
1367 * the event_list.
1368 *
1369 * XXX assumes any ->del() called during a TXN will only be on
1370 * an event added during that same TXN.
1371 */
1372 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1373 goto do_del;
1374
1375 /*
1376 * Not a TXN, therefore cleanup properly.
1377 */
1378 x86_pmu_stop(event, PERF_EF_UPDATE);
1379
1380 for (i = 0; i < cpuc->n_events; i++) {
1381 if (event == cpuc->event_list[i])
1382 break;
1383 }
1384
1385 if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1386 return;
1387
1388 /* If we have a newly added event; make sure to decrease n_added. */
1389 if (i >= cpuc->n_events - cpuc->n_added)
1390 --cpuc->n_added;
1391
1392 if (x86_pmu.put_event_constraints)
1393 x86_pmu.put_event_constraints(cpuc, event);
1394
1395 /* Delete the array entry. */
1396 while (++i < cpuc->n_events) {
1397 cpuc->event_list[i-1] = cpuc->event_list[i];
1398 cpuc->event_constraint[i-1] = cpuc->event_constraint[i];
1399 }
1400 --cpuc->n_events;
1401
1402 perf_event_update_userpage(event);
1403
1404 do_del:
1405 if (x86_pmu.del) {
1406 /*
1407 * This is after x86_pmu_stop(); so we disable LBRs after any
1408 * event can need them etc..
1409 */
1410 x86_pmu.del(event);
1411 }
1412 }
1413
1414 int x86_pmu_handle_irq(struct pt_regs *regs)
1415 {
1416 struct perf_sample_data data;
1417 struct cpu_hw_events *cpuc;
1418 struct perf_event *event;
1419 int idx, handled = 0;
1420 u64 val;
1421
1422 cpuc = this_cpu_ptr(&cpu_hw_events);
1423
1424 /*
1425 * Some chipsets need to unmask the LVTPC in a particular spot
1426 * inside the nmi handler. As a result, the unmasking was pushed
1427 * into all the nmi handlers.
1428 *
1429 * This generic handler doesn't seem to have any issues where the
1430 * unmasking occurs so it was left at the top.
1431 */
1432 apic_write(APIC_LVTPC, APIC_DM_NMI);
1433
1434 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1435 if (!test_bit(idx, cpuc->active_mask))
1436 continue;
1437
1438 event = cpuc->events[idx];
1439
1440 val = x86_perf_event_update(event);
1441 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1442 continue;
1443
1444 /*
1445 * event overflow
1446 */
1447 handled++;
1448 perf_sample_data_init(&data, 0, event->hw.last_period);
1449
1450 if (!x86_perf_event_set_period(event))
1451 continue;
1452
1453 if (perf_event_overflow(event, &data, regs))
1454 x86_pmu_stop(event, 0);
1455 }
1456
1457 if (handled)
1458 inc_irq_stat(apic_perf_irqs);
1459
1460 return handled;
1461 }
1462
1463 void perf_events_lapic_init(void)
1464 {
1465 if (!x86_pmu.apic || !x86_pmu_initialized())
1466 return;
1467
1468 /*
1469 * Always use NMI for PMU
1470 */
1471 apic_write(APIC_LVTPC, APIC_DM_NMI);
1472 }
1473
1474 static int
1475 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1476 {
1477 u64 start_clock;
1478 u64 finish_clock;
1479 int ret;
1480
1481 /*
1482 * All PMUs/events that share this PMI handler should make sure to
1483 * increment active_events for their events.
1484 */
1485 if (!atomic_read(&active_events))
1486 return NMI_DONE;
1487
1488 start_clock = sched_clock();
1489 ret = x86_pmu.handle_irq(regs);
1490 finish_clock = sched_clock();
1491
1492 perf_sample_event_took(finish_clock - start_clock);
1493
1494 return ret;
1495 }
1496 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1497
1498 struct event_constraint emptyconstraint;
1499 struct event_constraint unconstrained;
1500
1501 static int x86_pmu_prepare_cpu(unsigned int cpu)
1502 {
1503 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1504 int i;
1505
1506 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++)
1507 cpuc->kfree_on_online[i] = NULL;
1508 if (x86_pmu.cpu_prepare)
1509 return x86_pmu.cpu_prepare(cpu);
1510 return 0;
1511 }
1512
1513 static int x86_pmu_dead_cpu(unsigned int cpu)
1514 {
1515 if (x86_pmu.cpu_dead)
1516 x86_pmu.cpu_dead(cpu);
1517 return 0;
1518 }
1519
1520 static int x86_pmu_online_cpu(unsigned int cpu)
1521 {
1522 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1523 int i;
1524
1525 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) {
1526 kfree(cpuc->kfree_on_online[i]);
1527 cpuc->kfree_on_online[i] = NULL;
1528 }
1529 return 0;
1530 }
1531
1532 static int x86_pmu_starting_cpu(unsigned int cpu)
1533 {
1534 if (x86_pmu.cpu_starting)
1535 x86_pmu.cpu_starting(cpu);
1536 return 0;
1537 }
1538
1539 static int x86_pmu_dying_cpu(unsigned int cpu)
1540 {
1541 if (x86_pmu.cpu_dying)
1542 x86_pmu.cpu_dying(cpu);
1543 return 0;
1544 }
1545
1546 static void __init pmu_check_apic(void)
1547 {
1548 if (boot_cpu_has(X86_FEATURE_APIC))
1549 return;
1550
1551 x86_pmu.apic = 0;
1552 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1553 pr_info("no hardware sampling interrupt available.\n");
1554
1555 /*
1556 * If we have a PMU initialized but no APIC
1557 * interrupts, we cannot sample hardware
1558 * events (user-space has to fall back and
1559 * sample via a hrtimer based software event):
1560 */
1561 pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1562
1563 }
1564
1565 static struct attribute_group x86_pmu_format_group = {
1566 .name = "format",
1567 .attrs = NULL,
1568 };
1569
1570 /*
1571 * Remove all undefined events (x86_pmu.event_map(id) == 0)
1572 * out of events_attr attributes.
1573 */
1574 static void __init filter_events(struct attribute **attrs)
1575 {
1576 struct device_attribute *d;
1577 struct perf_pmu_events_attr *pmu_attr;
1578 int offset = 0;
1579 int i, j;
1580
1581 for (i = 0; attrs[i]; i++) {
1582 d = (struct device_attribute *)attrs[i];
1583 pmu_attr = container_of(d, struct perf_pmu_events_attr, attr);
1584 /* str trumps id */
1585 if (pmu_attr->event_str)
1586 continue;
1587 if (x86_pmu.event_map(i + offset))
1588 continue;
1589
1590 for (j = i; attrs[j]; j++)
1591 attrs[j] = attrs[j + 1];
1592
1593 /* Check the shifted attr. */
1594 i--;
1595
1596 /*
1597 * event_map() is index based, the attrs array is organized
1598 * by increasing event index. If we shift the events, then
1599 * we need to compensate for the event_map(), otherwise
1600 * we are looking up the wrong event in the map
1601 */
1602 offset++;
1603 }
1604 }
1605
1606 /* Merge two pointer arrays */
1607 __init struct attribute **merge_attr(struct attribute **a, struct attribute **b)
1608 {
1609 struct attribute **new;
1610 int j, i;
1611
1612 for (j = 0; a[j]; j++)
1613 ;
1614 for (i = 0; b[i]; i++)
1615 j++;
1616 j++;
1617
1618 new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
1619 if (!new)
1620 return NULL;
1621
1622 j = 0;
1623 for (i = 0; a[i]; i++)
1624 new[j++] = a[i];
1625 for (i = 0; b[i]; i++)
1626 new[j++] = b[i];
1627 new[j] = NULL;
1628
1629 return new;
1630 }
1631
1632 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page)
1633 {
1634 struct perf_pmu_events_attr *pmu_attr = \
1635 container_of(attr, struct perf_pmu_events_attr, attr);
1636 u64 config = x86_pmu.event_map(pmu_attr->id);
1637
1638 /* string trumps id */
1639 if (pmu_attr->event_str)
1640 return sprintf(page, "%s", pmu_attr->event_str);
1641
1642 return x86_pmu.events_sysfs_show(page, config);
1643 }
1644 EXPORT_SYMBOL_GPL(events_sysfs_show);
1645
1646 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
1647 char *page)
1648 {
1649 struct perf_pmu_events_ht_attr *pmu_attr =
1650 container_of(attr, struct perf_pmu_events_ht_attr, attr);
1651
1652 /*
1653 * Report conditional events depending on Hyper-Threading.
1654 *
1655 * This is overly conservative as usually the HT special
1656 * handling is not needed if the other CPU thread is idle.
1657 *
1658 * Note this does not (and cannot) handle the case when thread
1659 * siblings are invisible, for example with virtualization
1660 * if they are owned by some other guest. The user tool
1661 * has to re-read when a thread sibling gets onlined later.
1662 */
1663 return sprintf(page, "%s",
1664 topology_max_smt_threads() > 1 ?
1665 pmu_attr->event_str_ht :
1666 pmu_attr->event_str_noht);
1667 }
1668
1669 EVENT_ATTR(cpu-cycles, CPU_CYCLES );
1670 EVENT_ATTR(instructions, INSTRUCTIONS );
1671 EVENT_ATTR(cache-references, CACHE_REFERENCES );
1672 EVENT_ATTR(cache-misses, CACHE_MISSES );
1673 EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS );
1674 EVENT_ATTR(branch-misses, BRANCH_MISSES );
1675 EVENT_ATTR(bus-cycles, BUS_CYCLES );
1676 EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND );
1677 EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND );
1678 EVENT_ATTR(ref-cycles, REF_CPU_CYCLES );
1679
1680 static struct attribute *empty_attrs;
1681
1682 static struct attribute *events_attr[] = {
1683 EVENT_PTR(CPU_CYCLES),
1684 EVENT_PTR(INSTRUCTIONS),
1685 EVENT_PTR(CACHE_REFERENCES),
1686 EVENT_PTR(CACHE_MISSES),
1687 EVENT_PTR(BRANCH_INSTRUCTIONS),
1688 EVENT_PTR(BRANCH_MISSES),
1689 EVENT_PTR(BUS_CYCLES),
1690 EVENT_PTR(STALLED_CYCLES_FRONTEND),
1691 EVENT_PTR(STALLED_CYCLES_BACKEND),
1692 EVENT_PTR(REF_CPU_CYCLES),
1693 NULL,
1694 };
1695
1696 static struct attribute_group x86_pmu_events_group = {
1697 .name = "events",
1698 .attrs = events_attr,
1699 };
1700
1701 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1702 {
1703 u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1704 u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1705 bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1706 bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1707 bool any = (config & ARCH_PERFMON_EVENTSEL_ANY);
1708 bool inv = (config & ARCH_PERFMON_EVENTSEL_INV);
1709 ssize_t ret;
1710
1711 /*
1712 * We have whole page size to spend and just little data
1713 * to write, so we can safely use sprintf.
1714 */
1715 ret = sprintf(page, "event=0x%02llx", event);
1716
1717 if (umask)
1718 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1719
1720 if (edge)
1721 ret += sprintf(page + ret, ",edge");
1722
1723 if (pc)
1724 ret += sprintf(page + ret, ",pc");
1725
1726 if (any)
1727 ret += sprintf(page + ret, ",any");
1728
1729 if (inv)
1730 ret += sprintf(page + ret, ",inv");
1731
1732 if (cmask)
1733 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1734
1735 ret += sprintf(page + ret, "\n");
1736
1737 return ret;
1738 }
1739
1740 static struct attribute_group x86_pmu_attr_group;
1741 static struct attribute_group x86_pmu_caps_group;
1742
1743 static int __init init_hw_perf_events(void)
1744 {
1745 struct x86_pmu_quirk *quirk;
1746 int err;
1747
1748 pr_info("Performance Events: ");
1749
1750 switch (boot_cpu_data.x86_vendor) {
1751 case X86_VENDOR_INTEL:
1752 err = intel_pmu_init();
1753 break;
1754 case X86_VENDOR_AMD:
1755 err = amd_pmu_init();
1756 break;
1757 default:
1758 err = -ENOTSUPP;
1759 }
1760 if (err != 0) {
1761 pr_cont("no PMU driver, software events only.\n");
1762 return 0;
1763 }
1764
1765 pmu_check_apic();
1766
1767 /* sanity check that the hardware exists or is emulated */
1768 if (!check_hw_exists())
1769 return 0;
1770
1771 pr_cont("%s PMU driver.\n", x86_pmu.name);
1772
1773 x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
1774
1775 for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1776 quirk->func();
1777
1778 if (!x86_pmu.intel_ctrl)
1779 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1780
1781 perf_events_lapic_init();
1782 register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1783
1784 unconstrained = (struct event_constraint)
1785 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1786 0, x86_pmu.num_counters, 0, 0);
1787
1788 x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1789
1790 if (x86_pmu.caps_attrs) {
1791 struct attribute **tmp;
1792
1793 tmp = merge_attr(x86_pmu_caps_group.attrs, x86_pmu.caps_attrs);
1794 if (!WARN_ON(!tmp))
1795 x86_pmu_caps_group.attrs = tmp;
1796 }
1797
1798 if (x86_pmu.event_attrs)
1799 x86_pmu_events_group.attrs = x86_pmu.event_attrs;
1800
1801 if (!x86_pmu.events_sysfs_show)
1802 x86_pmu_events_group.attrs = &empty_attrs;
1803 else
1804 filter_events(x86_pmu_events_group.attrs);
1805
1806 if (x86_pmu.cpu_events) {
1807 struct attribute **tmp;
1808
1809 tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events);
1810 if (!WARN_ON(!tmp))
1811 x86_pmu_events_group.attrs = tmp;
1812 }
1813
1814 if (x86_pmu.attrs) {
1815 struct attribute **tmp;
1816
1817 tmp = merge_attr(x86_pmu_attr_group.attrs, x86_pmu.attrs);
1818 if (!WARN_ON(!tmp))
1819 x86_pmu_attr_group.attrs = tmp;
1820 }
1821
1822 pr_info("... version: %d\n", x86_pmu.version);
1823 pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
1824 pr_info("... generic registers: %d\n", x86_pmu.num_counters);
1825 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
1826 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1827 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed);
1828 pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl);
1829
1830 /*
1831 * Install callbacks. Core will call them for each online
1832 * cpu.
1833 */
1834 err = cpuhp_setup_state(CPUHP_PERF_X86_PREPARE, "perf/x86:prepare",
1835 x86_pmu_prepare_cpu, x86_pmu_dead_cpu);
1836 if (err)
1837 return err;
1838
1839 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING,
1840 "perf/x86:starting", x86_pmu_starting_cpu,
1841 x86_pmu_dying_cpu);
1842 if (err)
1843 goto out;
1844
1845 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE, "perf/x86:online",
1846 x86_pmu_online_cpu, NULL);
1847 if (err)
1848 goto out1;
1849
1850 err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1851 if (err)
1852 goto out2;
1853
1854 return 0;
1855
1856 out2:
1857 cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE);
1858 out1:
1859 cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING);
1860 out:
1861 cpuhp_remove_state(CPUHP_PERF_X86_PREPARE);
1862 return err;
1863 }
1864 early_initcall(init_hw_perf_events);
1865
1866 static inline void x86_pmu_read(struct perf_event *event)
1867 {
1868 x86_perf_event_update(event);
1869 }
1870
1871 /*
1872 * Start group events scheduling transaction
1873 * Set the flag to make pmu::enable() not perform the
1874 * schedulability test, it will be performed at commit time
1875 *
1876 * We only support PERF_PMU_TXN_ADD transactions. Save the
1877 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1878 * transactions.
1879 */
1880 static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
1881 {
1882 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1883
1884 WARN_ON_ONCE(cpuc->txn_flags); /* txn already in flight */
1885
1886 cpuc->txn_flags = txn_flags;
1887 if (txn_flags & ~PERF_PMU_TXN_ADD)
1888 return;
1889
1890 perf_pmu_disable(pmu);
1891 __this_cpu_write(cpu_hw_events.n_txn, 0);
1892 }
1893
1894 /*
1895 * Stop group events scheduling transaction
1896 * Clear the flag and pmu::enable() will perform the
1897 * schedulability test.
1898 */
1899 static void x86_pmu_cancel_txn(struct pmu *pmu)
1900 {
1901 unsigned int txn_flags;
1902 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1903
1904 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
1905
1906 txn_flags = cpuc->txn_flags;
1907 cpuc->txn_flags = 0;
1908 if (txn_flags & ~PERF_PMU_TXN_ADD)
1909 return;
1910
1911 /*
1912 * Truncate collected array by the number of events added in this
1913 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1914 */
1915 __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1916 __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1917 perf_pmu_enable(pmu);
1918 }
1919
1920 /*
1921 * Commit group events scheduling transaction
1922 * Perform the group schedulability test as a whole
1923 * Return 0 if success
1924 *
1925 * Does not cancel the transaction on failure; expects the caller to do this.
1926 */
1927 static int x86_pmu_commit_txn(struct pmu *pmu)
1928 {
1929 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1930 int assign[X86_PMC_IDX_MAX];
1931 int n, ret;
1932
1933 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
1934
1935 if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) {
1936 cpuc->txn_flags = 0;
1937 return 0;
1938 }
1939
1940 n = cpuc->n_events;
1941
1942 if (!x86_pmu_initialized())
1943 return -EAGAIN;
1944
1945 ret = x86_pmu.schedule_events(cpuc, n, assign);
1946 if (ret)
1947 return ret;
1948
1949 /*
1950 * copy new assignment, now we know it is possible
1951 * will be used by hw_perf_enable()
1952 */
1953 memcpy(cpuc->assign, assign, n*sizeof(int));
1954
1955 cpuc->txn_flags = 0;
1956 perf_pmu_enable(pmu);
1957 return 0;
1958 }
1959 /*
1960 * a fake_cpuc is used to validate event groups. Due to
1961 * the extra reg logic, we need to also allocate a fake
1962 * per_core and per_cpu structure. Otherwise, group events
1963 * using extra reg may conflict without the kernel being
1964 * able to catch this when the last event gets added to
1965 * the group.
1966 */
1967 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1968 {
1969 intel_cpuc_finish(cpuc);
1970 kfree(cpuc);
1971 }
1972
1973 static struct cpu_hw_events *allocate_fake_cpuc(void)
1974 {
1975 struct cpu_hw_events *cpuc;
1976 int cpu = raw_smp_processor_id();
1977
1978 cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1979 if (!cpuc)
1980 return ERR_PTR(-ENOMEM);
1981 cpuc->is_fake = 1;
1982
1983 if (intel_cpuc_prepare(cpuc, cpu))
1984 goto error;
1985
1986 return cpuc;
1987 error:
1988 free_fake_cpuc(cpuc);
1989 return ERR_PTR(-ENOMEM);
1990 }
1991
1992 /*
1993 * validate that we can schedule this event
1994 */
1995 static int validate_event(struct perf_event *event)
1996 {
1997 struct cpu_hw_events *fake_cpuc;
1998 struct event_constraint *c;
1999 int ret = 0;
2000
2001 fake_cpuc = allocate_fake_cpuc();
2002 if (IS_ERR(fake_cpuc))
2003 return PTR_ERR(fake_cpuc);
2004
2005 c = x86_pmu.get_event_constraints(fake_cpuc, -1, event);
2006
2007 if (!c || !c->weight)
2008 ret = -EINVAL;
2009
2010 if (x86_pmu.put_event_constraints)
2011 x86_pmu.put_event_constraints(fake_cpuc, event);
2012
2013 free_fake_cpuc(fake_cpuc);
2014
2015 return ret;
2016 }
2017
2018 /*
2019 * validate a single event group
2020 *
2021 * validation include:
2022 * - check events are compatible which each other
2023 * - events do not compete for the same counter
2024 * - number of events <= number of counters
2025 *
2026 * validation ensures the group can be loaded onto the
2027 * PMU if it was the only group available.
2028 */
2029 static int validate_group(struct perf_event *event)
2030 {
2031 struct perf_event *leader = event->group_leader;
2032 struct cpu_hw_events *fake_cpuc;
2033 int ret = -EINVAL, n;
2034
2035 fake_cpuc = allocate_fake_cpuc();
2036 if (IS_ERR(fake_cpuc))
2037 return PTR_ERR(fake_cpuc);
2038 /*
2039 * the event is not yet connected with its
2040 * siblings therefore we must first collect
2041 * existing siblings, then add the new event
2042 * before we can simulate the scheduling
2043 */
2044 n = collect_events(fake_cpuc, leader, true);
2045 if (n < 0)
2046 goto out;
2047
2048 fake_cpuc->n_events = n;
2049 n = collect_events(fake_cpuc, event, false);
2050 if (n < 0)
2051 goto out;
2052
2053 fake_cpuc->n_events = n;
2054
2055 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
2056
2057 out:
2058 free_fake_cpuc(fake_cpuc);
2059 return ret;
2060 }
2061
2062 static int x86_pmu_event_init(struct perf_event *event)
2063 {
2064 struct pmu *tmp;
2065 int err;
2066
2067 switch (event->attr.type) {
2068 case PERF_TYPE_RAW:
2069 case PERF_TYPE_HARDWARE:
2070 case PERF_TYPE_HW_CACHE:
2071 break;
2072
2073 default:
2074 return -ENOENT;
2075 }
2076
2077 err = __x86_pmu_event_init(event);
2078 if (!err) {
2079 /*
2080 * we temporarily connect event to its pmu
2081 * such that validate_group() can classify
2082 * it as an x86 event using is_x86_event()
2083 */
2084 tmp = event->pmu;
2085 event->pmu = &pmu;
2086
2087 if (event->group_leader != event)
2088 err = validate_group(event);
2089 else
2090 err = validate_event(event);
2091
2092 event->pmu = tmp;
2093 }
2094 if (err) {
2095 if (event->destroy)
2096 event->destroy(event);
2097 }
2098
2099 if (ACCESS_ONCE(x86_pmu.attr_rdpmc))
2100 event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;
2101
2102 return err;
2103 }
2104
2105 static void refresh_pce(void *ignored)
2106 {
2107 load_mm_cr4(this_cpu_read(cpu_tlbstate.loaded_mm));
2108 }
2109
2110 static void x86_pmu_event_mapped(struct perf_event *event, struct mm_struct *mm)
2111 {
2112 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2113 return;
2114
2115 /*
2116 * This function relies on not being called concurrently in two
2117 * tasks in the same mm. Otherwise one task could observe
2118 * perf_rdpmc_allowed > 1 and return all the way back to
2119 * userspace with CR4.PCE clear while another task is still
2120 * doing on_each_cpu_mask() to propagate CR4.PCE.
2121 *
2122 * For now, this can't happen because all callers hold mmap_sem
2123 * for write. If this changes, we'll need a different solution.
2124 */
2125 lockdep_assert_held_exclusive(&mm->mmap_sem);
2126
2127 if (atomic_inc_return(&mm->context.perf_rdpmc_allowed) == 1)
2128 on_each_cpu_mask(mm_cpumask(mm), refresh_pce, NULL, 1);
2129 }
2130
2131 static void x86_pmu_event_unmapped(struct perf_event *event, struct mm_struct *mm)
2132 {
2133
2134 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2135 return;
2136
2137 if (atomic_dec_and_test(&mm->context.perf_rdpmc_allowed))
2138 on_each_cpu_mask(mm_cpumask(mm), refresh_pce, NULL, 1);
2139 }
2140
2141 static int x86_pmu_event_idx(struct perf_event *event)
2142 {
2143 int idx = event->hw.idx;
2144
2145 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2146 return 0;
2147
2148 if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
2149 idx -= INTEL_PMC_IDX_FIXED;
2150 idx |= 1 << 30;
2151 }
2152
2153 return idx + 1;
2154 }
2155
2156 static ssize_t get_attr_rdpmc(struct device *cdev,
2157 struct device_attribute *attr,
2158 char *buf)
2159 {
2160 return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
2161 }
2162
2163 static ssize_t set_attr_rdpmc(struct device *cdev,
2164 struct device_attribute *attr,
2165 const char *buf, size_t count)
2166 {
2167 unsigned long val;
2168 ssize_t ret;
2169
2170 ret = kstrtoul(buf, 0, &val);
2171 if (ret)
2172 return ret;
2173
2174 if (val > 2)
2175 return -EINVAL;
2176
2177 if (x86_pmu.attr_rdpmc_broken)
2178 return -ENOTSUPP;
2179
2180 if ((val == 2) != (x86_pmu.attr_rdpmc == 2)) {
2181 /*
2182 * Changing into or out of always available, aka
2183 * perf-event-bypassing mode. This path is extremely slow,
2184 * but only root can trigger it, so it's okay.
2185 */
2186 if (val == 2)
2187 static_key_slow_inc(&rdpmc_always_available);
2188 else
2189 static_key_slow_dec(&rdpmc_always_available);
2190 on_each_cpu(refresh_pce, NULL, 1);
2191 }
2192
2193 x86_pmu.attr_rdpmc = val;
2194
2195 return count;
2196 }
2197
2198 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
2199
2200 static struct attribute *x86_pmu_attrs[] = {
2201 &dev_attr_rdpmc.attr,
2202 NULL,
2203 };
2204
2205 static struct attribute_group x86_pmu_attr_group = {
2206 .attrs = x86_pmu_attrs,
2207 };
2208
2209 static ssize_t max_precise_show(struct device *cdev,
2210 struct device_attribute *attr,
2211 char *buf)
2212 {
2213 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu_max_precise());
2214 }
2215
2216 static DEVICE_ATTR_RO(max_precise);
2217
2218 static struct attribute *x86_pmu_caps_attrs[] = {
2219 &dev_attr_max_precise.attr,
2220 NULL
2221 };
2222
2223 static struct attribute_group x86_pmu_caps_group = {
2224 .name = "caps",
2225 .attrs = x86_pmu_caps_attrs,
2226 };
2227
2228 static const struct attribute_group *x86_pmu_attr_groups[] = {
2229 &x86_pmu_attr_group,
2230 &x86_pmu_format_group,
2231 &x86_pmu_events_group,
2232 &x86_pmu_caps_group,
2233 NULL,
2234 };
2235
2236 static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
2237 {
2238 if (x86_pmu.sched_task)
2239 x86_pmu.sched_task(ctx, sched_in);
2240 }
2241
2242 void perf_check_microcode(void)
2243 {
2244 if (x86_pmu.check_microcode)
2245 x86_pmu.check_microcode();
2246 }
2247
2248 static int x86_pmu_check_period(struct perf_event *event, u64 value)
2249 {
2250 if (x86_pmu.check_period && x86_pmu.check_period(event, value))
2251 return -EINVAL;
2252
2253 if (value && x86_pmu.limit_period) {
2254 if (x86_pmu.limit_period(event, value) > value)
2255 return -EINVAL;
2256 }
2257
2258 return 0;
2259 }
2260
2261 static struct pmu pmu = {
2262 .pmu_enable = x86_pmu_enable,
2263 .pmu_disable = x86_pmu_disable,
2264
2265 .attr_groups = x86_pmu_attr_groups,
2266
2267 .event_init = x86_pmu_event_init,
2268
2269 .event_mapped = x86_pmu_event_mapped,
2270 .event_unmapped = x86_pmu_event_unmapped,
2271
2272 .add = x86_pmu_add,
2273 .del = x86_pmu_del,
2274 .start = x86_pmu_start,
2275 .stop = x86_pmu_stop,
2276 .read = x86_pmu_read,
2277
2278 .start_txn = x86_pmu_start_txn,
2279 .cancel_txn = x86_pmu_cancel_txn,
2280 .commit_txn = x86_pmu_commit_txn,
2281
2282 .event_idx = x86_pmu_event_idx,
2283 .sched_task = x86_pmu_sched_task,
2284 .task_ctx_size = sizeof(struct x86_perf_task_context),
2285 .check_period = x86_pmu_check_period,
2286 };
2287
2288 void arch_perf_update_userpage(struct perf_event *event,
2289 struct perf_event_mmap_page *userpg, u64 now)
2290 {
2291 struct cyc2ns_data data;
2292 u64 offset;
2293
2294 userpg->cap_user_time = 0;
2295 userpg->cap_user_time_zero = 0;
2296 userpg->cap_user_rdpmc =
2297 !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED);
2298 userpg->pmc_width = x86_pmu.cntval_bits;
2299
2300 if (!using_native_sched_clock() || !sched_clock_stable())
2301 return;
2302
2303 cyc2ns_read_begin(&data);
2304
2305 offset = data.cyc2ns_offset + __sched_clock_offset;
2306
2307 /*
2308 * Internal timekeeping for enabled/running/stopped times
2309 * is always in the local_clock domain.
2310 */
2311 userpg->cap_user_time = 1;
2312 userpg->time_mult = data.cyc2ns_mul;
2313 userpg->time_shift = data.cyc2ns_shift;
2314 userpg->time_offset = offset - now;
2315
2316 /*
2317 * cap_user_time_zero doesn't make sense when we're using a different
2318 * time base for the records.
2319 */
2320 if (!event->attr.use_clockid) {
2321 userpg->cap_user_time_zero = 1;
2322 userpg->time_zero = offset;
2323 }
2324
2325 cyc2ns_read_end();
2326 }
2327
2328 void
2329 perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2330 {
2331 struct unwind_state state;
2332 unsigned long addr;
2333
2334 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2335 /* TODO: We don't support guest os callchain now */
2336 return;
2337 }
2338
2339 if (perf_callchain_store(entry, regs->ip))
2340 return;
2341
2342 for (unwind_start(&state, current, regs, NULL); !unwind_done(&state);
2343 unwind_next_frame(&state)) {
2344 addr = unwind_get_return_address(&state);
2345 if (!addr || perf_callchain_store(entry, addr))
2346 return;
2347 }
2348 }
2349
2350 static inline int
2351 valid_user_frame(const void __user *fp, unsigned long size)
2352 {
2353 return (__range_not_ok(fp, size, TASK_SIZE) == 0);
2354 }
2355
2356 static unsigned long get_segment_base(unsigned int segment)
2357 {
2358 struct desc_struct *desc;
2359 unsigned int idx = segment >> 3;
2360
2361 if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2362 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2363 struct ldt_struct *ldt;
2364
2365 /* IRQs are off, so this synchronizes with smp_store_release */
2366 ldt = READ_ONCE(current->active_mm->context.ldt);
2367 if (!ldt || idx >= ldt->nr_entries)
2368 return 0;
2369
2370 desc = &ldt->entries[idx];
2371 #else
2372 return 0;
2373 #endif
2374 } else {
2375 if (idx >= GDT_ENTRIES)
2376 return 0;
2377
2378 desc = raw_cpu_ptr(gdt_page.gdt) + idx;
2379 }
2380
2381 return get_desc_base(desc);
2382 }
2383
2384 #ifdef CONFIG_IA32_EMULATION
2385
2386 #include <asm/compat.h>
2387
2388 static inline int
2389 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2390 {
2391 /* 32-bit process in 64-bit kernel. */
2392 unsigned long ss_base, cs_base;
2393 struct stack_frame_ia32 frame;
2394 const void __user *fp;
2395
2396 if (!test_thread_flag(TIF_IA32))
2397 return 0;
2398
2399 cs_base = get_segment_base(regs->cs);
2400 ss_base = get_segment_base(regs->ss);
2401
2402 fp = compat_ptr(ss_base + regs->bp);
2403 pagefault_disable();
2404 while (entry->nr < entry->max_stack) {
2405 unsigned long bytes;
2406 frame.next_frame = 0;
2407 frame.return_address = 0;
2408
2409 if (!valid_user_frame(fp, sizeof(frame)))
2410 break;
2411
2412 bytes = __copy_from_user_nmi(&frame.next_frame, fp, 4);
2413 if (bytes != 0)
2414 break;
2415 bytes = __copy_from_user_nmi(&frame.return_address, fp+4, 4);
2416 if (bytes != 0)
2417 break;
2418
2419 perf_callchain_store(entry, cs_base + frame.return_address);
2420 fp = compat_ptr(ss_base + frame.next_frame);
2421 }
2422 pagefault_enable();
2423 return 1;
2424 }
2425 #else
2426 static inline int
2427 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2428 {
2429 return 0;
2430 }
2431 #endif
2432
2433 void
2434 perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2435 {
2436 struct stack_frame frame;
2437 const unsigned long __user *fp;
2438
2439 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2440 /* TODO: We don't support guest os callchain now */
2441 return;
2442 }
2443
2444 /*
2445 * We don't know what to do with VM86 stacks.. ignore them for now.
2446 */
2447 if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2448 return;
2449
2450 fp = (unsigned long __user *)regs->bp;
2451
2452 perf_callchain_store(entry, regs->ip);
2453
2454 if (!nmi_uaccess_okay())
2455 return;
2456
2457 if (perf_callchain_user32(regs, entry))
2458 return;
2459
2460 pagefault_disable();
2461 while (entry->nr < entry->max_stack) {
2462 unsigned long bytes;
2463
2464 frame.next_frame = NULL;
2465 frame.return_address = 0;
2466
2467 if (!valid_user_frame(fp, sizeof(frame)))
2468 break;
2469
2470 bytes = __copy_from_user_nmi(&frame.next_frame, fp, sizeof(*fp));
2471 if (bytes != 0)
2472 break;
2473 bytes = __copy_from_user_nmi(&frame.return_address, fp + 1, sizeof(*fp));
2474 if (bytes != 0)
2475 break;
2476
2477 perf_callchain_store(entry, frame.return_address);
2478 fp = (void __user *)frame.next_frame;
2479 }
2480 pagefault_enable();
2481 }
2482
2483 /*
2484 * Deal with code segment offsets for the various execution modes:
2485 *
2486 * VM86 - the good olde 16 bit days, where the linear address is
2487 * 20 bits and we use regs->ip + 0x10 * regs->cs.
2488 *
2489 * IA32 - Where we need to look at GDT/LDT segment descriptor tables
2490 * to figure out what the 32bit base address is.
2491 *
2492 * X32 - has TIF_X32 set, but is running in x86_64
2493 *
2494 * X86_64 - CS,DS,SS,ES are all zero based.
2495 */
2496 static unsigned long code_segment_base(struct pt_regs *regs)
2497 {
2498 /*
2499 * For IA32 we look at the GDT/LDT segment base to convert the
2500 * effective IP to a linear address.
2501 */
2502
2503 #ifdef CONFIG_X86_32
2504 /*
2505 * If we are in VM86 mode, add the segment offset to convert to a
2506 * linear address.
2507 */
2508 if (regs->flags & X86_VM_MASK)
2509 return 0x10 * regs->cs;
2510
2511 if (user_mode(regs) && regs->cs != __USER_CS)
2512 return get_segment_base(regs->cs);
2513 #else
2514 if (user_mode(regs) && !user_64bit_mode(regs) &&
2515 regs->cs != __USER32_CS)
2516 return get_segment_base(regs->cs);
2517 #endif
2518 return 0;
2519 }
2520
2521 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2522 {
2523 if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2524 return perf_guest_cbs->get_guest_ip();
2525
2526 return regs->ip + code_segment_base(regs);
2527 }
2528
2529 unsigned long perf_misc_flags(struct pt_regs *regs)
2530 {
2531 int misc = 0;
2532
2533 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2534 if (perf_guest_cbs->is_user_mode())
2535 misc |= PERF_RECORD_MISC_GUEST_USER;
2536 else
2537 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2538 } else {
2539 if (user_mode(regs))
2540 misc |= PERF_RECORD_MISC_USER;
2541 else
2542 misc |= PERF_RECORD_MISC_KERNEL;
2543 }
2544
2545 if (regs->flags & PERF_EFLAGS_EXACT)
2546 misc |= PERF_RECORD_MISC_EXACT_IP;
2547
2548 return misc;
2549 }
2550
2551 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2552 {
2553 cap->version = x86_pmu.version;
2554 cap->num_counters_gp = x86_pmu.num_counters;
2555 cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2556 cap->bit_width_gp = x86_pmu.cntval_bits;
2557 cap->bit_width_fixed = x86_pmu.cntval_bits;
2558 cap->events_mask = (unsigned int)x86_pmu.events_maskl;
2559 cap->events_mask_len = x86_pmu.events_mask_len;
2560 }
2561 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);
Linux with added FPC-III support