1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/export.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/ctype.h>
9 #include <linux/delay.h>
10 #include <linux/sched/mm.h>
11 #include <linux/sched/clock.h>
12 #include <linux/sched/task.h>
13 #include <linux/init.h>
14 #include <linux/kprobes.h>
15 #include <linux/kgdb.h>
16 #include <linux/smp.h>
18 #include <linux/syscore_ops.h>
20 #include <asm/stackprotector.h>
21 #include <asm/perf_event.h>
22 #include <asm/mmu_context.h>
23 #include <asm/archrandom.h>
24 #include <asm/hypervisor.h>
25 #include <asm/processor.h>
26 #include <asm/tlbflush.h>
27 #include <asm/debugreg.h>
28 #include <asm/sections.h>
29 #include <asm/vsyscall.h>
30 #include <linux/topology.h>
31 #include <linux/cpumask.h>
32 #include <asm/pgtable.h>
33 #include <linux/atomic.h>
34 #include <asm/proto.h>
35 #include <asm/setup.h>
38 #include <asm/fpu/internal.h>
40 #include <asm/hwcap2.h>
41 #include <linux/numa.h>
48 #include <asm/microcode.h>
49 #include <asm/microcode_intel.h>
50 #include <asm/intel-family.h>
51 #include <asm/cpu_device_id.h>
53 #ifdef CONFIG_X86_LOCAL_APIC
54 #include <asm/uv/uv.h>
59 u32 elf_hwcap2 __read_mostly
;
61 /* all of these masks are initialized in setup_cpu_local_masks() */
62 cpumask_var_t cpu_initialized_mask
;
63 cpumask_var_t cpu_callout_mask
;
64 cpumask_var_t cpu_callin_mask
;
66 /* representing cpus for which sibling maps can be computed */
67 cpumask_var_t cpu_sibling_setup_mask
;
69 /* Number of siblings per CPU package */
70 int smp_num_siblings
= 1;
71 EXPORT_SYMBOL(smp_num_siblings
);
73 /* Last level cache ID of each logical CPU */
74 DEFINE_PER_CPU_READ_MOSTLY(u16
, cpu_llc_id
) = BAD_APICID
;
76 /* correctly size the local cpu masks */
77 void __init
setup_cpu_local_masks(void)
79 alloc_bootmem_cpumask_var(&cpu_initialized_mask
);
80 alloc_bootmem_cpumask_var(&cpu_callin_mask
);
81 alloc_bootmem_cpumask_var(&cpu_callout_mask
);
82 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask
);
85 static void default_init(struct cpuinfo_x86
*c
)
88 cpu_detect_cache_sizes(c
);
90 /* Not much we can do here... */
91 /* Check if at least it has cpuid */
92 if (c
->cpuid_level
== -1) {
93 /* No cpuid. It must be an ancient CPU */
95 strcpy(c
->x86_model_id
, "486");
97 strcpy(c
->x86_model_id
, "386");
102 static const struct cpu_dev default_cpu
= {
103 .c_init
= default_init
,
104 .c_vendor
= "Unknown",
105 .c_x86_vendor
= X86_VENDOR_UNKNOWN
,
108 static const struct cpu_dev
*this_cpu
= &default_cpu
;
110 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page
, gdt_page
) = { .gdt
= {
113 * We need valid kernel segments for data and code in long mode too
114 * IRET will check the segment types kkeil 2000/10/28
115 * Also sysret mandates a special GDT layout
117 * TLS descriptors are currently at a different place compared to i386.
118 * Hopefully nobody expects them at a fixed place (Wine?)
120 [GDT_ENTRY_KERNEL32_CS
] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
121 [GDT_ENTRY_KERNEL_CS
] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
122 [GDT_ENTRY_KERNEL_DS
] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
123 [GDT_ENTRY_DEFAULT_USER32_CS
] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
124 [GDT_ENTRY_DEFAULT_USER_DS
] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
125 [GDT_ENTRY_DEFAULT_USER_CS
] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
127 [GDT_ENTRY_KERNEL_CS
] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
128 [GDT_ENTRY_KERNEL_DS
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
129 [GDT_ENTRY_DEFAULT_USER_CS
] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
130 [GDT_ENTRY_DEFAULT_USER_DS
] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
132 * Segments used for calling PnP BIOS have byte granularity.
133 * They code segments and data segments have fixed 64k limits,
134 * the transfer segment sizes are set at run time.
137 [GDT_ENTRY_PNPBIOS_CS32
] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
139 [GDT_ENTRY_PNPBIOS_CS16
] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
141 [GDT_ENTRY_PNPBIOS_DS
] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
143 [GDT_ENTRY_PNPBIOS_TS1
] = GDT_ENTRY_INIT(0x0092, 0, 0),
145 [GDT_ENTRY_PNPBIOS_TS2
] = GDT_ENTRY_INIT(0x0092, 0, 0),
147 * The APM segments have byte granularity and their bases
148 * are set at run time. All have 64k limits.
151 [GDT_ENTRY_APMBIOS_BASE
] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
153 [GDT_ENTRY_APMBIOS_BASE
+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
155 [GDT_ENTRY_APMBIOS_BASE
+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
157 [GDT_ENTRY_ESPFIX_SS
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
158 [GDT_ENTRY_PERCPU
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
159 GDT_STACK_CANARY_INIT
162 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page
);
164 static int __init
x86_mpx_setup(char *s
)
166 /* require an exact match without trailing characters */
170 /* do not emit a message if the feature is not present */
171 if (!boot_cpu_has(X86_FEATURE_MPX
))
174 setup_clear_cpu_cap(X86_FEATURE_MPX
);
175 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
178 __setup("nompx", x86_mpx_setup
);
181 static int __init
x86_nopcid_setup(char *s
)
183 /* nopcid doesn't accept parameters */
187 /* do not emit a message if the feature is not present */
188 if (!boot_cpu_has(X86_FEATURE_PCID
))
191 setup_clear_cpu_cap(X86_FEATURE_PCID
);
192 pr_info("nopcid: PCID feature disabled\n");
195 early_param("nopcid", x86_nopcid_setup
);
198 static int __init
x86_noinvpcid_setup(char *s
)
200 /* noinvpcid doesn't accept parameters */
204 /* do not emit a message if the feature is not present */
205 if (!boot_cpu_has(X86_FEATURE_INVPCID
))
208 setup_clear_cpu_cap(X86_FEATURE_INVPCID
);
209 pr_info("noinvpcid: INVPCID feature disabled\n");
212 early_param("noinvpcid", x86_noinvpcid_setup
);
215 static int cachesize_override
= -1;
216 static int disable_x86_serial_nr
= 1;
218 static int __init
cachesize_setup(char *str
)
220 get_option(&str
, &cachesize_override
);
223 __setup("cachesize=", cachesize_setup
);
225 static int __init
x86_sep_setup(char *s
)
227 setup_clear_cpu_cap(X86_FEATURE_SEP
);
230 __setup("nosep", x86_sep_setup
);
232 /* Standard macro to see if a specific flag is changeable */
233 static inline int flag_is_changeable_p(u32 flag
)
238 * Cyrix and IDT cpus allow disabling of CPUID
239 * so the code below may return different results
240 * when it is executed before and after enabling
241 * the CPUID. Add "volatile" to not allow gcc to
242 * optimize the subsequent calls to this function.
244 asm volatile ("pushfl \n\t"
255 : "=&r" (f1
), "=&r" (f2
)
258 return ((f1
^f2
) & flag
) != 0;
261 /* Probe for the CPUID instruction */
262 int have_cpuid_p(void)
264 return flag_is_changeable_p(X86_EFLAGS_ID
);
267 static void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
269 unsigned long lo
, hi
;
271 if (!cpu_has(c
, X86_FEATURE_PN
) || !disable_x86_serial_nr
)
274 /* Disable processor serial number: */
276 rdmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
278 wrmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
280 pr_notice("CPU serial number disabled.\n");
281 clear_cpu_cap(c
, X86_FEATURE_PN
);
283 /* Disabling the serial number may affect the cpuid level */
284 c
->cpuid_level
= cpuid_eax(0);
287 static int __init
x86_serial_nr_setup(char *s
)
289 disable_x86_serial_nr
= 0;
292 __setup("serialnumber", x86_serial_nr_setup
);
294 static inline int flag_is_changeable_p(u32 flag
)
298 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
303 static __init
int setup_disable_smep(char *arg
)
305 setup_clear_cpu_cap(X86_FEATURE_SMEP
);
306 /* Check for things that depend on SMEP being enabled: */
307 check_mpx_erratum(&boot_cpu_data
);
310 __setup("nosmep", setup_disable_smep
);
312 static __always_inline
void setup_smep(struct cpuinfo_x86
*c
)
314 if (cpu_has(c
, X86_FEATURE_SMEP
))
315 cr4_set_bits(X86_CR4_SMEP
);
318 static __init
int setup_disable_smap(char *arg
)
320 setup_clear_cpu_cap(X86_FEATURE_SMAP
);
323 __setup("nosmap", setup_disable_smap
);
325 static __always_inline
void setup_smap(struct cpuinfo_x86
*c
)
327 unsigned long eflags
= native_save_fl();
329 /* This should have been cleared long ago */
330 BUG_ON(eflags
& X86_EFLAGS_AC
);
332 if (cpu_has(c
, X86_FEATURE_SMAP
)) {
333 #ifdef CONFIG_X86_SMAP
334 cr4_set_bits(X86_CR4_SMAP
);
336 cr4_clear_bits(X86_CR4_SMAP
);
342 * Protection Keys are not available in 32-bit mode.
344 static bool pku_disabled
;
346 static __always_inline
void setup_pku(struct cpuinfo_x86
*c
)
348 /* check the boot processor, plus compile options for PKU: */
349 if (!cpu_feature_enabled(X86_FEATURE_PKU
))
351 /* checks the actual processor's cpuid bits: */
352 if (!cpu_has(c
, X86_FEATURE_PKU
))
357 cr4_set_bits(X86_CR4_PKE
);
359 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
360 * cpuid bit to be set. We need to ensure that we
361 * update that bit in this CPU's "cpu_info".
363 set_cpu_cap(c
, X86_FEATURE_OSPKE
);
366 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
367 static __init
int setup_disable_pku(char *arg
)
370 * Do not clear the X86_FEATURE_PKU bit. All of the
371 * runtime checks are against OSPKE so clearing the
374 * This way, we will see "pku" in cpuinfo, but not
375 * "ospke", which is exactly what we want. It shows
376 * that the CPU has PKU, but the OS has not enabled it.
377 * This happens to be exactly how a system would look
378 * if we disabled the config option.
380 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
384 __setup("nopku", setup_disable_pku
);
385 #endif /* CONFIG_X86_64 */
388 * Some CPU features depend on higher CPUID levels, which may not always
389 * be available due to CPUID level capping or broken virtualization
390 * software. Add those features to this table to auto-disable them.
392 struct cpuid_dependent_feature
{
397 static const struct cpuid_dependent_feature
398 cpuid_dependent_features
[] = {
399 { X86_FEATURE_MWAIT
, 0x00000005 },
400 { X86_FEATURE_DCA
, 0x00000009 },
401 { X86_FEATURE_XSAVE
, 0x0000000d },
405 static void filter_cpuid_features(struct cpuinfo_x86
*c
, bool warn
)
407 const struct cpuid_dependent_feature
*df
;
409 for (df
= cpuid_dependent_features
; df
->feature
; df
++) {
411 if (!cpu_has(c
, df
->feature
))
414 * Note: cpuid_level is set to -1 if unavailable, but
415 * extended_extended_level is set to 0 if unavailable
416 * and the legitimate extended levels are all negative
417 * when signed; hence the weird messing around with
420 if (!((s32
)df
->level
< 0 ?
421 (u32
)df
->level
> (u32
)c
->extended_cpuid_level
:
422 (s32
)df
->level
> (s32
)c
->cpuid_level
))
425 clear_cpu_cap(c
, df
->feature
);
429 pr_warn("CPU: CPU feature " X86_CAP_FMT
" disabled, no CPUID level 0x%x\n",
430 x86_cap_flag(df
->feature
), df
->level
);
435 * Naming convention should be: <Name> [(<Codename>)]
436 * This table only is used unless init_<vendor>() below doesn't set it;
437 * in particular, if CPUID levels 0x80000002..4 are supported, this
441 /* Look up CPU names by table lookup. */
442 static const char *table_lookup_model(struct cpuinfo_x86
*c
)
445 const struct legacy_cpu_model_info
*info
;
447 if (c
->x86_model
>= 16)
448 return NULL
; /* Range check */
453 info
= this_cpu
->legacy_models
;
455 while (info
->family
) {
456 if (info
->family
== c
->x86
)
457 return info
->model_names
[c
->x86_model
];
461 return NULL
; /* Not found */
464 __u32 cpu_caps_cleared
[NCAPINTS
+ NBUGINTS
];
465 __u32 cpu_caps_set
[NCAPINTS
+ NBUGINTS
];
467 void load_percpu_segment(int cpu
)
470 loadsegment(fs
, __KERNEL_PERCPU
);
472 __loadsegment_simple(gs
, 0);
473 wrmsrl(MSR_GS_BASE
, (unsigned long)per_cpu(irq_stack_union
.gs_base
, cpu
));
475 load_stack_canary_segment();
479 /* The 32-bit entry code needs to find cpu_entry_area. */
480 DEFINE_PER_CPU(struct cpu_entry_area
*, cpu_entry_area
);
485 * Special IST stacks which the CPU switches to when it calls
486 * an IST-marked descriptor entry. Up to 7 stacks (hardware
487 * limit), all of them are 4K, except the debug stack which
490 static const unsigned int exception_stack_sizes
[N_EXCEPTION_STACKS
] = {
491 [0 ... N_EXCEPTION_STACKS
- 1] = EXCEPTION_STKSZ
,
492 [DEBUG_STACK
- 1] = DEBUG_STKSZ
496 /* Load the original GDT from the per-cpu structure */
497 void load_direct_gdt(int cpu
)
499 struct desc_ptr gdt_descr
;
501 gdt_descr
.address
= (long)get_cpu_gdt_rw(cpu
);
502 gdt_descr
.size
= GDT_SIZE
- 1;
503 load_gdt(&gdt_descr
);
505 EXPORT_SYMBOL_GPL(load_direct_gdt
);
507 /* Load a fixmap remapping of the per-cpu GDT */
508 void load_fixmap_gdt(int cpu
)
510 struct desc_ptr gdt_descr
;
512 gdt_descr
.address
= (long)get_cpu_gdt_ro(cpu
);
513 gdt_descr
.size
= GDT_SIZE
- 1;
514 load_gdt(&gdt_descr
);
516 EXPORT_SYMBOL_GPL(load_fixmap_gdt
);
519 * Current gdt points %fs at the "master" per-cpu area: after this,
520 * it's on the real one.
522 void switch_to_new_gdt(int cpu
)
524 /* Load the original GDT */
525 load_direct_gdt(cpu
);
526 /* Reload the per-cpu base */
527 load_percpu_segment(cpu
);
530 static const struct cpu_dev
*cpu_devs
[X86_VENDOR_NUM
] = {};
532 static void get_model_name(struct cpuinfo_x86
*c
)
537 if (c
->extended_cpuid_level
< 0x80000004)
540 v
= (unsigned int *)c
->x86_model_id
;
541 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
542 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
543 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
544 c
->x86_model_id
[48] = 0;
546 /* Trim whitespace */
547 p
= q
= s
= &c
->x86_model_id
[0];
553 /* Note the last non-whitespace index */
563 void cpu_detect_cache_sizes(struct cpuinfo_x86
*c
)
565 unsigned int n
, dummy
, ebx
, ecx
, edx
, l2size
;
567 n
= c
->extended_cpuid_level
;
569 if (n
>= 0x80000005) {
570 cpuid(0x80000005, &dummy
, &ebx
, &ecx
, &edx
);
571 c
->x86_cache_size
= (ecx
>>24) + (edx
>>24);
573 /* On K8 L1 TLB is inclusive, so don't count it */
578 if (n
< 0x80000006) /* Some chips just has a large L1. */
581 cpuid(0x80000006, &dummy
, &ebx
, &ecx
, &edx
);
585 c
->x86_tlbsize
+= ((ebx
>> 16) & 0xfff) + (ebx
& 0xfff);
587 /* do processor-specific cache resizing */
588 if (this_cpu
->legacy_cache_size
)
589 l2size
= this_cpu
->legacy_cache_size(c
, l2size
);
591 /* Allow user to override all this if necessary. */
592 if (cachesize_override
!= -1)
593 l2size
= cachesize_override
;
596 return; /* Again, no L2 cache is possible */
599 c
->x86_cache_size
= l2size
;
602 u16 __read_mostly tlb_lli_4k
[NR_INFO
];
603 u16 __read_mostly tlb_lli_2m
[NR_INFO
];
604 u16 __read_mostly tlb_lli_4m
[NR_INFO
];
605 u16 __read_mostly tlb_lld_4k
[NR_INFO
];
606 u16 __read_mostly tlb_lld_2m
[NR_INFO
];
607 u16 __read_mostly tlb_lld_4m
[NR_INFO
];
608 u16 __read_mostly tlb_lld_1g
[NR_INFO
];
610 static void cpu_detect_tlb(struct cpuinfo_x86
*c
)
612 if (this_cpu
->c_detect_tlb
)
613 this_cpu
->c_detect_tlb(c
);
615 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
616 tlb_lli_4k
[ENTRIES
], tlb_lli_2m
[ENTRIES
],
617 tlb_lli_4m
[ENTRIES
]);
619 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
620 tlb_lld_4k
[ENTRIES
], tlb_lld_2m
[ENTRIES
],
621 tlb_lld_4m
[ENTRIES
], tlb_lld_1g
[ENTRIES
]);
624 int detect_ht_early(struct cpuinfo_x86
*c
)
627 u32 eax
, ebx
, ecx
, edx
;
629 if (!cpu_has(c
, X86_FEATURE_HT
))
632 if (cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
635 if (cpu_has(c
, X86_FEATURE_XTOPOLOGY
))
638 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
640 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
641 if (smp_num_siblings
== 1)
642 pr_info_once("CPU0: Hyper-Threading is disabled\n");
647 void detect_ht(struct cpuinfo_x86
*c
)
650 int index_msb
, core_bits
;
652 if (detect_ht_early(c
) < 0)
655 index_msb
= get_count_order(smp_num_siblings
);
656 c
->phys_proc_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
);
658 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
660 index_msb
= get_count_order(smp_num_siblings
);
662 core_bits
= get_count_order(c
->x86_max_cores
);
664 c
->cpu_core_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
) &
665 ((1 << core_bits
) - 1);
669 static void get_cpu_vendor(struct cpuinfo_x86
*c
)
671 char *v
= c
->x86_vendor_id
;
674 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
678 if (!strcmp(v
, cpu_devs
[i
]->c_ident
[0]) ||
679 (cpu_devs
[i
]->c_ident
[1] &&
680 !strcmp(v
, cpu_devs
[i
]->c_ident
[1]))) {
682 this_cpu
= cpu_devs
[i
];
683 c
->x86_vendor
= this_cpu
->c_x86_vendor
;
688 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
689 "CPU: Your system may be unstable.\n", v
);
691 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
692 this_cpu
= &default_cpu
;
695 void cpu_detect(struct cpuinfo_x86
*c
)
697 /* Get vendor name */
698 cpuid(0x00000000, (unsigned int *)&c
->cpuid_level
,
699 (unsigned int *)&c
->x86_vendor_id
[0],
700 (unsigned int *)&c
->x86_vendor_id
[8],
701 (unsigned int *)&c
->x86_vendor_id
[4]);
704 /* Intel-defined flags: level 0x00000001 */
705 if (c
->cpuid_level
>= 0x00000001) {
706 u32 junk
, tfms
, cap0
, misc
;
708 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
709 c
->x86
= x86_family(tfms
);
710 c
->x86_model
= x86_model(tfms
);
711 c
->x86_stepping
= x86_stepping(tfms
);
713 if (cap0
& (1<<19)) {
714 c
->x86_clflush_size
= ((misc
>> 8) & 0xff) * 8;
715 c
->x86_cache_alignment
= c
->x86_clflush_size
;
720 static void apply_forced_caps(struct cpuinfo_x86
*c
)
724 for (i
= 0; i
< NCAPINTS
+ NBUGINTS
; i
++) {
725 c
->x86_capability
[i
] &= ~cpu_caps_cleared
[i
];
726 c
->x86_capability
[i
] |= cpu_caps_set
[i
];
730 static void init_speculation_control(struct cpuinfo_x86
*c
)
733 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
734 * and they also have a different bit for STIBP support. Also,
735 * a hypervisor might have set the individual AMD bits even on
736 * Intel CPUs, for finer-grained selection of what's available.
738 if (cpu_has(c
, X86_FEATURE_SPEC_CTRL
)) {
739 set_cpu_cap(c
, X86_FEATURE_IBRS
);
740 set_cpu_cap(c
, X86_FEATURE_IBPB
);
741 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
744 if (cpu_has(c
, X86_FEATURE_INTEL_STIBP
))
745 set_cpu_cap(c
, X86_FEATURE_STIBP
);
747 if (cpu_has(c
, X86_FEATURE_SPEC_CTRL_SSBD
) ||
748 cpu_has(c
, X86_FEATURE_VIRT_SSBD
))
749 set_cpu_cap(c
, X86_FEATURE_SSBD
);
751 if (cpu_has(c
, X86_FEATURE_AMD_IBRS
)) {
752 set_cpu_cap(c
, X86_FEATURE_IBRS
);
753 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
756 if (cpu_has(c
, X86_FEATURE_AMD_IBPB
))
757 set_cpu_cap(c
, X86_FEATURE_IBPB
);
759 if (cpu_has(c
, X86_FEATURE_AMD_STIBP
)) {
760 set_cpu_cap(c
, X86_FEATURE_STIBP
);
761 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
764 if (cpu_has(c
, X86_FEATURE_AMD_SSBD
)) {
765 set_cpu_cap(c
, X86_FEATURE_SSBD
);
766 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
767 clear_cpu_cap(c
, X86_FEATURE_VIRT_SSBD
);
771 static void init_cqm(struct cpuinfo_x86
*c
)
773 if (!cpu_has(c
, X86_FEATURE_CQM_LLC
)) {
774 c
->x86_cache_max_rmid
= -1;
775 c
->x86_cache_occ_scale
= -1;
779 /* will be overridden if occupancy monitoring exists */
780 c
->x86_cache_max_rmid
= cpuid_ebx(0xf);
782 if (cpu_has(c
, X86_FEATURE_CQM_OCCUP_LLC
) ||
783 cpu_has(c
, X86_FEATURE_CQM_MBM_TOTAL
) ||
784 cpu_has(c
, X86_FEATURE_CQM_MBM_LOCAL
)) {
785 u32 eax
, ebx
, ecx
, edx
;
787 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
788 cpuid_count(0xf, 1, &eax
, &ebx
, &ecx
, &edx
);
790 c
->x86_cache_max_rmid
= ecx
;
791 c
->x86_cache_occ_scale
= ebx
;
795 void get_cpu_cap(struct cpuinfo_x86
*c
)
797 u32 eax
, ebx
, ecx
, edx
;
799 /* Intel-defined flags: level 0x00000001 */
800 if (c
->cpuid_level
>= 0x00000001) {
801 cpuid(0x00000001, &eax
, &ebx
, &ecx
, &edx
);
803 c
->x86_capability
[CPUID_1_ECX
] = ecx
;
804 c
->x86_capability
[CPUID_1_EDX
] = edx
;
807 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
808 if (c
->cpuid_level
>= 0x00000006)
809 c
->x86_capability
[CPUID_6_EAX
] = cpuid_eax(0x00000006);
811 /* Additional Intel-defined flags: level 0x00000007 */
812 if (c
->cpuid_level
>= 0x00000007) {
813 cpuid_count(0x00000007, 0, &eax
, &ebx
, &ecx
, &edx
);
814 c
->x86_capability
[CPUID_7_0_EBX
] = ebx
;
815 c
->x86_capability
[CPUID_7_ECX
] = ecx
;
816 c
->x86_capability
[CPUID_7_EDX
] = edx
;
819 /* Extended state features: level 0x0000000d */
820 if (c
->cpuid_level
>= 0x0000000d) {
821 cpuid_count(0x0000000d, 1, &eax
, &ebx
, &ecx
, &edx
);
823 c
->x86_capability
[CPUID_D_1_EAX
] = eax
;
826 /* AMD-defined flags: level 0x80000001 */
827 eax
= cpuid_eax(0x80000000);
828 c
->extended_cpuid_level
= eax
;
830 if ((eax
& 0xffff0000) == 0x80000000) {
831 if (eax
>= 0x80000001) {
832 cpuid(0x80000001, &eax
, &ebx
, &ecx
, &edx
);
834 c
->x86_capability
[CPUID_8000_0001_ECX
] = ecx
;
835 c
->x86_capability
[CPUID_8000_0001_EDX
] = edx
;
839 if (c
->extended_cpuid_level
>= 0x80000007) {
840 cpuid(0x80000007, &eax
, &ebx
, &ecx
, &edx
);
842 c
->x86_capability
[CPUID_8000_0007_EBX
] = ebx
;
846 if (c
->extended_cpuid_level
>= 0x80000008) {
847 cpuid(0x80000008, &eax
, &ebx
, &ecx
, &edx
);
849 c
->x86_virt_bits
= (eax
>> 8) & 0xff;
850 c
->x86_phys_bits
= eax
& 0xff;
851 c
->x86_capability
[CPUID_8000_0008_EBX
] = ebx
;
854 else if (cpu_has(c
, X86_FEATURE_PAE
) || cpu_has(c
, X86_FEATURE_PSE36
))
855 c
->x86_phys_bits
= 36;
857 c
->x86_cache_bits
= c
->x86_phys_bits
;
859 if (c
->extended_cpuid_level
>= 0x8000000a)
860 c
->x86_capability
[CPUID_8000_000A_EDX
] = cpuid_edx(0x8000000a);
862 init_scattered_cpuid_features(c
);
863 init_speculation_control(c
);
867 * Clear/Set all flags overridden by options, after probe.
868 * This needs to happen each time we re-probe, which may happen
869 * several times during CPU initialization.
871 apply_forced_caps(c
);
874 static void identify_cpu_without_cpuid(struct cpuinfo_x86
*c
)
880 * First of all, decide if this is a 486 or higher
881 * It's a 486 if we can modify the AC flag
883 if (flag_is_changeable_p(X86_EFLAGS_AC
))
888 for (i
= 0; i
< X86_VENDOR_NUM
; i
++)
889 if (cpu_devs
[i
] && cpu_devs
[i
]->c_identify
) {
890 c
->x86_vendor_id
[0] = 0;
891 cpu_devs
[i
]->c_identify(c
);
892 if (c
->x86_vendor_id
[0]) {
900 #define NO_SPECULATION BIT(0)
901 #define NO_MELTDOWN BIT(1)
902 #define NO_SSB BIT(2)
903 #define NO_L1TF BIT(3)
904 #define NO_MDS BIT(4)
905 #define MSBDS_ONLY BIT(5)
906 #define NO_SWAPGS BIT(6)
907 #define NO_ITLB_MULTIHIT BIT(7)
909 #define VULNWL(_vendor, _family, _model, _whitelist) \
910 { X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist }
912 #define VULNWL_INTEL(model, whitelist) \
913 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist)
915 #define VULNWL_AMD(family, whitelist) \
916 VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
918 static const __initconst
struct x86_cpu_id cpu_vuln_whitelist
[] = {
919 VULNWL(ANY
, 4, X86_MODEL_ANY
, NO_SPECULATION
),
920 VULNWL(CENTAUR
, 5, X86_MODEL_ANY
, NO_SPECULATION
),
921 VULNWL(INTEL
, 5, X86_MODEL_ANY
, NO_SPECULATION
),
922 VULNWL(NSC
, 5, X86_MODEL_ANY
, NO_SPECULATION
),
925 VULNWL_INTEL(ATOM_SALTWELL
, NO_SPECULATION
| NO_ITLB_MULTIHIT
),
926 VULNWL_INTEL(ATOM_SALTWELL_TABLET
, NO_SPECULATION
| NO_ITLB_MULTIHIT
),
927 VULNWL_INTEL(ATOM_SALTWELL_MID
, NO_SPECULATION
| NO_ITLB_MULTIHIT
),
928 VULNWL_INTEL(ATOM_BONNELL
, NO_SPECULATION
| NO_ITLB_MULTIHIT
),
929 VULNWL_INTEL(ATOM_BONNELL_MID
, NO_SPECULATION
| NO_ITLB_MULTIHIT
),
931 VULNWL_INTEL(ATOM_SILVERMONT
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
932 VULNWL_INTEL(ATOM_SILVERMONT_X
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
933 VULNWL_INTEL(ATOM_SILVERMONT_MID
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
934 VULNWL_INTEL(ATOM_AIRMONT
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
935 VULNWL_INTEL(XEON_PHI_KNL
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
936 VULNWL_INTEL(XEON_PHI_KNM
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
938 VULNWL_INTEL(CORE_YONAH
, NO_SSB
),
940 VULNWL_INTEL(ATOM_AIRMONT_MID
, NO_L1TF
| MSBDS_ONLY
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
942 VULNWL_INTEL(ATOM_GOLDMONT
, NO_MDS
| NO_L1TF
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
943 VULNWL_INTEL(ATOM_GOLDMONT_X
, NO_MDS
| NO_L1TF
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
944 VULNWL_INTEL(ATOM_GOLDMONT_PLUS
, NO_MDS
| NO_L1TF
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
947 * Technically, swapgs isn't serializing on AMD (despite it previously
948 * being documented as such in the APM). But according to AMD, %gs is
949 * updated non-speculatively, and the issuing of %gs-relative memory
950 * operands will be blocked until the %gs update completes, which is
951 * good enough for our purposes.
954 VULNWL_INTEL(ATOM_TREMONT_X
, NO_ITLB_MULTIHIT
),
956 /* AMD Family 0xf - 0x12 */
957 VULNWL_AMD(0x0f, NO_MELTDOWN
| NO_SSB
| NO_L1TF
| NO_MDS
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
958 VULNWL_AMD(0x10, NO_MELTDOWN
| NO_SSB
| NO_L1TF
| NO_MDS
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
959 VULNWL_AMD(0x11, NO_MELTDOWN
| NO_SSB
| NO_L1TF
| NO_MDS
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
960 VULNWL_AMD(0x12, NO_MELTDOWN
| NO_SSB
| NO_L1TF
| NO_MDS
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
962 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
963 VULNWL_AMD(X86_FAMILY_ANY
, NO_MELTDOWN
| NO_L1TF
| NO_MDS
| NO_SWAPGS
| NO_ITLB_MULTIHIT
),
967 #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \
968 X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \
969 INTEL_FAM6_##model, steppings, \
970 X86_FEATURE_ANY, issues)
974 static const struct x86_cpu_id cpu_vuln_blacklist
[] __initconst
= {
975 VULNBL_INTEL_STEPPINGS(IVYBRIDGE
, X86_STEPPING_ANY
, SRBDS
),
976 VULNBL_INTEL_STEPPINGS(HASWELL_CORE
, X86_STEPPING_ANY
, SRBDS
),
977 VULNBL_INTEL_STEPPINGS(HASWELL_ULT
, X86_STEPPING_ANY
, SRBDS
),
978 VULNBL_INTEL_STEPPINGS(HASWELL_GT3E
, X86_STEPPING_ANY
, SRBDS
),
979 VULNBL_INTEL_STEPPINGS(BROADWELL_GT3E
, X86_STEPPING_ANY
, SRBDS
),
980 VULNBL_INTEL_STEPPINGS(BROADWELL_CORE
, X86_STEPPING_ANY
, SRBDS
),
981 VULNBL_INTEL_STEPPINGS(SKYLAKE_MOBILE
, X86_STEPPING_ANY
, SRBDS
),
982 VULNBL_INTEL_STEPPINGS(SKYLAKE_DESKTOP
, X86_STEPPING_ANY
, SRBDS
),
983 VULNBL_INTEL_STEPPINGS(KABYLAKE_MOBILE
, X86_STEPPINGS(0x0, 0xC), SRBDS
),
984 VULNBL_INTEL_STEPPINGS(KABYLAKE_DESKTOP
,X86_STEPPINGS(0x0, 0xD), SRBDS
),
988 static bool __init
cpu_matches(const struct x86_cpu_id
*table
, unsigned long which
)
990 const struct x86_cpu_id
*m
= x86_match_cpu(table
);
992 return m
&& !!(m
->driver_data
& which
);
995 u64
x86_read_arch_cap_msr(void)
999 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES
))
1000 rdmsrl(MSR_IA32_ARCH_CAPABILITIES
, ia32_cap
);
1005 static void __init
cpu_set_bug_bits(struct cpuinfo_x86
*c
)
1007 u64 ia32_cap
= x86_read_arch_cap_msr();
1009 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */
1010 if (!cpu_matches(cpu_vuln_whitelist
, NO_ITLB_MULTIHIT
) &&
1011 !(ia32_cap
& ARCH_CAP_PSCHANGE_MC_NO
))
1012 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT
);
1014 if (cpu_matches(cpu_vuln_whitelist
, NO_SPECULATION
))
1017 setup_force_cpu_bug(X86_BUG_SPECTRE_V1
);
1018 setup_force_cpu_bug(X86_BUG_SPECTRE_V2
);
1020 if (!cpu_matches(cpu_vuln_whitelist
, NO_SSB
) &&
1021 !(ia32_cap
& ARCH_CAP_SSB_NO
) &&
1022 !cpu_has(c
, X86_FEATURE_AMD_SSB_NO
))
1023 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS
);
1025 if (ia32_cap
& ARCH_CAP_IBRS_ALL
)
1026 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED
);
1028 if (!cpu_matches(cpu_vuln_whitelist
, NO_MDS
) &&
1029 !(ia32_cap
& ARCH_CAP_MDS_NO
)) {
1030 setup_force_cpu_bug(X86_BUG_MDS
);
1031 if (cpu_matches(cpu_vuln_whitelist
, MSBDS_ONLY
))
1032 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY
);
1035 if (!cpu_matches(cpu_vuln_whitelist
, NO_SWAPGS
))
1036 setup_force_cpu_bug(X86_BUG_SWAPGS
);
1039 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when:
1040 * - TSX is supported or
1041 * - TSX_CTRL is present
1043 * TSX_CTRL check is needed for cases when TSX could be disabled before
1044 * the kernel boot e.g. kexec.
1045 * TSX_CTRL check alone is not sufficient for cases when the microcode
1046 * update is not present or running as guest that don't get TSX_CTRL.
1048 if (!(ia32_cap
& ARCH_CAP_TAA_NO
) &&
1049 (cpu_has(c
, X86_FEATURE_RTM
) ||
1050 (ia32_cap
& ARCH_CAP_TSX_CTRL_MSR
)))
1051 setup_force_cpu_bug(X86_BUG_TAA
);
1054 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed
1055 * in the vulnerability blacklist.
1057 if ((cpu_has(c
, X86_FEATURE_RDRAND
) ||
1058 cpu_has(c
, X86_FEATURE_RDSEED
)) &&
1059 cpu_matches(cpu_vuln_blacklist
, SRBDS
))
1060 setup_force_cpu_bug(X86_BUG_SRBDS
);
1062 if (cpu_matches(cpu_vuln_whitelist
, NO_MELTDOWN
))
1065 /* Rogue Data Cache Load? No! */
1066 if (ia32_cap
& ARCH_CAP_RDCL_NO
)
1069 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN
);
1071 if (cpu_matches(cpu_vuln_whitelist
, NO_L1TF
))
1074 setup_force_cpu_bug(X86_BUG_L1TF
);
1078 * Do minimum CPU detection early.
1079 * Fields really needed: vendor, cpuid_level, family, model, mask,
1081 * The others are not touched to avoid unwanted side effects.
1083 * WARNING: this function is only called on the BP. Don't add code here
1084 * that is supposed to run on all CPUs.
1086 static void __init
early_identify_cpu(struct cpuinfo_x86
*c
)
1088 #ifdef CONFIG_X86_64
1089 c
->x86_clflush_size
= 64;
1090 c
->x86_phys_bits
= 36;
1091 c
->x86_virt_bits
= 48;
1093 c
->x86_clflush_size
= 32;
1094 c
->x86_phys_bits
= 32;
1095 c
->x86_virt_bits
= 32;
1097 c
->x86_cache_alignment
= c
->x86_clflush_size
;
1099 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
1100 c
->extended_cpuid_level
= 0;
1102 if (!have_cpuid_p())
1103 identify_cpu_without_cpuid(c
);
1105 /* cyrix could have cpuid enabled via c_identify()*/
1106 if (have_cpuid_p()) {
1110 setup_force_cpu_cap(X86_FEATURE_CPUID
);
1112 if (this_cpu
->c_early_init
)
1113 this_cpu
->c_early_init(c
);
1116 filter_cpuid_features(c
, false);
1118 if (this_cpu
->c_bsp_init
)
1119 this_cpu
->c_bsp_init(c
);
1121 setup_clear_cpu_cap(X86_FEATURE_CPUID
);
1124 setup_force_cpu_cap(X86_FEATURE_ALWAYS
);
1126 cpu_set_bug_bits(c
);
1128 fpu__init_system(c
);
1130 #ifdef CONFIG_X86_32
1132 * Regardless of whether PCID is enumerated, the SDM says
1133 * that it can't be enabled in 32-bit mode.
1135 setup_clear_cpu_cap(X86_FEATURE_PCID
);
1139 void __init
early_cpu_init(void)
1141 const struct cpu_dev
*const *cdev
;
1144 #ifdef CONFIG_PROCESSOR_SELECT
1145 pr_info("KERNEL supported cpus:\n");
1148 for (cdev
= __x86_cpu_dev_start
; cdev
< __x86_cpu_dev_end
; cdev
++) {
1149 const struct cpu_dev
*cpudev
= *cdev
;
1151 if (count
>= X86_VENDOR_NUM
)
1153 cpu_devs
[count
] = cpudev
;
1156 #ifdef CONFIG_PROCESSOR_SELECT
1160 for (j
= 0; j
< 2; j
++) {
1161 if (!cpudev
->c_ident
[j
])
1163 pr_info(" %s %s\n", cpudev
->c_vendor
,
1164 cpudev
->c_ident
[j
]);
1169 early_identify_cpu(&boot_cpu_data
);
1173 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1174 * unfortunately, that's not true in practice because of early VIA
1175 * chips and (more importantly) broken virtualizers that are not easy
1176 * to detect. In the latter case it doesn't even *fail* reliably, so
1177 * probing for it doesn't even work. Disable it completely on 32-bit
1178 * unless we can find a reliable way to detect all the broken cases.
1179 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1181 static void detect_nopl(struct cpuinfo_x86
*c
)
1183 #ifdef CONFIG_X86_32
1184 clear_cpu_cap(c
, X86_FEATURE_NOPL
);
1186 set_cpu_cap(c
, X86_FEATURE_NOPL
);
1190 static void detect_null_seg_behavior(struct cpuinfo_x86
*c
)
1192 #ifdef CONFIG_X86_64
1194 * Empirically, writing zero to a segment selector on AMD does
1195 * not clear the base, whereas writing zero to a segment
1196 * selector on Intel does clear the base. Intel's behavior
1197 * allows slightly faster context switches in the common case
1198 * where GS is unused by the prev and next threads.
1200 * Since neither vendor documents this anywhere that I can see,
1201 * detect it directly instead of hardcoding the choice by
1204 * I've designated AMD's behavior as the "bug" because it's
1205 * counterintuitive and less friendly.
1208 unsigned long old_base
, tmp
;
1209 rdmsrl(MSR_FS_BASE
, old_base
);
1210 wrmsrl(MSR_FS_BASE
, 1);
1212 rdmsrl(MSR_FS_BASE
, tmp
);
1214 set_cpu_bug(c
, X86_BUG_NULL_SEG
);
1215 wrmsrl(MSR_FS_BASE
, old_base
);
1219 static void generic_identify(struct cpuinfo_x86
*c
)
1221 c
->extended_cpuid_level
= 0;
1223 if (!have_cpuid_p())
1224 identify_cpu_without_cpuid(c
);
1226 /* cyrix could have cpuid enabled via c_identify()*/
1227 if (!have_cpuid_p())
1236 if (c
->cpuid_level
>= 0x00000001) {
1237 c
->initial_apicid
= (cpuid_ebx(1) >> 24) & 0xFF;
1238 #ifdef CONFIG_X86_32
1240 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
1242 c
->apicid
= c
->initial_apicid
;
1245 c
->phys_proc_id
= c
->initial_apicid
;
1248 get_model_name(c
); /* Default name */
1252 detect_null_seg_behavior(c
);
1255 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1256 * systems that run Linux at CPL > 0 may or may not have the
1257 * issue, but, even if they have the issue, there's absolutely
1258 * nothing we can do about it because we can't use the real IRET
1261 * NB: For the time being, only 32-bit kernels support
1262 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1263 * whether to apply espfix using paravirt hooks. If any
1264 * non-paravirt system ever shows up that does *not* have the
1265 * ESPFIX issue, we can change this.
1267 #ifdef CONFIG_X86_32
1268 # ifdef CONFIG_PARAVIRT
1270 extern void native_iret(void);
1271 if (pv_cpu_ops
.iret
== native_iret
)
1272 set_cpu_bug(c
, X86_BUG_ESPFIX
);
1275 set_cpu_bug(c
, X86_BUG_ESPFIX
);
1280 static void x86_init_cache_qos(struct cpuinfo_x86
*c
)
1283 * The heavy lifting of max_rmid and cache_occ_scale are handled
1284 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
1285 * in case CQM bits really aren't there in this CPU.
1287 if (c
!= &boot_cpu_data
) {
1288 boot_cpu_data
.x86_cache_max_rmid
=
1289 min(boot_cpu_data
.x86_cache_max_rmid
,
1290 c
->x86_cache_max_rmid
);
1295 * Validate that ACPI/mptables have the same information about the
1296 * effective APIC id and update the package map.
1298 static void validate_apic_and_package_id(struct cpuinfo_x86
*c
)
1301 unsigned int apicid
, cpu
= smp_processor_id();
1303 apicid
= apic
->cpu_present_to_apicid(cpu
);
1305 if (apicid
!= c
->apicid
) {
1306 pr_err(FW_BUG
"CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1307 cpu
, apicid
, c
->initial_apicid
);
1309 BUG_ON(topology_update_package_map(c
->phys_proc_id
, cpu
));
1311 c
->logical_proc_id
= 0;
1316 * This does the hard work of actually picking apart the CPU stuff...
1318 static void identify_cpu(struct cpuinfo_x86
*c
)
1322 c
->loops_per_jiffy
= loops_per_jiffy
;
1323 c
->x86_cache_size
= 0;
1324 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
1325 c
->x86_model
= c
->x86_stepping
= 0; /* So far unknown... */
1326 c
->x86_vendor_id
[0] = '\0'; /* Unset */
1327 c
->x86_model_id
[0] = '\0'; /* Unset */
1328 c
->x86_max_cores
= 1;
1329 c
->x86_coreid_bits
= 0;
1331 #ifdef CONFIG_X86_64
1332 c
->x86_clflush_size
= 64;
1333 c
->x86_phys_bits
= 36;
1334 c
->x86_virt_bits
= 48;
1336 c
->cpuid_level
= -1; /* CPUID not detected */
1337 c
->x86_clflush_size
= 32;
1338 c
->x86_phys_bits
= 32;
1339 c
->x86_virt_bits
= 32;
1341 c
->x86_cache_alignment
= c
->x86_clflush_size
;
1342 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
1344 generic_identify(c
);
1346 if (this_cpu
->c_identify
)
1347 this_cpu
->c_identify(c
);
1349 /* Clear/Set all flags overridden by options, after probe */
1350 apply_forced_caps(c
);
1352 #ifdef CONFIG_X86_64
1353 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
1357 * Vendor-specific initialization. In this section we
1358 * canonicalize the feature flags, meaning if there are
1359 * features a certain CPU supports which CPUID doesn't
1360 * tell us, CPUID claiming incorrect flags, or other bugs,
1361 * we handle them here.
1363 * At the end of this section, c->x86_capability better
1364 * indicate the features this CPU genuinely supports!
1366 if (this_cpu
->c_init
)
1367 this_cpu
->c_init(c
);
1369 /* Disable the PN if appropriate */
1370 squash_the_stupid_serial_number(c
);
1372 /* Set up SMEP/SMAP */
1377 * The vendor-specific functions might have changed features.
1378 * Now we do "generic changes."
1381 /* Filter out anything that depends on CPUID levels we don't have */
1382 filter_cpuid_features(c
, true);
1384 /* If the model name is still unset, do table lookup. */
1385 if (!c
->x86_model_id
[0]) {
1387 p
= table_lookup_model(c
);
1389 strcpy(c
->x86_model_id
, p
);
1391 /* Last resort... */
1392 sprintf(c
->x86_model_id
, "%02x/%02x",
1393 c
->x86
, c
->x86_model
);
1396 #ifdef CONFIG_X86_64
1401 x86_init_cache_qos(c
);
1405 * Clear/Set all flags overridden by options, need do it
1406 * before following smp all cpus cap AND.
1408 apply_forced_caps(c
);
1411 * On SMP, boot_cpu_data holds the common feature set between
1412 * all CPUs; so make sure that we indicate which features are
1413 * common between the CPUs. The first time this routine gets
1414 * executed, c == &boot_cpu_data.
1416 if (c
!= &boot_cpu_data
) {
1417 /* AND the already accumulated flags with these */
1418 for (i
= 0; i
< NCAPINTS
; i
++)
1419 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
1421 /* OR, i.e. replicate the bug flags */
1422 for (i
= NCAPINTS
; i
< NCAPINTS
+ NBUGINTS
; i
++)
1423 c
->x86_capability
[i
] |= boot_cpu_data
.x86_capability
[i
];
1426 /* Init Machine Check Exception if available. */
1429 select_idle_routine(c
);
1432 numa_add_cpu(smp_processor_id());
1437 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1438 * on 32-bit kernels:
1440 #ifdef CONFIG_X86_32
1441 void enable_sep_cpu(void)
1443 struct tss_struct
*tss
;
1446 if (!boot_cpu_has(X86_FEATURE_SEP
))
1450 tss
= &per_cpu(cpu_tss_rw
, cpu
);
1453 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1454 * see the big comment in struct x86_hw_tss's definition.
1457 tss
->x86_tss
.ss1
= __KERNEL_CS
;
1458 wrmsr(MSR_IA32_SYSENTER_CS
, tss
->x86_tss
.ss1
, 0);
1459 wrmsr(MSR_IA32_SYSENTER_ESP
, (unsigned long)(cpu_entry_stack(cpu
) + 1), 0);
1460 wrmsr(MSR_IA32_SYSENTER_EIP
, (unsigned long)entry_SYSENTER_32
, 0);
1466 void __init
identify_boot_cpu(void)
1468 identify_cpu(&boot_cpu_data
);
1469 #ifdef CONFIG_X86_32
1473 cpu_detect_tlb(&boot_cpu_data
);
1477 void identify_secondary_cpu(struct cpuinfo_x86
*c
)
1479 BUG_ON(c
== &boot_cpu_data
);
1481 #ifdef CONFIG_X86_32
1485 validate_apic_and_package_id(c
);
1486 x86_spec_ctrl_setup_ap();
1490 static __init
int setup_noclflush(char *arg
)
1492 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH
);
1493 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT
);
1496 __setup("noclflush", setup_noclflush
);
1498 void print_cpu_info(struct cpuinfo_x86
*c
)
1500 const char *vendor
= NULL
;
1502 if (c
->x86_vendor
< X86_VENDOR_NUM
) {
1503 vendor
= this_cpu
->c_vendor
;
1505 if (c
->cpuid_level
>= 0)
1506 vendor
= c
->x86_vendor_id
;
1509 if (vendor
&& !strstr(c
->x86_model_id
, vendor
))
1510 pr_cont("%s ", vendor
);
1512 if (c
->x86_model_id
[0])
1513 pr_cont("%s", c
->x86_model_id
);
1515 pr_cont("%d86", c
->x86
);
1517 pr_cont(" (family: 0x%x, model: 0x%x", c
->x86
, c
->x86_model
);
1519 if (c
->x86_stepping
|| c
->cpuid_level
>= 0)
1520 pr_cont(", stepping: 0x%x)\n", c
->x86_stepping
);
1526 * clearcpuid= was already parsed in fpu__init_parse_early_param.
1527 * But we need to keep a dummy __setup around otherwise it would
1528 * show up as an environment variable for init.
1530 static __init
int setup_clearcpuid(char *arg
)
1534 __setup("clearcpuid=", setup_clearcpuid
);
1536 #ifdef CONFIG_X86_64
1537 DEFINE_PER_CPU_FIRST(union irq_stack_union
,
1538 irq_stack_union
) __aligned(PAGE_SIZE
) __visible
;
1541 * The following percpu variables are hot. Align current_task to
1542 * cacheline size such that they fall in the same cacheline.
1544 DEFINE_PER_CPU(struct task_struct
*, current_task
) ____cacheline_aligned
=
1546 EXPORT_PER_CPU_SYMBOL(current_task
);
1548 DEFINE_PER_CPU(char *, irq_stack_ptr
) =
1549 init_per_cpu_var(irq_stack_union
.irq_stack
) + IRQ_STACK_SIZE
;
1551 DEFINE_PER_CPU(unsigned int, irq_count
) __visible
= -1;
1553 DEFINE_PER_CPU(int, __preempt_count
) = INIT_PREEMPT_COUNT
;
1554 EXPORT_PER_CPU_SYMBOL(__preempt_count
);
1556 /* May not be marked __init: used by software suspend */
1557 void syscall_init(void)
1559 extern char _entry_trampoline
[];
1560 extern char entry_SYSCALL_64_trampoline
[];
1562 int cpu
= smp_processor_id();
1563 unsigned long SYSCALL64_entry_trampoline
=
1564 (unsigned long)get_cpu_entry_area(cpu
)->entry_trampoline
+
1565 (entry_SYSCALL_64_trampoline
- _entry_trampoline
);
1567 wrmsr(MSR_STAR
, 0, (__USER32_CS
<< 16) | __KERNEL_CS
);
1568 if (static_cpu_has(X86_FEATURE_PTI
))
1569 wrmsrl(MSR_LSTAR
, SYSCALL64_entry_trampoline
);
1571 wrmsrl(MSR_LSTAR
, (unsigned long)entry_SYSCALL_64
);
1573 #ifdef CONFIG_IA32_EMULATION
1574 wrmsrl(MSR_CSTAR
, (unsigned long)entry_SYSCALL_compat
);
1576 * This only works on Intel CPUs.
1577 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1578 * This does not cause SYSENTER to jump to the wrong location, because
1579 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1581 wrmsrl_safe(MSR_IA32_SYSENTER_CS
, (u64
)__KERNEL_CS
);
1582 wrmsrl_safe(MSR_IA32_SYSENTER_ESP
, (unsigned long)(cpu_entry_stack(cpu
) + 1));
1583 wrmsrl_safe(MSR_IA32_SYSENTER_EIP
, (u64
)entry_SYSENTER_compat
);
1585 wrmsrl(MSR_CSTAR
, (unsigned long)ignore_sysret
);
1586 wrmsrl_safe(MSR_IA32_SYSENTER_CS
, (u64
)GDT_ENTRY_INVALID_SEG
);
1587 wrmsrl_safe(MSR_IA32_SYSENTER_ESP
, 0ULL);
1588 wrmsrl_safe(MSR_IA32_SYSENTER_EIP
, 0ULL);
1591 /* Flags to clear on syscall */
1592 wrmsrl(MSR_SYSCALL_MASK
,
1593 X86_EFLAGS_TF
|X86_EFLAGS_DF
|X86_EFLAGS_IF
|
1594 X86_EFLAGS_IOPL
|X86_EFLAGS_AC
|X86_EFLAGS_NT
);
1598 * Copies of the original ist values from the tss are only accessed during
1599 * debugging, no special alignment required.
1601 DEFINE_PER_CPU(struct orig_ist
, orig_ist
);
1603 static DEFINE_PER_CPU(unsigned long, debug_stack_addr
);
1604 DEFINE_PER_CPU(int, debug_stack_usage
);
1606 int is_debug_stack(unsigned long addr
)
1608 return __this_cpu_read(debug_stack_usage
) ||
1609 (addr
<= __this_cpu_read(debug_stack_addr
) &&
1610 addr
> (__this_cpu_read(debug_stack_addr
) - DEBUG_STKSZ
));
1612 NOKPROBE_SYMBOL(is_debug_stack
);
1614 DEFINE_PER_CPU(u32
, debug_idt_ctr
);
1616 void debug_stack_set_zero(void)
1618 this_cpu_inc(debug_idt_ctr
);
1621 NOKPROBE_SYMBOL(debug_stack_set_zero
);
1623 void debug_stack_reset(void)
1625 if (WARN_ON(!this_cpu_read(debug_idt_ctr
)))
1627 if (this_cpu_dec_return(debug_idt_ctr
) == 0)
1630 NOKPROBE_SYMBOL(debug_stack_reset
);
1632 #else /* CONFIG_X86_64 */
1634 DEFINE_PER_CPU(struct task_struct
*, current_task
) = &init_task
;
1635 EXPORT_PER_CPU_SYMBOL(current_task
);
1636 DEFINE_PER_CPU(int, __preempt_count
) = INIT_PREEMPT_COUNT
;
1637 EXPORT_PER_CPU_SYMBOL(__preempt_count
);
1640 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1641 * the top of the kernel stack. Use an extra percpu variable to track the
1642 * top of the kernel stack directly.
1644 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack
) =
1645 (unsigned long)&init_thread_union
+ THREAD_SIZE
;
1646 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack
);
1648 #ifdef CONFIG_CC_STACKPROTECTOR
1649 DEFINE_PER_CPU_ALIGNED(struct stack_canary
, stack_canary
);
1652 #endif /* CONFIG_X86_64 */
1655 * Clear all 6 debug registers:
1657 static void clear_all_debug_regs(void)
1661 for (i
= 0; i
< 8; i
++) {
1662 /* Ignore db4, db5 */
1663 if ((i
== 4) || (i
== 5))
1672 * Restore debug regs if using kgdbwait and you have a kernel debugger
1673 * connection established.
1675 static void dbg_restore_debug_regs(void)
1677 if (unlikely(kgdb_connected
&& arch_kgdb_ops
.correct_hw_break
))
1678 arch_kgdb_ops
.correct_hw_break();
1680 #else /* ! CONFIG_KGDB */
1681 #define dbg_restore_debug_regs()
1682 #endif /* ! CONFIG_KGDB */
1684 static void wait_for_master_cpu(int cpu
)
1688 * wait for ACK from master CPU before continuing
1689 * with AP initialization
1691 WARN_ON(cpumask_test_and_set_cpu(cpu
, cpu_initialized_mask
));
1692 while (!cpumask_test_cpu(cpu
, cpu_callout_mask
))
1698 * cpu_init() initializes state that is per-CPU. Some data is already
1699 * initialized (naturally) in the bootstrap process, such as the GDT
1700 * and IDT. We reload them nevertheless, this function acts as a
1701 * 'CPU state barrier', nothing should get across.
1702 * A lot of state is already set up in PDA init for 64 bit
1704 #ifdef CONFIG_X86_64
1708 struct orig_ist
*oist
;
1709 struct task_struct
*me
;
1710 struct tss_struct
*t
;
1712 int cpu
= raw_smp_processor_id();
1715 wait_for_master_cpu(cpu
);
1718 * Initialize the CR4 shadow before doing anything that could
1726 t
= &per_cpu(cpu_tss_rw
, cpu
);
1727 oist
= &per_cpu(orig_ist
, cpu
);
1730 if (this_cpu_read(numa_node
) == 0 &&
1731 early_cpu_to_node(cpu
) != NUMA_NO_NODE
)
1732 set_numa_node(early_cpu_to_node(cpu
));
1737 pr_debug("Initializing CPU#%d\n", cpu
);
1739 cr4_clear_bits(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1742 * Initialize the per-CPU GDT with the boot GDT,
1743 * and set up the GDT descriptor:
1746 switch_to_new_gdt(cpu
);
1751 memset(me
->thread
.tls_array
, 0, GDT_ENTRY_TLS_ENTRIES
* 8);
1754 wrmsrl(MSR_FS_BASE
, 0);
1755 wrmsrl(MSR_KERNEL_GS_BASE
, 0);
1762 * set up and load the per-CPU TSS
1764 if (!oist
->ist
[0]) {
1765 char *estacks
= get_cpu_entry_area(cpu
)->exception_stacks
;
1767 for (v
= 0; v
< N_EXCEPTION_STACKS
; v
++) {
1768 estacks
+= exception_stack_sizes
[v
];
1769 oist
->ist
[v
] = t
->x86_tss
.ist
[v
] =
1770 (unsigned long)estacks
;
1771 if (v
== DEBUG_STACK
-1)
1772 per_cpu(debug_stack_addr
, cpu
) = (unsigned long)estacks
;
1776 t
->x86_tss
.io_bitmap_base
= IO_BITMAP_OFFSET
;
1779 * <= is required because the CPU will access up to
1780 * 8 bits beyond the end of the IO permission bitmap.
1782 for (i
= 0; i
<= IO_BITMAP_LONGS
; i
++)
1783 t
->io_bitmap
[i
] = ~0UL;
1786 me
->active_mm
= &init_mm
;
1788 initialize_tlbstate_and_flush();
1789 enter_lazy_tlb(&init_mm
, me
);
1792 * Initialize the TSS. sp0 points to the entry trampoline stack
1793 * regardless of what task is running.
1795 set_tss_desc(cpu
, &get_cpu_entry_area(cpu
)->tss
.x86_tss
);
1797 load_sp0((unsigned long)(cpu_entry_stack(cpu
) + 1));
1799 load_mm_ldt(&init_mm
);
1801 clear_all_debug_regs();
1802 dbg_restore_debug_regs();
1809 load_fixmap_gdt(cpu
);
1816 int cpu
= smp_processor_id();
1817 struct task_struct
*curr
= current
;
1818 struct tss_struct
*t
= &per_cpu(cpu_tss_rw
, cpu
);
1820 wait_for_master_cpu(cpu
);
1823 * Initialize the CR4 shadow before doing anything that could
1828 show_ucode_info_early();
1830 pr_info("Initializing CPU#%d\n", cpu
);
1832 if (cpu_feature_enabled(X86_FEATURE_VME
) ||
1833 boot_cpu_has(X86_FEATURE_TSC
) ||
1834 boot_cpu_has(X86_FEATURE_DE
))
1835 cr4_clear_bits(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1838 switch_to_new_gdt(cpu
);
1841 * Set up and load the per-CPU TSS and LDT
1844 curr
->active_mm
= &init_mm
;
1846 initialize_tlbstate_and_flush();
1847 enter_lazy_tlb(&init_mm
, curr
);
1850 * Initialize the TSS. Don't bother initializing sp0, as the initial
1851 * task never enters user mode.
1853 set_tss_desc(cpu
, &get_cpu_entry_area(cpu
)->tss
.x86_tss
);
1856 load_mm_ldt(&init_mm
);
1858 t
->x86_tss
.io_bitmap_base
= IO_BITMAP_OFFSET
;
1860 #ifdef CONFIG_DOUBLEFAULT
1861 /* Set up doublefault TSS pointer in the GDT */
1862 __set_tss_desc(cpu
, GDT_ENTRY_DOUBLEFAULT_TSS
, &doublefault_tss
);
1865 clear_all_debug_regs();
1866 dbg_restore_debug_regs();
1870 load_fixmap_gdt(cpu
);
1874 static void bsp_resume(void)
1876 if (this_cpu
->c_bsp_resume
)
1877 this_cpu
->c_bsp_resume(&boot_cpu_data
);
1880 static struct syscore_ops cpu_syscore_ops
= {
1881 .resume
= bsp_resume
,
1884 static int __init
init_cpu_syscore(void)
1886 register_syscore_ops(&cpu_syscore_ops
);
1889 core_initcall(init_cpu_syscore
);
1892 * The microcode loader calls this upon late microcode load to recheck features,
1893 * only when microcode has been updated. Caller holds microcode_mutex and CPU
1896 void microcode_check(void)
1898 struct cpuinfo_x86 info
;
1900 perf_check_microcode();
1902 /* Reload CPUID max function as it might've changed. */
1903 info
.cpuid_level
= cpuid_eax(0);
1906 * Copy all capability leafs to pick up the synthetic ones so that
1907 * memcmp() below doesn't fail on that. The ones coming from CPUID will
1908 * get overwritten in get_cpu_cap().
1910 memcpy(&info
.x86_capability
, &boot_cpu_data
.x86_capability
, sizeof(info
.x86_capability
));
1914 if (!memcmp(&info
.x86_capability
, &boot_cpu_data
.x86_capability
, sizeof(info
.x86_capability
)))
1917 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
1918 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");