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mm: fix exec activate_mm vs TLB shootdown and lazy tlb switching race
[linux/fpc-iii.git] / arch / x86 / kernel / cpu / intel.c
blob3a5ea741701b0ce669324b125699e812459526e3
1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/kernel.h>
3
4 #include <linux/string.h>
5 #include <linux/bitops.h>
6 #include <linux/smp.h>
7 #include <linux/sched.h>
8 #include <linux/sched/clock.h>
9 #include <linux/thread_info.h>
10 #include <linux/init.h>
11 #include <linux/uaccess.h>
12
13 #include <asm/cpufeature.h>
14 #include <asm/pgtable.h>
15 #include <asm/msr.h>
16 #include <asm/bugs.h>
17 #include <asm/cpu.h>
18 #include <asm/intel-family.h>
19 #include <asm/microcode_intel.h>
20 #include <asm/hwcap2.h>
21 #include <asm/elf.h>
22
23 #ifdef CONFIG_X86_64
24 #include <linux/topology.h>
25 #endif
26
27 #include "cpu.h"
28
29 #ifdef CONFIG_X86_LOCAL_APIC
30 #include <asm/mpspec.h>
31 #include <asm/apic.h>
32 #endif
33
34 /*
35 * Just in case our CPU detection goes bad, or you have a weird system,
36 * allow a way to override the automatic disabling of MPX.
37 */
38 static int forcempx;
39
40 static int __init forcempx_setup(char *__unused)
41 {
42 forcempx = 1;
43
44 return 1;
45 }
46 __setup("intel-skd-046-workaround=disable", forcempx_setup);
47
48 void check_mpx_erratum(struct cpuinfo_x86 *c)
49 {
50 if (forcempx)
51 return;
52 /*
53 * Turn off the MPX feature on CPUs where SMEP is not
54 * available or disabled.
55 *
56 * Works around Intel Erratum SKD046: "Branch Instructions
57 * May Initialize MPX Bound Registers Incorrectly".
58 *
59 * This might falsely disable MPX on systems without
60 * SMEP, like Atom processors without SMEP. But there
61 * is no such hardware known at the moment.
62 */
63 if (cpu_has(c, X86_FEATURE_MPX) && !cpu_has(c, X86_FEATURE_SMEP)) {
64 setup_clear_cpu_cap(X86_FEATURE_MPX);
65 pr_warn("x86/mpx: Disabling MPX since SMEP not present\n");
66 }
67 }
68
69 static bool ring3mwait_disabled __read_mostly;
70
71 static int __init ring3mwait_disable(char *__unused)
72 {
73 ring3mwait_disabled = true;
74 return 0;
75 }
76 __setup("ring3mwait=disable", ring3mwait_disable);
77
78 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
79 {
80 /*
81 * Ring 3 MONITOR/MWAIT feature cannot be detected without
82 * cpu model and family comparison.
83 */
84 if (c->x86 != 6)
85 return;
86 switch (c->x86_model) {
87 case INTEL_FAM6_XEON_PHI_KNL:
88 case INTEL_FAM6_XEON_PHI_KNM:
89 break;
90 default:
91 return;
92 }
93
94 if (ring3mwait_disabled)
95 return;
96
97 set_cpu_cap(c, X86_FEATURE_RING3MWAIT);
98 this_cpu_or(msr_misc_features_shadow,
99 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT);
100
101 if (c == &boot_cpu_data)
102 ELF_HWCAP2 |= HWCAP2_RING3MWAIT;
103 }
104
105 /*
106 * Early microcode releases for the Spectre v2 mitigation were broken.
107 * Information taken from;
108 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
109 * - https://kb.vmware.com/s/article/52345
110 * - Microcode revisions observed in the wild
111 * - Release note from 20180108 microcode release
112 */
113 struct sku_microcode {
114 u8 model;
115 u8 stepping;
116 u32 microcode;
117 };
118 static const struct sku_microcode spectre_bad_microcodes[] = {
119 { INTEL_FAM6_KABYLAKE_DESKTOP, 0x0B, 0x80 },
120 { INTEL_FAM6_KABYLAKE_DESKTOP, 0x0A, 0x80 },
121 { INTEL_FAM6_KABYLAKE_DESKTOP, 0x09, 0x80 },
122 { INTEL_FAM6_KABYLAKE_MOBILE, 0x0A, 0x80 },
123 { INTEL_FAM6_KABYLAKE_MOBILE, 0x09, 0x80 },
124 { INTEL_FAM6_SKYLAKE_X, 0x03, 0x0100013e },
125 { INTEL_FAM6_SKYLAKE_X, 0x04, 0x0200003c },
126 { INTEL_FAM6_BROADWELL_CORE, 0x04, 0x28 },
127 { INTEL_FAM6_BROADWELL_GT3E, 0x01, 0x1b },
128 { INTEL_FAM6_BROADWELL_XEON_D, 0x02, 0x14 },
129 { INTEL_FAM6_BROADWELL_XEON_D, 0x03, 0x07000011 },
130 { INTEL_FAM6_BROADWELL_X, 0x01, 0x0b000025 },
131 { INTEL_FAM6_HASWELL_ULT, 0x01, 0x21 },
132 { INTEL_FAM6_HASWELL_GT3E, 0x01, 0x18 },
133 { INTEL_FAM6_HASWELL_CORE, 0x03, 0x23 },
134 { INTEL_FAM6_HASWELL_X, 0x02, 0x3b },
135 { INTEL_FAM6_HASWELL_X, 0x04, 0x10 },
136 { INTEL_FAM6_IVYBRIDGE_X, 0x04, 0x42a },
137 /* Observed in the wild */
138 { INTEL_FAM6_SANDYBRIDGE_X, 0x06, 0x61b },
139 { INTEL_FAM6_SANDYBRIDGE_X, 0x07, 0x712 },
140 };
141
142 static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
143 {
144 int i;
145
146 /*
147 * We know that the hypervisor lie to us on the microcode version so
148 * we may as well hope that it is running the correct version.
149 */
150 if (cpu_has(c, X86_FEATURE_HYPERVISOR))
151 return false;
152
153 if (c->x86 != 6)
154 return false;
155
156 for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) {
157 if (c->x86_model == spectre_bad_microcodes[i].model &&
158 c->x86_stepping == spectre_bad_microcodes[i].stepping)
159 return (c->microcode <= spectre_bad_microcodes[i].microcode);
160 }
161 return false;
162 }
163
164 static void early_init_intel(struct cpuinfo_x86 *c)
165 {
166 u64 misc_enable;
167
168 /* Unmask CPUID levels if masked: */
169 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
170 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
171 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
172 c->cpuid_level = cpuid_eax(0);
173 get_cpu_cap(c);
174 }
175 }
176
177 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
178 (c->x86 == 0x6 && c->x86_model >= 0x0e))
179 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
180
181 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))
182 c->microcode = intel_get_microcode_revision();
183
184 /* Now if any of them are set, check the blacklist and clear the lot */
185 if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) ||
186 cpu_has(c, X86_FEATURE_INTEL_STIBP) ||
187 cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) ||
188 cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) {
189 pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n");
190 setup_clear_cpu_cap(X86_FEATURE_IBRS);
191 setup_clear_cpu_cap(X86_FEATURE_IBPB);
192 setup_clear_cpu_cap(X86_FEATURE_STIBP);
193 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL);
194 setup_clear_cpu_cap(X86_FEATURE_MSR_SPEC_CTRL);
195 setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP);
196 setup_clear_cpu_cap(X86_FEATURE_SSBD);
197 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL_SSBD);
198 }
199
200 /*
201 * Atom erratum AAE44/AAF40/AAG38/AAH41:
202 *
203 * A race condition between speculative fetches and invalidating
204 * a large page. This is worked around in microcode, but we
205 * need the microcode to have already been loaded... so if it is
206 * not, recommend a BIOS update and disable large pages.
207 */
208 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 &&
209 c->microcode < 0x20e) {
210 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
211 clear_cpu_cap(c, X86_FEATURE_PSE);
212 }
213
214 #ifdef CONFIG_X86_64
215 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
216 #else
217 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
218 if (c->x86 == 15 && c->x86_cache_alignment == 64)
219 c->x86_cache_alignment = 128;
220 #endif
221
222 /* CPUID workaround for 0F33/0F34 CPU */
223 if (c->x86 == 0xF && c->x86_model == 0x3
224 && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))
225 c->x86_phys_bits = 36;
226
227 /*
228 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
229 * with P/T states and does not stop in deep C-states.
230 *
231 * It is also reliable across cores and sockets. (but not across
232 * cabinets - we turn it off in that case explicitly.)
233 */
234 if (c->x86_power & (1 << 8)) {
235 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
236 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
237 }
238
239 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
240 if (c->x86 == 6) {
241 switch (c->x86_model) {
242 case 0x27: /* Penwell */
243 case 0x35: /* Cloverview */
244 case 0x4a: /* Merrifield */
245 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
246 break;
247 default:
248 break;
249 }
250 }
251
252 /*
253 * There is a known erratum on Pentium III and Core Solo
254 * and Core Duo CPUs.
255 * " Page with PAT set to WC while associated MTRR is UC
256 * may consolidate to UC "
257 * Because of this erratum, it is better to stick with
258 * setting WC in MTRR rather than using PAT on these CPUs.
259 *
260 * Enable PAT WC only on P4, Core 2 or later CPUs.
261 */
262 if (c->x86 == 6 && c->x86_model < 15)
263 clear_cpu_cap(c, X86_FEATURE_PAT);
264
265 /*
266 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
267 * clear the fast string and enhanced fast string CPU capabilities.
268 */
269 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
270 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
271 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
272 pr_info("Disabled fast string operations\n");
273 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
274 setup_clear_cpu_cap(X86_FEATURE_ERMS);
275 }
276 }
277
278 /*
279 * Intel Quark Core DevMan_001.pdf section 6.4.11
280 * "The operating system also is required to invalidate (i.e., flush)
281 * the TLB when any changes are made to any of the page table entries.
282 * The operating system must reload CR3 to cause the TLB to be flushed"
283 *
284 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h
285 * should be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE
286 * to be modified.
287 */
288 if (c->x86 == 5 && c->x86_model == 9) {
289 pr_info("Disabling PGE capability bit\n");
290 setup_clear_cpu_cap(X86_FEATURE_PGE);
291 }
292
293 if (c->cpuid_level >= 0x00000001) {
294 u32 eax, ebx, ecx, edx;
295
296 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
297 /*
298 * If HTT (EDX[28]) is set EBX[16:23] contain the number of
299 * apicids which are reserved per package. Store the resulting
300 * shift value for the package management code.
301 */
302 if (edx & (1U << 28))
303 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
304 }
305
306 check_mpx_erratum(c);
307
308 /*
309 * Get the number of SMT siblings early from the extended topology
310 * leaf, if available. Otherwise try the legacy SMT detection.
311 */
312 if (detect_extended_topology_early(c) < 0)
313 detect_ht_early(c);
314 }
315
316 #ifdef CONFIG_X86_32
317 /*
318 * Early probe support logic for ppro memory erratum #50
319 *
320 * This is called before we do cpu ident work
321 */
322
323 int ppro_with_ram_bug(void)
324 {
325 /* Uses data from early_cpu_detect now */
326 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
327 boot_cpu_data.x86 == 6 &&
328 boot_cpu_data.x86_model == 1 &&
329 boot_cpu_data.x86_stepping < 8) {
330 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
331 return 1;
332 }
333 return 0;
334 }
335
336 static void intel_smp_check(struct cpuinfo_x86 *c)
337 {
338 /* calling is from identify_secondary_cpu() ? */
339 if (!c->cpu_index)
340 return;
341
342 /*
343 * Mask B, Pentium, but not Pentium MMX
344 */
345 if (c->x86 == 5 &&
346 c->x86_stepping >= 1 && c->x86_stepping <= 4 &&
347 c->x86_model <= 3) {
348 /*
349 * Remember we have B step Pentia with bugs
350 */
351 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
352 "with B stepping processors.\n");
353 }
354 }
355
356 static int forcepae;
357 static int __init forcepae_setup(char *__unused)
358 {
359 forcepae = 1;
360 return 1;
361 }
362 __setup("forcepae", forcepae_setup);
363
364 static void intel_workarounds(struct cpuinfo_x86 *c)
365 {
366 #ifdef CONFIG_X86_F00F_BUG
367 /*
368 * All models of Pentium and Pentium with MMX technology CPUs
369 * have the F0 0F bug, which lets nonprivileged users lock up the
370 * system. Announce that the fault handler will be checking for it.
371 * The Quark is also family 5, but does not have the same bug.
372 */
373 clear_cpu_bug(c, X86_BUG_F00F);
374 if (c->x86 == 5 && c->x86_model < 9) {
375 static int f00f_workaround_enabled;
376
377 set_cpu_bug(c, X86_BUG_F00F);
378 if (!f00f_workaround_enabled) {
379 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");
380 f00f_workaround_enabled = 1;
381 }
382 }
383 #endif
384
385 /*
386 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
387 * model 3 mask 3
388 */
389 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)
390 clear_cpu_cap(c, X86_FEATURE_SEP);
391
392 /*
393 * PAE CPUID issue: many Pentium M report no PAE but may have a
394 * functionally usable PAE implementation.
395 * Forcefully enable PAE if kernel parameter "forcepae" is present.
396 */
397 if (forcepae) {
398 pr_warn("PAE forced!\n");
399 set_cpu_cap(c, X86_FEATURE_PAE);
400 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
401 }
402
403 /*
404 * P4 Xeon erratum 037 workaround.
405 * Hardware prefetcher may cause stale data to be loaded into the cache.
406 */
407 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {
408 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
409 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
410 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
411 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
412 }
413 }
414
415 /*
416 * See if we have a good local APIC by checking for buggy Pentia,
417 * i.e. all B steppings and the C2 stepping of P54C when using their
418 * integrated APIC (see 11AP erratum in "Pentium Processor
419 * Specification Update").
420 */
421 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
422 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))
423 set_cpu_bug(c, X86_BUG_11AP);
424
425
426 #ifdef CONFIG_X86_INTEL_USERCOPY
427 /*
428 * Set up the preferred alignment for movsl bulk memory moves
429 */
430 switch (c->x86) {
431 case 4: /* 486: untested */
432 break;
433 case 5: /* Old Pentia: untested */
434 break;
435 case 6: /* PII/PIII only like movsl with 8-byte alignment */
436 movsl_mask.mask = 7;
437 break;
438 case 15: /* P4 is OK down to 8-byte alignment */
439 movsl_mask.mask = 7;
440 break;
441 }
442 #endif
443
444 intel_smp_check(c);
445 }
446 #else
447 static void intel_workarounds(struct cpuinfo_x86 *c)
448 {
449 }
450 #endif
451
452 static void srat_detect_node(struct cpuinfo_x86 *c)
453 {
454 #ifdef CONFIG_NUMA
455 unsigned node;
456 int cpu = smp_processor_id();
457
458 /* Don't do the funky fallback heuristics the AMD version employs
459 for now. */
460 node = numa_cpu_node(cpu);
461 if (node == NUMA_NO_NODE || !node_online(node)) {
462 /* reuse the value from init_cpu_to_node() */
463 node = cpu_to_node(cpu);
464 }
465 numa_set_node(cpu, node);
466 #endif
467 }
468
469 /*
470 * find out the number of processor cores on the die
471 */
472 static int intel_num_cpu_cores(struct cpuinfo_x86 *c)
473 {
474 unsigned int eax, ebx, ecx, edx;
475
476 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
477 return 1;
478
479 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
480 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
481 if (eax & 0x1f)
482 return (eax >> 26) + 1;
483 else
484 return 1;
485 }
486
487 static void detect_vmx_virtcap(struct cpuinfo_x86 *c)
488 {
489 /* Intel VMX MSR indicated features */
490 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
491 #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
492 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
493 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
494 #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
495 #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
496
497 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
498
499 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
500 clear_cpu_cap(c, X86_FEATURE_VNMI);
501 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
502 clear_cpu_cap(c, X86_FEATURE_EPT);
503 clear_cpu_cap(c, X86_FEATURE_VPID);
504
505 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
506 msr_ctl = vmx_msr_high | vmx_msr_low;
507 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
508 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
509 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
510 set_cpu_cap(c, X86_FEATURE_VNMI);
511 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
512 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
513 vmx_msr_low, vmx_msr_high);
514 msr_ctl2 = vmx_msr_high | vmx_msr_low;
515 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
516 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
517 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
518 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
519 set_cpu_cap(c, X86_FEATURE_EPT);
520 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
521 set_cpu_cap(c, X86_FEATURE_VPID);
522 }
523 }
524
525 static void init_intel_energy_perf(struct cpuinfo_x86 *c)
526 {
527 u64 epb;
528
529 /*
530 * Initialize MSR_IA32_ENERGY_PERF_BIAS if not already initialized.
531 * (x86_energy_perf_policy(8) is available to change it at run-time.)
532 */
533 if (!cpu_has(c, X86_FEATURE_EPB))
534 return;
535
536 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
537 if ((epb & 0xF) != ENERGY_PERF_BIAS_PERFORMANCE)
538 return;
539
540 pr_warn_once("ENERGY_PERF_BIAS: Set to 'normal', was 'performance'\n");
541 pr_warn_once("ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)\n");
542 epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL;
543 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
544 }
545
546 static void intel_bsp_resume(struct cpuinfo_x86 *c)
547 {
548 /*
549 * MSR_IA32_ENERGY_PERF_BIAS is lost across suspend/resume,
550 * so reinitialize it properly like during bootup:
551 */
552 init_intel_energy_perf(c);
553 }
554
555 static void init_cpuid_fault(struct cpuinfo_x86 *c)
556 {
557 u64 msr;
558
559 if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) {
560 if (msr & MSR_PLATFORM_INFO_CPUID_FAULT)
561 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT);
562 }
563 }
564
565 static void init_intel_misc_features(struct cpuinfo_x86 *c)
566 {
567 u64 msr;
568
569 if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr))
570 return;
571
572 /* Clear all MISC features */
573 this_cpu_write(msr_misc_features_shadow, 0);
574
575 /* Check features and update capabilities and shadow control bits */
576 init_cpuid_fault(c);
577 probe_xeon_phi_r3mwait(c);
578
579 msr = this_cpu_read(msr_misc_features_shadow);
580 wrmsrl(MSR_MISC_FEATURES_ENABLES, msr);
581 }
582
583 static void init_intel(struct cpuinfo_x86 *c)
584 {
585 unsigned int l2 = 0;
586
587 early_init_intel(c);
588
589 intel_workarounds(c);
590
591 /*
592 * Detect the extended topology information if available. This
593 * will reinitialise the initial_apicid which will be used
594 * in init_intel_cacheinfo()
595 */
596 detect_extended_topology(c);
597
598 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
599 /*
600 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
601 * detection.
602 */
603 c->x86_max_cores = intel_num_cpu_cores(c);
604 #ifdef CONFIG_X86_32
605 detect_ht(c);
606 #endif
607 }
608
609 l2 = init_intel_cacheinfo(c);
610
611 /* Detect legacy cache sizes if init_intel_cacheinfo did not */
612 if (l2 == 0) {
613 cpu_detect_cache_sizes(c);
614 l2 = c->x86_cache_size;
615 }
616
617 if (c->cpuid_level > 9) {
618 unsigned eax = cpuid_eax(10);
619 /* Check for version and the number of counters */
620 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
621 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
622 }
623
624 if (cpu_has(c, X86_FEATURE_XMM2))
625 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
626
627 if (boot_cpu_has(X86_FEATURE_DS)) {
628 unsigned int l1;
629 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
630 if (!(l1 & (1<<11)))
631 set_cpu_cap(c, X86_FEATURE_BTS);
632 if (!(l1 & (1<<12)))
633 set_cpu_cap(c, X86_FEATURE_PEBS);
634 }
635
636 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) &&
637 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
638 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
639
640 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) &&
641 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT)))
642 set_cpu_bug(c, X86_BUG_MONITOR);
643
644 #ifdef CONFIG_X86_64
645 if (c->x86 == 15)
646 c->x86_cache_alignment = c->x86_clflush_size * 2;
647 if (c->x86 == 6)
648 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
649 #else
650 /*
651 * Names for the Pentium II/Celeron processors
652 * detectable only by also checking the cache size.
653 * Dixon is NOT a Celeron.
654 */
655 if (c->x86 == 6) {
656 char *p = NULL;
657
658 switch (c->x86_model) {
659 case 5:
660 if (l2 == 0)
661 p = "Celeron (Covington)";
662 else if (l2 == 256)
663 p = "Mobile Pentium II (Dixon)";
664 break;
665
666 case 6:
667 if (l2 == 128)
668 p = "Celeron (Mendocino)";
669 else if (c->x86_stepping == 0 || c->x86_stepping == 5)
670 p = "Celeron-A";
671 break;
672
673 case 8:
674 if (l2 == 128)
675 p = "Celeron (Coppermine)";
676 break;
677 }
678
679 if (p)
680 strcpy(c->x86_model_id, p);
681 }
682
683 if (c->x86 == 15)
684 set_cpu_cap(c, X86_FEATURE_P4);
685 if (c->x86 == 6)
686 set_cpu_cap(c, X86_FEATURE_P3);
687 #endif
688
689 /* Work around errata */
690 srat_detect_node(c);
691
692 if (cpu_has(c, X86_FEATURE_VMX))
693 detect_vmx_virtcap(c);
694
695 init_intel_energy_perf(c);
696
697 init_intel_misc_features(c);
698
699 if (tsx_ctrl_state == TSX_CTRL_ENABLE)
700 tsx_enable();
701 if (tsx_ctrl_state == TSX_CTRL_DISABLE)
702 tsx_disable();
703 }
704
705 #ifdef CONFIG_X86_32
706 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
707 {
708 /*
709 * Intel PIII Tualatin. This comes in two flavours.
710 * One has 256kb of cache, the other 512. We have no way
711 * to determine which, so we use a boottime override
712 * for the 512kb model, and assume 256 otherwise.
713 */
714 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
715 size = 256;
716
717 /*
718 * Intel Quark SoC X1000 contains a 4-way set associative
719 * 16K cache with a 16 byte cache line and 256 lines per tag
720 */
721 if ((c->x86 == 5) && (c->x86_model == 9))
722 size = 16;
723 return size;
724 }
725 #endif
726
727 #define TLB_INST_4K 0x01
728 #define TLB_INST_4M 0x02
729 #define TLB_INST_2M_4M 0x03
730
731 #define TLB_INST_ALL 0x05
732 #define TLB_INST_1G 0x06
733
734 #define TLB_DATA_4K 0x11
735 #define TLB_DATA_4M 0x12
736 #define TLB_DATA_2M_4M 0x13
737 #define TLB_DATA_4K_4M 0x14
738
739 #define TLB_DATA_1G 0x16
740
741 #define TLB_DATA0_4K 0x21
742 #define TLB_DATA0_4M 0x22
743 #define TLB_DATA0_2M_4M 0x23
744
745 #define STLB_4K 0x41
746 #define STLB_4K_2M 0x42
747
748 static const struct _tlb_table intel_tlb_table[] = {
749 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
750 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
751 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
752 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
753 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
754 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
755 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" },
756 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
757 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
758 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
759 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
760 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
761 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
762 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
763 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
764 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
765 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
766 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
767 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
768 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
769 { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" },
770 { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
771 { 0x6d, TLB_DATA_1G, 16, " TLB_DATA 1 GByte pages, fully associative" },
772 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
773 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
774 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
775 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
776 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
777 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
778 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
779 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
780 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
781 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
782 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
783 { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" },
784 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
785 { 0x00, 0, 0 }
786 };
787
788 static void intel_tlb_lookup(const unsigned char desc)
789 {
790 unsigned char k;
791 if (desc == 0)
792 return;
793
794 /* look up this descriptor in the table */
795 for (k = 0; intel_tlb_table[k].descriptor != desc && \
796 intel_tlb_table[k].descriptor != 0; k++)
797 ;
798
799 if (intel_tlb_table[k].tlb_type == 0)
800 return;
801
802 switch (intel_tlb_table[k].tlb_type) {
803 case STLB_4K:
804 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
805 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
806 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
807 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
808 break;
809 case STLB_4K_2M:
810 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
811 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
812 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
813 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
814 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
815 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
816 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
817 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
818 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
819 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
820 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
821 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
822 break;
823 case TLB_INST_ALL:
824 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
825 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
826 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
827 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
828 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
829 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
830 break;
831 case TLB_INST_4K:
832 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
833 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
834 break;
835 case TLB_INST_4M:
836 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
837 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
838 break;
839 case TLB_INST_2M_4M:
840 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
841 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
842 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
843 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
844 break;
845 case TLB_DATA_4K:
846 case TLB_DATA0_4K:
847 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
848 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
849 break;
850 case TLB_DATA_4M:
851 case TLB_DATA0_4M:
852 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
853 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
854 break;
855 case TLB_DATA_2M_4M:
856 case TLB_DATA0_2M_4M:
857 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
858 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
859 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
860 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
861 break;
862 case TLB_DATA_4K_4M:
863 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
864 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
865 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
866 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
867 break;
868 case TLB_DATA_1G:
869 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
870 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
871 break;
872 }
873 }
874
875 static void intel_detect_tlb(struct cpuinfo_x86 *c)
876 {
877 int i, j, n;
878 unsigned int regs[4];
879 unsigned char *desc = (unsigned char *)regs;
880
881 if (c->cpuid_level < 2)
882 return;
883
884 /* Number of times to iterate */
885 n = cpuid_eax(2) & 0xFF;
886
887 for (i = 0 ; i < n ; i++) {
888 cpuid(2, &regs[0], &regs[1], &regs[2], &regs[3]);
889
890 /* If bit 31 is set, this is an unknown format */
891 for (j = 0 ; j < 3 ; j++)
892 if (regs[j] & (1 << 31))
893 regs[j] = 0;
894
895 /* Byte 0 is level count, not a descriptor */
896 for (j = 1 ; j < 16 ; j++)
897 intel_tlb_lookup(desc[j]);
898 }
899 }
900
901 static const struct cpu_dev intel_cpu_dev = {
902 .c_vendor = "Intel",
903 .c_ident = { "GenuineIntel" },
904 #ifdef CONFIG_X86_32
905 .legacy_models = {
906 { .family = 4, .model_names =
907 {
908 [0] = "486 DX-25/33",
909 [1] = "486 DX-50",
910 [2] = "486 SX",
911 [3] = "486 DX/2",
912 [4] = "486 SL",
913 [5] = "486 SX/2",
914 [7] = "486 DX/2-WB",
915 [8] = "486 DX/4",
916 [9] = "486 DX/4-WB"
917 }
918 },
919 { .family = 5, .model_names =
920 {
921 [0] = "Pentium 60/66 A-step",
922 [1] = "Pentium 60/66",
923 [2] = "Pentium 75 - 200",
924 [3] = "OverDrive PODP5V83",
925 [4] = "Pentium MMX",
926 [7] = "Mobile Pentium 75 - 200",
927 [8] = "Mobile Pentium MMX",
928 [9] = "Quark SoC X1000",
929 }
930 },
931 { .family = 6, .model_names =
932 {
933 [0] = "Pentium Pro A-step",
934 [1] = "Pentium Pro",
935 [3] = "Pentium II (Klamath)",
936 [4] = "Pentium II (Deschutes)",
937 [5] = "Pentium II (Deschutes)",
938 [6] = "Mobile Pentium II",
939 [7] = "Pentium III (Katmai)",
940 [8] = "Pentium III (Coppermine)",
941 [10] = "Pentium III (Cascades)",
942 [11] = "Pentium III (Tualatin)",
943 }
944 },
945 { .family = 15, .model_names =
946 {
947 [0] = "Pentium 4 (Unknown)",
948 [1] = "Pentium 4 (Willamette)",
949 [2] = "Pentium 4 (Northwood)",
950 [4] = "Pentium 4 (Foster)",
951 [5] = "Pentium 4 (Foster)",
952 }
953 },
954 },
955 .legacy_cache_size = intel_size_cache,
956 #endif
957 .c_detect_tlb = intel_detect_tlb,
958 .c_early_init = early_init_intel,
959 .c_init = init_intel,
960 .c_bsp_resume = intel_bsp_resume,
961 .c_x86_vendor = X86_VENDOR_INTEL,
962 };
963
964 cpu_dev_register(intel_cpu_dev);
965
Linux with added FPC-III support