arch/x86/kernel/early-quirks.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Various workarounds for chipset bugs.
   3    This code runs very early and can't use the regular PCI subsystem
   4    The entries are keyed to PCI bridges which usually identify chipsets
   5    uniquely.
   6    This is only for whole classes of chipsets with specific problems which
   7    need early invasive action (e.g. before the timers are initialized).
   8    Most PCI device specific workarounds can be done later and should be
   9    in standard PCI quirks
  10    Mainboard specific bugs should be handled by DMI entries.
  11    CPU specific bugs in setup.c */
  12
  13 #include <linux/pci.h>
  14 #include <linux/acpi.h>
  15 #include <linux/delay.h>
  16 #include <linux/pci_ids.h>
  17 #include <linux/bcma/bcma.h>
  18 #include <linux/bcma/bcma_regs.h>
  19 #include <linux/platform_data/x86/apple.h>
  20 #include <drm/i915_drm.h>
  21 #include <asm/pci-direct.h>
  22 #include <asm/dma.h>
  23 #include <asm/io_apic.h>
  24 #include <asm/apic.h>
  25 #include <asm/hpet.h>
  26 #include <asm/iommu.h>
  27 #include <asm/gart.h>
  28 #include <asm/irq_remapping.h>
  29 #include <asm/early_ioremap.h>
  30
  31 #define dev_err(msg)  pr_err("pci 0000:%02x:%02x.%d: %s", bus, slot, func, msg)
  32
  33 static void __init fix_hypertransport_config(int num, int slot, int func)
  34 {
  35         u32 htcfg;
  36         /*
  37          * we found a hypertransport bus
  38          * make sure that we are broadcasting
  39          * interrupts to all cpus on the ht bus
  40          * if we're using extended apic ids
  41          */
  42         htcfg = read_pci_config(num, slot, func, 0x68);
  43         if (htcfg & (1 << 18)) {
  44                 printk(KERN_INFO "Detected use of extended apic ids "
  45                                  "on hypertransport bus\n");
  46                 if ((htcfg & (1 << 17)) == 0) {
  47                         printk(KERN_INFO "Enabling hypertransport extended "
  48                                          "apic interrupt broadcast\n");
  49                         printk(KERN_INFO "Note this is a bios bug, "
  50                                          "please contact your hw vendor\n");
  51                         htcfg |= (1 << 17);
  52                         write_pci_config(num, slot, func, 0x68, htcfg);
  53                 }
  54         }
  55
  56
  57 }
  58
  59 static void __init via_bugs(int  num, int slot, int func)
  60 {
  61 #ifdef CONFIG_GART_IOMMU
  62         if ((max_pfn > MAX_DMA32_PFN ||  force_iommu) &&
  63             !gart_iommu_aperture_allowed) {
  64                 printk(KERN_INFO
  65                        "Looks like a VIA chipset. Disabling IOMMU."
  66                        " Override with iommu=allowed\n");
  67                 gart_iommu_aperture_disabled = 1;
  68         }
  69 #endif
  70 }
  71
  72 #ifdef CONFIG_ACPI
  73 #ifdef CONFIG_X86_IO_APIC
  74
  75 static int __init nvidia_hpet_check(struct acpi_table_header *header)
  76 {
  77         return 0;
  78 }
  79 #endif /* CONFIG_X86_IO_APIC */
  80 #endif /* CONFIG_ACPI */
  81
  82 static void __init nvidia_bugs(int num, int slot, int func)
  83 {
  84 #ifdef CONFIG_ACPI
  85 #ifdef CONFIG_X86_IO_APIC
  86         /*
  87          * Only applies to Nvidia root ports (bus 0) and not to
  88          * Nvidia graphics cards with PCI ports on secondary buses.
  89          */
  90         if (num)
  91                 return;
  92
  93         /*
  94          * All timer overrides on Nvidia are
  95          * wrong unless HPET is enabled.
  96          * Unfortunately that's not true on many Asus boards.
  97          * We don't know yet how to detect this automatically, but
  98          * at least allow a command line override.
  99          */
 100         if (acpi_use_timer_override)
 101                 return;
 102
 103         if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) {
 104                 acpi_skip_timer_override = 1;
 105                 printk(KERN_INFO "Nvidia board "
 106                        "detected. Ignoring ACPI "
 107                        "timer override.\n");
 108                 printk(KERN_INFO "If you got timer trouble "
 109                         "try acpi_use_timer_override\n");
 110         }
 111 #endif
 112 #endif
 113         /* RED-PEN skip them on mptables too? */
 114
 115 }
 116
 117 #if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
 118 static u32 __init ati_ixp4x0_rev(int num, int slot, int func)
 119 {
 120         u32 d;
 121         u8  b;
 122
 123         b = read_pci_config_byte(num, slot, func, 0xac);
 124         b &= ~(1<<5);
 125         write_pci_config_byte(num, slot, func, 0xac, b);
 126
 127         d = read_pci_config(num, slot, func, 0x70);
 128         d |= 1<<8;
 129         write_pci_config(num, slot, func, 0x70, d);
 130
 131         d = read_pci_config(num, slot, func, 0x8);
 132         d &= 0xff;
 133         return d;
 134 }
 135
 136 static void __init ati_bugs(int num, int slot, int func)
 137 {
 138         u32 d;
 139         u8  b;
 140
 141         if (acpi_use_timer_override)
 142                 return;
 143
 144         d = ati_ixp4x0_rev(num, slot, func);
 145         if (d  < 0x82)
 146                 acpi_skip_timer_override = 1;
 147         else {
 148                 /* check for IRQ0 interrupt swap */
 149                 outb(0x72, 0xcd6); b = inb(0xcd7);
 150                 if (!(b & 0x2))
 151                         acpi_skip_timer_override = 1;
 152         }
 153
 154         if (acpi_skip_timer_override) {
 155                 printk(KERN_INFO "SB4X0 revision 0x%x\n", d);
 156                 printk(KERN_INFO "Ignoring ACPI timer override.\n");
 157                 printk(KERN_INFO "If you got timer trouble "
 158                        "try acpi_use_timer_override\n");
 159         }
 160 }
 161
 162 static u32 __init ati_sbx00_rev(int num, int slot, int func)
 163 {
 164         u32 d;
 165
 166         d = read_pci_config(num, slot, func, 0x8);
 167         d &= 0xff;
 168
 169         return d;
 170 }
 171
 172 static void __init ati_bugs_contd(int num, int slot, int func)
 173 {
 174         u32 d, rev;
 175
 176         rev = ati_sbx00_rev(num, slot, func);
 177         if (rev >= 0x40)
 178                 acpi_fix_pin2_polarity = 1;
 179
 180         /*
 181          * SB600: revisions 0x11, 0x12, 0x13, 0x14, ...
 182          * SB700: revisions 0x39, 0x3a, ...
 183          * SB800: revisions 0x40, 0x41, ...
 184          */
 185         if (rev >= 0x39)
 186                 return;
 187
 188         if (acpi_use_timer_override)
 189                 return;
 190
 191         /* check for IRQ0 interrupt swap */
 192         d = read_pci_config(num, slot, func, 0x64);
 193         if (!(d & (1<<14)))
 194                 acpi_skip_timer_override = 1;
 195
 196         if (acpi_skip_timer_override) {
 197                 printk(KERN_INFO "SB600 revision 0x%x\n", rev);
 198                 printk(KERN_INFO "Ignoring ACPI timer override.\n");
 199                 printk(KERN_INFO "If you got timer trouble "
 200                        "try acpi_use_timer_override\n");
 201         }
 202 }
 203 #else
 204 static void __init ati_bugs(int num, int slot, int func)
 205 {
 206 }
 207
 208 static void __init ati_bugs_contd(int num, int slot, int func)
 209 {
 210 }
 211 #endif
 212
 213 static void __init intel_remapping_check(int num, int slot, int func)
 214 {
 215         u8 revision;
 216         u16 device;
 217
 218         device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
 219         revision = read_pci_config_byte(num, slot, func, PCI_REVISION_ID);
 220
 221         /*
 222          * Revision <= 13 of all triggering devices id in this quirk
 223          * have a problem draining interrupts when irq remapping is
 224          * enabled, and should be flagged as broken. Additionally
 225          * revision 0x22 of device id 0x3405 has this problem.
 226          */
 227         if (revision <= 0x13)
 228                 set_irq_remapping_broken();
 229         else if (device == 0x3405 && revision == 0x22)
 230                 set_irq_remapping_broken();
 231 }
 232
 233 /*
 234  * Systems with Intel graphics controllers set aside memory exclusively
 235  * for gfx driver use.  This memory is not marked in the E820 as reserved
 236  * or as RAM, and so is subject to overlap from E820 manipulation later
 237  * in the boot process.  On some systems, MMIO space is allocated on top,
 238  * despite the efforts of the "RAM buffer" approach, which simply rounds
 239  * memory boundaries up to 64M to try to catch space that may decode
 240  * as RAM and so is not suitable for MMIO.
 241  */
 242
 243 #define KB(x)   ((x) * 1024UL)
 244 #define MB(x)   (KB (KB (x)))
 245
 246 static size_t __init i830_tseg_size(void)
 247 {
 248         u8 esmramc = read_pci_config_byte(0, 0, 0, I830_ESMRAMC);
 249
 250         if (!(esmramc & TSEG_ENABLE))
 251                 return 0;
 252
 253         if (esmramc & I830_TSEG_SIZE_1M)
 254                 return MB(1);
 255         else
 256                 return KB(512);
 257 }
 258
 259 static size_t __init i845_tseg_size(void)
 260 {
 261         u8 esmramc = read_pci_config_byte(0, 0, 0, I845_ESMRAMC);
 262         u8 tseg_size = esmramc & I845_TSEG_SIZE_MASK;
 263
 264         if (!(esmramc & TSEG_ENABLE))
 265                 return 0;
 266
 267         switch (tseg_size) {
 268         case I845_TSEG_SIZE_512K:       return KB(512);
 269         case I845_TSEG_SIZE_1M:         return MB(1);
 270         default:
 271                 WARN(1, "Unknown ESMRAMC value: %x!\n", esmramc);
 272         }
 273         return 0;
 274 }
 275
 276 static size_t __init i85x_tseg_size(void)
 277 {
 278         u8 esmramc = read_pci_config_byte(0, 0, 0, I85X_ESMRAMC);
 279
 280         if (!(esmramc & TSEG_ENABLE))
 281                 return 0;
 282
 283         return MB(1);
 284 }
 285
 286 static size_t __init i830_mem_size(void)
 287 {
 288         return read_pci_config_byte(0, 0, 0, I830_DRB3) * MB(32);
 289 }
 290
 291 static size_t __init i85x_mem_size(void)
 292 {
 293         return read_pci_config_byte(0, 0, 1, I85X_DRB3) * MB(32);
 294 }
 295
 296 /*
 297  * On 830/845/85x the stolen memory base isn't available in any
 298  * register. We need to calculate it as TOM-TSEG_SIZE-stolen_size.
 299  */
 300 static phys_addr_t __init i830_stolen_base(int num, int slot, int func,
 301                                            size_t stolen_size)
 302 {
 303         return (phys_addr_t)i830_mem_size() - i830_tseg_size() - stolen_size;
 304 }
 305
 306 static phys_addr_t __init i845_stolen_base(int num, int slot, int func,
 307                                            size_t stolen_size)
 308 {
 309         return (phys_addr_t)i830_mem_size() - i845_tseg_size() - stolen_size;
 310 }
 311
 312 static phys_addr_t __init i85x_stolen_base(int num, int slot, int func,
 313                                            size_t stolen_size)
 314 {
 315         return (phys_addr_t)i85x_mem_size() - i85x_tseg_size() - stolen_size;
 316 }
 317
 318 static phys_addr_t __init i865_stolen_base(int num, int slot, int func,
 319                                            size_t stolen_size)
 320 {
 321         u16 toud = 0;
 322
 323         toud = read_pci_config_16(0, 0, 0, I865_TOUD);
 324
 325         return (phys_addr_t)(toud << 16) + i845_tseg_size();
 326 }
 327
 328 static phys_addr_t __init gen3_stolen_base(int num, int slot, int func,
 329                                            size_t stolen_size)
 330 {
 331         u32 bsm;
 332
 333         /* Almost universally we can find the Graphics Base of Stolen Memory
 334          * at register BSM (0x5c) in the igfx configuration space. On a few
 335          * (desktop) machines this is also mirrored in the bridge device at
 336          * different locations, or in the MCHBAR.
 337          */
 338         bsm = read_pci_config(num, slot, func, INTEL_BSM);
 339
 340         return (phys_addr_t)bsm & INTEL_BSM_MASK;
 341 }
 342
 343 static size_t __init i830_stolen_size(int num, int slot, int func)
 344 {
 345         u16 gmch_ctrl;
 346         u16 gms;
 347
 348         gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
 349         gms = gmch_ctrl & I830_GMCH_GMS_MASK;
 350
 351         switch (gms) {
 352         case I830_GMCH_GMS_STOLEN_512:  return KB(512);
 353         case I830_GMCH_GMS_STOLEN_1024: return MB(1);
 354         case I830_GMCH_GMS_STOLEN_8192: return MB(8);
 355         /* local memory isn't part of the normal address space */
 356         case I830_GMCH_GMS_LOCAL:       return 0;
 357         default:
 358                 WARN(1, "Unknown GMCH_CTRL value: %x!\n", gmch_ctrl);
 359         }
 360
 361         return 0;
 362 }
 363
 364 static size_t __init gen3_stolen_size(int num, int slot, int func)
 365 {
 366         u16 gmch_ctrl;
 367         u16 gms;
 368
 369         gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
 370         gms = gmch_ctrl & I855_GMCH_GMS_MASK;
 371
 372         switch (gms) {
 373         case I855_GMCH_GMS_STOLEN_1M:   return MB(1);
 374         case I855_GMCH_GMS_STOLEN_4M:   return MB(4);
 375         case I855_GMCH_GMS_STOLEN_8M:   return MB(8);
 376         case I855_GMCH_GMS_STOLEN_16M:  return MB(16);
 377         case I855_GMCH_GMS_STOLEN_32M:  return MB(32);
 378         case I915_GMCH_GMS_STOLEN_48M:  return MB(48);
 379         case I915_GMCH_GMS_STOLEN_64M:  return MB(64);
 380         case G33_GMCH_GMS_STOLEN_128M:  return MB(128);
 381         case G33_GMCH_GMS_STOLEN_256M:  return MB(256);
 382         case INTEL_GMCH_GMS_STOLEN_96M: return MB(96);
 383         case INTEL_GMCH_GMS_STOLEN_160M:return MB(160);
 384         case INTEL_GMCH_GMS_STOLEN_224M:return MB(224);
 385         case INTEL_GMCH_GMS_STOLEN_352M:return MB(352);
 386         default:
 387                 WARN(1, "Unknown GMCH_CTRL value: %x!\n", gmch_ctrl);
 388         }
 389
 390         return 0;
 391 }
 392
 393 static size_t __init gen6_stolen_size(int num, int slot, int func)
 394 {
 395         u16 gmch_ctrl;
 396         u16 gms;
 397
 398         gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
 399         gms = (gmch_ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK;
 400
 401         return (size_t)gms * MB(32);
 402 }
 403
 404 static size_t __init gen8_stolen_size(int num, int slot, int func)
 405 {
 406         u16 gmch_ctrl;
 407         u16 gms;
 408
 409         gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
 410         gms = (gmch_ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK;
 411
 412         return (size_t)gms * MB(32);
 413 }
 414
 415 static size_t __init chv_stolen_size(int num, int slot, int func)
 416 {
 417         u16 gmch_ctrl;
 418         u16 gms;
 419
 420         gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
 421         gms = (gmch_ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK;
 422
 423         /*
 424          * 0x0  to 0x10: 32MB increments starting at 0MB
 425          * 0x11 to 0x16: 4MB increments starting at 8MB
 426          * 0x17 to 0x1d: 4MB increments start at 36MB
 427          */
 428         if (gms < 0x11)
 429                 return (size_t)gms * MB(32);
 430         else if (gms < 0x17)
 431                 return (size_t)(gms - 0x11 + 2) * MB(4);
 432         else
 433                 return (size_t)(gms - 0x17 + 9) * MB(4);
 434 }
 435
 436 static size_t __init gen9_stolen_size(int num, int slot, int func)
 437 {
 438         u16 gmch_ctrl;
 439         u16 gms;
 440
 441         gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
 442         gms = (gmch_ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK;
 443
 444         /* 0x0  to 0xef: 32MB increments starting at 0MB */
 445         /* 0xf0 to 0xfe: 4MB increments starting at 4MB */
 446         if (gms < 0xf0)
 447                 return (size_t)gms * MB(32);
 448         else
 449                 return (size_t)(gms - 0xf0 + 1) * MB(4);
 450 }
 451
 452 struct intel_early_ops {
 453         size_t (*stolen_size)(int num, int slot, int func);
 454         phys_addr_t (*stolen_base)(int num, int slot, int func, size_t size);
 455 };
 456
 457 static const struct intel_early_ops i830_early_ops __initconst = {
 458         .stolen_base = i830_stolen_base,
 459         .stolen_size = i830_stolen_size,
 460 };
 461
 462 static const struct intel_early_ops i845_early_ops __initconst = {
 463         .stolen_base = i845_stolen_base,
 464         .stolen_size = i830_stolen_size,
 465 };
 466
 467 static const struct intel_early_ops i85x_early_ops __initconst = {
 468         .stolen_base = i85x_stolen_base,
 469         .stolen_size = gen3_stolen_size,
 470 };
 471
 472 static const struct intel_early_ops i865_early_ops __initconst = {
 473         .stolen_base = i865_stolen_base,
 474         .stolen_size = gen3_stolen_size,
 475 };
 476
 477 static const struct intel_early_ops gen3_early_ops __initconst = {
 478         .stolen_base = gen3_stolen_base,
 479         .stolen_size = gen3_stolen_size,
 480 };
 481
 482 static const struct intel_early_ops gen6_early_ops __initconst = {
 483         .stolen_base = gen3_stolen_base,
 484         .stolen_size = gen6_stolen_size,
 485 };
 486
 487 static const struct intel_early_ops gen8_early_ops __initconst = {
 488         .stolen_base = gen3_stolen_base,
 489         .stolen_size = gen8_stolen_size,
 490 };
 491
 492 static const struct intel_early_ops gen9_early_ops __initconst = {
 493         .stolen_base = gen3_stolen_base,
 494         .stolen_size = gen9_stolen_size,
 495 };
 496
 497 static const struct intel_early_ops chv_early_ops __initconst = {
 498         .stolen_base = gen3_stolen_base,
 499         .stolen_size = chv_stolen_size,
 500 };
 501
 502 static const struct pci_device_id intel_early_ids[] __initconst = {
 503         INTEL_I830_IDS(&i830_early_ops),
 504         INTEL_I845G_IDS(&i845_early_ops),
 505         INTEL_I85X_IDS(&i85x_early_ops),
 506         INTEL_I865G_IDS(&i865_early_ops),
 507         INTEL_I915G_IDS(&gen3_early_ops),
 508         INTEL_I915GM_IDS(&gen3_early_ops),
 509         INTEL_I945G_IDS(&gen3_early_ops),
 510         INTEL_I945GM_IDS(&gen3_early_ops),
 511         INTEL_VLV_IDS(&gen6_early_ops),
 512         INTEL_PINEVIEW_IDS(&gen3_early_ops),
 513         INTEL_I965G_IDS(&gen3_early_ops),
 514         INTEL_G33_IDS(&gen3_early_ops),
 515         INTEL_I965GM_IDS(&gen3_early_ops),
 516         INTEL_GM45_IDS(&gen3_early_ops),
 517         INTEL_G45_IDS(&gen3_early_ops),
 518         INTEL_IRONLAKE_D_IDS(&gen3_early_ops),
 519         INTEL_IRONLAKE_M_IDS(&gen3_early_ops),
 520         INTEL_SNB_D_IDS(&gen6_early_ops),
 521         INTEL_SNB_M_IDS(&gen6_early_ops),
 522         INTEL_IVB_M_IDS(&gen6_early_ops),
 523         INTEL_IVB_D_IDS(&gen6_early_ops),
 524         INTEL_HSW_IDS(&gen6_early_ops),
 525         INTEL_BDW_IDS(&gen8_early_ops),
 526         INTEL_CHV_IDS(&chv_early_ops),
 527         INTEL_SKL_IDS(&gen9_early_ops),
 528         INTEL_BXT_IDS(&gen9_early_ops),
 529         INTEL_KBL_IDS(&gen9_early_ops),
 530         INTEL_CFL_IDS(&gen9_early_ops),
 531         INTEL_GLK_IDS(&gen9_early_ops),
 532         INTEL_CNL_IDS(&gen9_early_ops),
 533 };
 534
 535 static void __init
 536 intel_graphics_stolen(int num, int slot, int func,
 537                       const struct intel_early_ops *early_ops)
 538 {
 539         phys_addr_t base, end;
 540         size_t size;
 541
 542         size = early_ops->stolen_size(num, slot, func);
 543         base = early_ops->stolen_base(num, slot, func, size);
 544
 545         if (!size || !base)
 546                 return;
 547
 548         end = base + size - 1;
 549         printk(KERN_INFO "Reserving Intel graphics memory at %pa-%pa\n",
 550                &base, &end);
 551
 552         /* Mark this space as reserved */
 553         e820__range_add(base, size, E820_TYPE_RESERVED);
 554         e820__update_table(e820_table);
 555 }
 556
 557 static void __init intel_graphics_quirks(int num, int slot, int func)
 558 {
 559         const struct intel_early_ops *early_ops;
 560         u16 device;
 561         int i;
 562
 563         device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
 564
 565         for (i = 0; i < ARRAY_SIZE(intel_early_ids); i++) {
 566                 kernel_ulong_t driver_data = intel_early_ids[i].driver_data;
 567
 568                 if (intel_early_ids[i].device != device)
 569                         continue;
 570
 571                 early_ops = (typeof(early_ops))driver_data;
 572
 573                 intel_graphics_stolen(num, slot, func, early_ops);
 574
 575                 return;
 576         }
 577 }
 578
 579 static void __init force_disable_hpet(int num, int slot, int func)
 580 {
 581 #ifdef CONFIG_HPET_TIMER
 582         boot_hpet_disable = true;
 583         pr_info("x86/hpet: Will disable the HPET for this platform because it's not reliable\n");
 584 #endif
 585 }
 586
 587 #define BCM4331_MMIO_SIZE       16384
 588 #define BCM4331_PM_CAP          0x40
 589 #define bcma_aread32(reg)       ioread32(mmio + 1 * BCMA_CORE_SIZE + reg)
 590 #define bcma_awrite32(reg, val) iowrite32(val, mmio + 1 * BCMA_CORE_SIZE + reg)
 591
 592 static void __init apple_airport_reset(int bus, int slot, int func)
 593 {
 594         void __iomem *mmio;
 595         u16 pmcsr;
 596         u64 addr;
 597         int i;
 598
 599         if (!x86_apple_machine)
 600                 return;
 601
 602         /* Card may have been put into PCI_D3hot by grub quirk */
 603         pmcsr = read_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL);
 604
 605         if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) {
 606                 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
 607                 write_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL, pmcsr);
 608                 mdelay(10);
 609
 610                 pmcsr = read_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL);
 611                 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) {
 612                         dev_err("Cannot power up Apple AirPort card\n");
 613                         return;
 614                 }
 615         }
 616
 617         addr  =      read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0);
 618         addr |= (u64)read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_1) << 32;
 619         addr &= PCI_BASE_ADDRESS_MEM_MASK;
 620
 621         mmio = early_ioremap(addr, BCM4331_MMIO_SIZE);
 622         if (!mmio) {
 623                 dev_err("Cannot iomap Apple AirPort card\n");
 624                 return;
 625         }
 626
 627         pr_info("Resetting Apple AirPort card (left enabled by EFI)\n");
 628
 629         for (i = 0; bcma_aread32(BCMA_RESET_ST) && i < 30; i++)
 630                 udelay(10);
 631
 632         bcma_awrite32(BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
 633         bcma_aread32(BCMA_RESET_CTL);
 634         udelay(1);
 635
 636         bcma_awrite32(BCMA_RESET_CTL, 0);
 637         bcma_aread32(BCMA_RESET_CTL);
 638         udelay(10);
 639
 640         early_iounmap(mmio, BCM4331_MMIO_SIZE);
 641 }
 642
 643 #define QFLAG_APPLY_ONCE        0x1
 644 #define QFLAG_APPLIED           0x2
 645 #define QFLAG_DONE              (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
 646 struct chipset {
 647         u32 vendor;
 648         u32 device;
 649         u32 class;
 650         u32 class_mask;
 651         u32 flags;
 652         void (*f)(int num, int slot, int func);
 653 };
 654
 655 static struct chipset early_qrk[] __initdata = {
 656         { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
 657           PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
 658         { PCI_VENDOR_ID_VIA, PCI_ANY_ID,
 659           PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
 660         { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
 661           PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
 662         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
 663           PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
 664         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
 665           PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
 666         { PCI_VENDOR_ID_INTEL, 0x3403, PCI_CLASS_BRIDGE_HOST,
 667           PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
 668         { PCI_VENDOR_ID_INTEL, 0x3405, PCI_CLASS_BRIDGE_HOST,
 669           PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
 670         { PCI_VENDOR_ID_INTEL, 0x3406, PCI_CLASS_BRIDGE_HOST,
 671           PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
 672         { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, PCI_ANY_ID,
 673           QFLAG_APPLY_ONCE, intel_graphics_quirks },
 674         /*
 675          * HPET on the current version of the Baytrail platform has accuracy
 676          * problems: it will halt in deep idle state - so we disable it.
 677          *
 678          * More details can be found in section 18.10.1.3 of the datasheet:
 679          *
 680          *    http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-z8000-datasheet-vol-1.pdf
 681          */
 682         { PCI_VENDOR_ID_INTEL, 0x0f00,
 683                 PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet},
 684         { PCI_VENDOR_ID_BROADCOM, 0x4331,
 685           PCI_CLASS_NETWORK_OTHER, PCI_ANY_ID, 0, apple_airport_reset},
 686         {}
 687 };
 688
 689 static void __init early_pci_scan_bus(int bus);
 690
 691 /**
 692  * check_dev_quirk - apply early quirks to a given PCI device
 693  * @num: bus number
 694  * @slot: slot number
 695  * @func: PCI function
 696  *
 697  * Check the vendor & device ID against the early quirks table.
 698  *
 699  * If the device is single function, let early_pci_scan_bus() know so we don't
 700  * poke at this device again.
 701  */
 702 static int __init check_dev_quirk(int num, int slot, int func)
 703 {
 704         u16 class;
 705         u16 vendor;
 706         u16 device;
 707         u8 type;
 708         u8 sec;
 709         int i;
 710
 711         class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE);
 712
 713         if (class == 0xffff)
 714                 return -1; /* no class, treat as single function */
 715
 716         vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID);
 717
 718         device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
 719
 720         for (i = 0; early_qrk[i].f != NULL; i++) {
 721                 if (((early_qrk[i].vendor == PCI_ANY_ID) ||
 722                         (early_qrk[i].vendor == vendor)) &&
 723                         ((early_qrk[i].device == PCI_ANY_ID) ||
 724                         (early_qrk[i].device == device)) &&
 725                         (!((early_qrk[i].class ^ class) &
 726                             early_qrk[i].class_mask))) {
 727                                 if ((early_qrk[i].flags &
 728                                      QFLAG_DONE) != QFLAG_DONE)
 729                                         early_qrk[i].f(num, slot, func);
 730                                 early_qrk[i].flags |= QFLAG_APPLIED;
 731                         }
 732         }
 733
 734         type = read_pci_config_byte(num, slot, func,
 735                                     PCI_HEADER_TYPE);
 736
 737         if ((type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
 738                 sec = read_pci_config_byte(num, slot, func, PCI_SECONDARY_BUS);
 739                 if (sec > num)
 740                         early_pci_scan_bus(sec);
 741         }
 742
 743         if (!(type & 0x80))
 744                 return -1;
 745
 746         return 0;
 747 }
 748
 749 static void __init early_pci_scan_bus(int bus)
 750 {
 751         int slot, func;
 752
 753         /* Poor man's PCI discovery */
 754         for (slot = 0; slot < 32; slot++)
 755                 for (func = 0; func < 8; func++) {
 756                         /* Only probe function 0 on single fn devices */
 757                         if (check_dev_quirk(bus, slot, func))
 758                                 break;
 759                 }
 760 }
 761
 762 void __init early_quirks(void)
 763 {
 764         if (!early_pci_allowed())
 765                 return;
 766
 767         early_pci_scan_bus(0);
 768 }