mm: fix exec activate_mm vs TLB shootdown and lazy tlb switching race
[linux/fpc-iii.git] / arch / x86 / kernel / process_32.c
blobdf6bb5f8ab2a4ee352e81c9520b819502a1408c9
1 /*
2 * Copyright (C) 1995 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * Gareth Hughes <gareth@valinux.com>, May 2000
6 */
8 /*
9 * This file handles the architecture-dependent parts of process handling..
12 #include <linux/cpu.h>
13 #include <linux/errno.h>
14 #include <linux/sched.h>
15 #include <linux/sched/task.h>
16 #include <linux/sched/task_stack.h>
17 #include <linux/fs.h>
18 #include <linux/kernel.h>
19 #include <linux/mm.h>
20 #include <linux/elfcore.h>
21 #include <linux/smp.h>
22 #include <linux/stddef.h>
23 #include <linux/slab.h>
24 #include <linux/vmalloc.h>
25 #include <linux/user.h>
26 #include <linux/interrupt.h>
27 #include <linux/delay.h>
28 #include <linux/reboot.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/export.h>
31 #include <linux/kallsyms.h>
32 #include <linux/ptrace.h>
33 #include <linux/personality.h>
34 #include <linux/percpu.h>
35 #include <linux/prctl.h>
36 #include <linux/ftrace.h>
37 #include <linux/uaccess.h>
38 #include <linux/io.h>
39 #include <linux/kdebug.h>
40 #include <linux/syscalls.h>
42 #include <asm/pgtable.h>
43 #include <asm/ldt.h>
44 #include <asm/processor.h>
45 #include <asm/fpu/internal.h>
46 #include <asm/desc.h>
47 #ifdef CONFIG_MATH_EMULATION
48 #include <asm/math_emu.h>
49 #endif
51 #include <linux/err.h>
53 #include <asm/tlbflush.h>
54 #include <asm/cpu.h>
55 #include <asm/syscalls.h>
56 #include <asm/debugreg.h>
57 #include <asm/switch_to.h>
58 #include <asm/vm86.h>
59 #include <asm/intel_rdt_sched.h>
60 #include <asm/proto.h>
62 #include "process.h"
64 void __show_regs(struct pt_regs *regs, int all)
66 unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
67 unsigned long d0, d1, d2, d3, d6, d7;
68 unsigned long sp;
69 unsigned short ss, gs;
71 if (user_mode(regs)) {
72 sp = regs->sp;
73 ss = regs->ss;
74 gs = get_user_gs(regs);
75 } else {
76 sp = kernel_stack_pointer(regs);
77 savesegment(ss, ss);
78 savesegment(gs, gs);
81 printk(KERN_DEFAULT "EIP: %pS\n", (void *)regs->ip);
82 printk(KERN_DEFAULT "EFLAGS: %08lx CPU: %d\n", regs->flags,
83 raw_smp_processor_id());
85 printk(KERN_DEFAULT "EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
86 regs->ax, regs->bx, regs->cx, regs->dx);
87 printk(KERN_DEFAULT "ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
88 regs->si, regs->di, regs->bp, sp);
89 printk(KERN_DEFAULT " DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
90 (u16)regs->ds, (u16)regs->es, (u16)regs->fs, gs, ss);
92 if (!all)
93 return;
95 cr0 = read_cr0();
96 cr2 = read_cr2();
97 cr3 = __read_cr3();
98 cr4 = __read_cr4();
99 printk(KERN_DEFAULT "CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
100 cr0, cr2, cr3, cr4);
102 get_debugreg(d0, 0);
103 get_debugreg(d1, 1);
104 get_debugreg(d2, 2);
105 get_debugreg(d3, 3);
106 get_debugreg(d6, 6);
107 get_debugreg(d7, 7);
109 /* Only print out debug registers if they are in their non-default state. */
110 if ((d0 == 0) && (d1 == 0) && (d2 == 0) && (d3 == 0) &&
111 (d6 == DR6_RESERVED) && (d7 == 0x400))
112 return;
114 printk(KERN_DEFAULT "DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
115 d0, d1, d2, d3);
116 printk(KERN_DEFAULT "DR6: %08lx DR7: %08lx\n",
117 d6, d7);
120 void release_thread(struct task_struct *dead_task)
122 BUG_ON(dead_task->mm);
123 release_vm86_irqs(dead_task);
126 int copy_thread_tls(unsigned long clone_flags, unsigned long sp,
127 unsigned long arg, struct task_struct *p, unsigned long tls)
129 struct pt_regs *childregs = task_pt_regs(p);
130 struct fork_frame *fork_frame = container_of(childregs, struct fork_frame, regs);
131 struct inactive_task_frame *frame = &fork_frame->frame;
132 struct task_struct *tsk;
133 int err;
136 * For a new task use the RESET flags value since there is no before.
137 * All the status flags are zero; DF and all the system flags must also
138 * be 0, specifically IF must be 0 because we context switch to the new
139 * task with interrupts disabled.
141 frame->flags = X86_EFLAGS_FIXED;
142 frame->bp = 0;
143 frame->ret_addr = (unsigned long) ret_from_fork;
144 p->thread.sp = (unsigned long) fork_frame;
145 p->thread.sp0 = (unsigned long) (childregs+1);
146 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
148 if (unlikely(p->flags & PF_KTHREAD)) {
149 /* kernel thread */
150 memset(childregs, 0, sizeof(struct pt_regs));
151 frame->bx = sp; /* function */
152 frame->di = arg;
153 p->thread.io_bitmap_ptr = NULL;
154 return 0;
156 frame->bx = 0;
157 *childregs = *current_pt_regs();
158 childregs->ax = 0;
159 if (sp)
160 childregs->sp = sp;
162 task_user_gs(p) = get_user_gs(current_pt_regs());
164 p->thread.io_bitmap_ptr = NULL;
165 tsk = current;
166 err = -ENOMEM;
168 if (unlikely(test_tsk_thread_flag(tsk, TIF_IO_BITMAP))) {
169 p->thread.io_bitmap_ptr = kmemdup(tsk->thread.io_bitmap_ptr,
170 IO_BITMAP_BYTES, GFP_KERNEL);
171 if (!p->thread.io_bitmap_ptr) {
172 p->thread.io_bitmap_max = 0;
173 return -ENOMEM;
175 set_tsk_thread_flag(p, TIF_IO_BITMAP);
178 err = 0;
181 * Set a new TLS for the child thread?
183 if (clone_flags & CLONE_SETTLS)
184 err = do_set_thread_area(p, -1,
185 (struct user_desc __user *)tls, 0);
187 if (err && p->thread.io_bitmap_ptr) {
188 kfree(p->thread.io_bitmap_ptr);
189 p->thread.io_bitmap_max = 0;
191 return err;
194 void
195 start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
197 set_user_gs(regs, 0);
198 regs->fs = 0;
199 regs->ds = __USER_DS;
200 regs->es = __USER_DS;
201 regs->ss = __USER_DS;
202 regs->cs = __USER_CS;
203 regs->ip = new_ip;
204 regs->sp = new_sp;
205 regs->flags = X86_EFLAGS_IF;
206 force_iret();
208 EXPORT_SYMBOL_GPL(start_thread);
212 * switch_to(x,y) should switch tasks from x to y.
214 * We fsave/fwait so that an exception goes off at the right time
215 * (as a call from the fsave or fwait in effect) rather than to
216 * the wrong process. Lazy FP saving no longer makes any sense
217 * with modern CPU's, and this simplifies a lot of things (SMP
218 * and UP become the same).
220 * NOTE! We used to use the x86 hardware context switching. The
221 * reason for not using it any more becomes apparent when you
222 * try to recover gracefully from saved state that is no longer
223 * valid (stale segment register values in particular). With the
224 * hardware task-switch, there is no way to fix up bad state in
225 * a reasonable manner.
227 * The fact that Intel documents the hardware task-switching to
228 * be slow is a fairly red herring - this code is not noticeably
229 * faster. However, there _is_ some room for improvement here,
230 * so the performance issues may eventually be a valid point.
231 * More important, however, is the fact that this allows us much
232 * more flexibility.
234 * The return value (in %ax) will be the "prev" task after
235 * the task-switch, and shows up in ret_from_fork in entry.S,
236 * for example.
238 __visible __notrace_funcgraph struct task_struct *
239 __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
241 struct thread_struct *prev = &prev_p->thread,
242 *next = &next_p->thread;
243 struct fpu *prev_fpu = &prev->fpu;
244 struct fpu *next_fpu = &next->fpu;
245 int cpu = smp_processor_id();
247 /* never put a printk in __switch_to... printk() calls wake_up*() indirectly */
249 switch_fpu_prepare(prev_fpu, cpu);
252 * Save away %gs. No need to save %fs, as it was saved on the
253 * stack on entry. No need to save %es and %ds, as those are
254 * always kernel segments while inside the kernel. Doing this
255 * before setting the new TLS descriptors avoids the situation
256 * where we temporarily have non-reloadable segments in %fs
257 * and %gs. This could be an issue if the NMI handler ever
258 * used %fs or %gs (it does not today), or if the kernel is
259 * running inside of a hypervisor layer.
261 lazy_save_gs(prev->gs);
264 * Load the per-thread Thread-Local Storage descriptor.
266 load_TLS(next, cpu);
269 * Restore IOPL if needed. In normal use, the flags restore
270 * in the switch assembly will handle this. But if the kernel
271 * is running virtualized at a non-zero CPL, the popf will
272 * not restore flags, so it must be done in a separate step.
274 if (get_kernel_rpl() && unlikely(prev->iopl != next->iopl))
275 set_iopl_mask(next->iopl);
277 switch_to_extra(prev_p, next_p);
280 * Leave lazy mode, flushing any hypercalls made here.
281 * This must be done before restoring TLS segments so
282 * the GDT and LDT are properly updated, and must be
283 * done before fpu__restore(), so the TS bit is up
284 * to date.
286 arch_end_context_switch(next_p);
289 * Reload esp0 and cpu_current_top_of_stack. This changes
290 * current_thread_info(). Refresh the SYSENTER configuration in
291 * case prev or next is vm86.
293 update_sp0(next_p);
294 refresh_sysenter_cs(next);
295 this_cpu_write(cpu_current_top_of_stack,
296 (unsigned long)task_stack_page(next_p) +
297 THREAD_SIZE);
300 * Restore %gs if needed (which is common)
302 if (prev->gs | next->gs)
303 lazy_load_gs(next->gs);
305 switch_fpu_finish(next_fpu, cpu);
307 this_cpu_write(current_task, next_p);
309 /* Load the Intel cache allocation PQR MSR. */
310 intel_rdt_sched_in();
312 return prev_p;
315 SYSCALL_DEFINE2(arch_prctl, int, option, unsigned long, arg2)
317 return do_arch_prctl_common(current, option, arg2);