| blob | 7043a4f0e98ab258c06116e675bac65d19080a7e |
1 /*
2 * Low-level PCI config space access for OLPC systems who lack the VSA
3 * PCI virtualization software.
4 *
5 * Copyright © 2006 Advanced Micro Devices, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * The AMD Geode chipset (ie: GX2 processor, cs5536 I/O companion device)
13 * has some I/O functions (display, southbridge, sound, USB HCIs, etc)
14 * that more or less behave like PCI devices, but the hardware doesn't
15 * directly implement the PCI configuration space headers. AMD provides
16 * "VSA" (Virtual System Architecture) software that emulates PCI config
17 * space for these devices, by trapping I/O accesses to PCI config register
18 * (CF8/CFC) and running some code in System Management Mode interrupt state.
19 * On the OLPC platform, we don't want to use that VSA code because
20 * (a) it slows down suspend/resume, and (b) recompiling it requires special
21 * compilers that are hard to get. So instead of letting the complex VSA
22 * code simulate the PCI config registers for the on-chip devices, we
23 * just simulate them the easy way, by inserting the code into the
24 * pci_write_config and pci_read_config path. Most of the config registers
25 * are read-only anyway, so the bulk of the simulation is just table lookup.
26 */
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <asm/olpc.h>
31 #include <asm/geode.h>
32 #include <asm/pci_x86.h>
34 /*
35 * In the tables below, the first two line (8 longwords) are the
36 * size masks that are used when the higher level PCI code determines
37 * the size of the region by writing ~0 to a base address register
38 * and reading back the result.
39 *
40 * The following lines are the values that are read during normal
41 * PCI config access cycles, i.e. not after just having written
42 * ~0 to a base address register.
43 */
56 };
69 };
82 };
95 };
108 };
122 };
135 };
146 44 is mask 8103 (power control) */
149 };
160 mask 8103 (power control) */
161 #if 0
163 #endif
166 61 FLADJ (R/W), PORTWAKECAP */
167 };
178 {
181 }
184 {
187 /*
188 * This is a little bit tricky. The header maps consist of
189 * 0x20 bytes of size masks, followed by 0x70 bytes of header data.
190 * In the normal case, when not probing a BAR's size, we want
191 * to access the header data, so we add 0x20 to the reg offset,
192 * thus skipping the size mask area.
193 * In the BAR probing case, we want to access the size mask for
194 * the BAR, so we subtract 0x10 (the config header offset for
195 * BAR0), and don't skip the size mask area.
196 */
202 }
206 {
211 /* Use the hardware mechanism for non-simulated devices */
215 /*
216 * No device has config registers past 0x70, so we save table space
217 * by not storing entries for the nonexistent registers
218 */
247 }
248 }
261 }
264 }
268 {
271 /* Use the hardware mechanism for non-simulated devices */
275 /* XXX we may want to extend this to simulate EHCI power management */
277 /*
278 * Mostly we just discard writes, but if the write is a size probe
279 * (i.e. writing ~0 to a BAR), we remember it and arrange to return
280 * the appropriate size mask on the next read. This is cheating
281 * to some extent, because it depends on the fact that the next
282 * access after such a write will always be a read to the same BAR.
283 */
286 /* write is to a BAR */
290 /*
291 * No warning on writes to ROM BAR, CMD, LATENCY_TIMER,
292 * CACHE_LINE_SIZE, or PM registers.
293 */
299 }
302 }
307 };
310 {
315 }