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mm: fix exec activate_mm vs TLB shootdown and lazy tlb switching race
[linux/fpc-iii.git] / arch / xtensa / kernel / ptrace.c
blob7c3ed7d78075477c7f725d0982ba2f96a8863330
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2001 - 2007 Tensilica Inc.
7 *
8 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
9 * Chris Zankel <chris@zankel.net>
10 * Scott Foehner<sfoehner@yahoo.com>,
11 * Kevin Chea
12 * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
13 */
14
15 #include <linux/errno.h>
16 #include <linux/hw_breakpoint.h>
17 #include <linux/kernel.h>
18 #include <linux/mm.h>
19 #include <linux/perf_event.h>
20 #include <linux/ptrace.h>
21 #include <linux/sched.h>
22 #include <linux/sched/task_stack.h>
23 #include <linux/security.h>
24 #include <linux/signal.h>
25 #include <linux/smp.h>
26 #include <linux/tracehook.h>
27 #include <linux/uaccess.h>
28
29 #include <asm/coprocessor.h>
30 #include <asm/elf.h>
31 #include <asm/page.h>
32 #include <asm/pgtable.h>
33 #include <asm/ptrace.h>
34
35
36 void user_enable_single_step(struct task_struct *child)
37 {
38 child->ptrace |= PT_SINGLESTEP;
39 }
40
41 void user_disable_single_step(struct task_struct *child)
42 {
43 child->ptrace &= ~PT_SINGLESTEP;
44 }
45
46 /*
47 * Called by kernel/ptrace.c when detaching to disable single stepping.
48 */
49
50 void ptrace_disable(struct task_struct *child)
51 {
52 /* Nothing to do.. */
53 }
54
55 static int ptrace_getregs(struct task_struct *child, void __user *uregs)
56 {
57 struct pt_regs *regs = task_pt_regs(child);
58 xtensa_gregset_t __user *gregset = uregs;
59 unsigned long wb = regs->windowbase;
60 int i;
61
62 if (!access_ok(VERIFY_WRITE, uregs, sizeof(xtensa_gregset_t)))
63 return -EIO;
64
65 __put_user(regs->pc, &gregset->pc);
66 __put_user(regs->ps & ~(1 << PS_EXCM_BIT), &gregset->ps);
67 __put_user(regs->lbeg, &gregset->lbeg);
68 __put_user(regs->lend, &gregset->lend);
69 __put_user(regs->lcount, &gregset->lcount);
70 __put_user(regs->windowstart, &gregset->windowstart);
71 __put_user(regs->windowbase, &gregset->windowbase);
72 __put_user(regs->threadptr, &gregset->threadptr);
73
74 for (i = 0; i < XCHAL_NUM_AREGS; i++)
75 __put_user(regs->areg[i],
76 gregset->a + ((wb * 4 + i) % XCHAL_NUM_AREGS));
77
78 return 0;
79 }
80
81 static int ptrace_setregs(struct task_struct *child, void __user *uregs)
82 {
83 struct pt_regs *regs = task_pt_regs(child);
84 xtensa_gregset_t *gregset = uregs;
85 const unsigned long ps_mask = PS_CALLINC_MASK | PS_OWB_MASK;
86 unsigned long ps;
87 unsigned long wb, ws;
88
89 if (!access_ok(VERIFY_WRITE, uregs, sizeof(xtensa_gregset_t)))
90 return -EIO;
91
92 __get_user(regs->pc, &gregset->pc);
93 __get_user(ps, &gregset->ps);
94 __get_user(regs->lbeg, &gregset->lbeg);
95 __get_user(regs->lend, &gregset->lend);
96 __get_user(regs->lcount, &gregset->lcount);
97 __get_user(ws, &gregset->windowstart);
98 __get_user(wb, &gregset->windowbase);
99 __get_user(regs->threadptr, &gregset->threadptr);
100
101 regs->ps = (regs->ps & ~ps_mask) | (ps & ps_mask) | (1 << PS_EXCM_BIT);
102
103 if (wb >= XCHAL_NUM_AREGS / 4)
104 return -EFAULT;
105
106 if (wb != regs->windowbase || ws != regs->windowstart) {
107 unsigned long rotws, wmask;
108
109 rotws = (((ws | (ws << WSBITS)) >> wb) &
110 ((1 << WSBITS) - 1)) & ~1;
111 wmask = ((rotws ? WSBITS + 1 - ffs(rotws) : 0) << 4) |
112 (rotws & 0xF) | 1;
113 regs->windowbase = wb;
114 regs->windowstart = ws;
115 regs->wmask = wmask;
116 }
117
118 if (wb != 0 && __copy_from_user(regs->areg + XCHAL_NUM_AREGS - wb * 4,
119 gregset->a, wb * 16))
120 return -EFAULT;
121
122 if (__copy_from_user(regs->areg, gregset->a + wb * 4,
123 (WSBITS - wb) * 16))
124 return -EFAULT;
125
126 return 0;
127 }
128
129
130 #if XTENSA_HAVE_COPROCESSORS
131 #define CP_OFFSETS(cp) \
132 { \
133 .elf_xtregs_offset = offsetof(elf_xtregs_t, cp), \
134 .ti_offset = offsetof(struct thread_info, xtregs_cp.cp), \
135 .sz = sizeof(xtregs_ ## cp ## _t), \
136 }
137
138 static const struct {
139 size_t elf_xtregs_offset;
140 size_t ti_offset;
141 size_t sz;
142 } cp_offsets[] = {
143 CP_OFFSETS(cp0),
144 CP_OFFSETS(cp1),
145 CP_OFFSETS(cp2),
146 CP_OFFSETS(cp3),
147 CP_OFFSETS(cp4),
148 CP_OFFSETS(cp5),
149 CP_OFFSETS(cp6),
150 CP_OFFSETS(cp7),
151 };
152 #endif
153
154 static int ptrace_getxregs(struct task_struct *child, void __user *uregs)
155 {
156 struct pt_regs *regs = task_pt_regs(child);
157 struct thread_info *ti = task_thread_info(child);
158 elf_xtregs_t __user *xtregs = uregs;
159 int ret = 0;
160 int i __maybe_unused;
161
162 if (!access_ok(VERIFY_WRITE, uregs, sizeof(elf_xtregs_t)))
163 return -EIO;
164
165 #if XTENSA_HAVE_COPROCESSORS
166 /* Flush all coprocessor registers to memory. */
167 coprocessor_flush_all(ti);
168
169 for (i = 0; i < ARRAY_SIZE(cp_offsets); ++i)
170 ret |= __copy_to_user((char __user *)xtregs +
171 cp_offsets[i].elf_xtregs_offset,
172 (const char *)ti +
173 cp_offsets[i].ti_offset,
174 cp_offsets[i].sz);
175 #endif
176 ret |= __copy_to_user(&xtregs->opt, &regs->xtregs_opt,
177 sizeof(xtregs->opt));
178 ret |= __copy_to_user(&xtregs->user,&ti->xtregs_user,
179 sizeof(xtregs->user));
180
181 return ret ? -EFAULT : 0;
182 }
183
184 static int ptrace_setxregs(struct task_struct *child, void __user *uregs)
185 {
186 struct thread_info *ti = task_thread_info(child);
187 struct pt_regs *regs = task_pt_regs(child);
188 elf_xtregs_t *xtregs = uregs;
189 int ret = 0;
190 int i __maybe_unused;
191
192 if (!access_ok(VERIFY_READ, uregs, sizeof(elf_xtregs_t)))
193 return -EFAULT;
194
195 #if XTENSA_HAVE_COPROCESSORS
196 /* Flush all coprocessors before we overwrite them. */
197 coprocessor_flush_all(ti);
198 coprocessor_release_all(ti);
199
200 for (i = 0; i < ARRAY_SIZE(cp_offsets); ++i)
201 ret |= __copy_from_user((char *)ti + cp_offsets[i].ti_offset,
202 (const char __user *)xtregs +
203 cp_offsets[i].elf_xtregs_offset,
204 cp_offsets[i].sz);
205 #endif
206 ret |= __copy_from_user(&regs->xtregs_opt, &xtregs->opt,
207 sizeof(xtregs->opt));
208 ret |= __copy_from_user(&ti->xtregs_user, &xtregs->user,
209 sizeof(xtregs->user));
210
211 return ret ? -EFAULT : 0;
212 }
213
214 static int ptrace_peekusr(struct task_struct *child, long regno,
215 long __user *ret)
216 {
217 struct pt_regs *regs;
218 unsigned long tmp;
219
220 regs = task_pt_regs(child);
221 tmp = 0; /* Default return value. */
222
223 switch(regno) {
224 case REG_AR_BASE ... REG_AR_BASE + XCHAL_NUM_AREGS - 1:
225 tmp = regs->areg[regno - REG_AR_BASE];
226 break;
227
228 case REG_A_BASE ... REG_A_BASE + 15:
229 tmp = regs->areg[regno - REG_A_BASE];
230 break;
231
232 case REG_PC:
233 tmp = regs->pc;
234 break;
235
236 case REG_PS:
237 /* Note: PS.EXCM is not set while user task is running;
238 * its being set in regs is for exception handling
239 * convenience.
240 */
241 tmp = (regs->ps & ~(1 << PS_EXCM_BIT));
242 break;
243
244 case REG_WB:
245 break; /* tmp = 0 */
246
247 case REG_WS:
248 {
249 unsigned long wb = regs->windowbase;
250 unsigned long ws = regs->windowstart;
251 tmp = ((ws >> wb) | (ws << (WSBITS - wb))) &
252 ((1 << WSBITS) - 1);
253 break;
254 }
255 case REG_LBEG:
256 tmp = regs->lbeg;
257 break;
258
259 case REG_LEND:
260 tmp = regs->lend;
261 break;
262
263 case REG_LCOUNT:
264 tmp = regs->lcount;
265 break;
266
267 case REG_SAR:
268 tmp = regs->sar;
269 break;
270
271 case SYSCALL_NR:
272 tmp = regs->syscall;
273 break;
274
275 default:
276 return -EIO;
277 }
278 return put_user(tmp, ret);
279 }
280
281 static int ptrace_pokeusr(struct task_struct *child, long regno, long val)
282 {
283 struct pt_regs *regs;
284 regs = task_pt_regs(child);
285
286 switch (regno) {
287 case REG_AR_BASE ... REG_AR_BASE + XCHAL_NUM_AREGS - 1:
288 regs->areg[regno - REG_AR_BASE] = val;
289 break;
290
291 case REG_A_BASE ... REG_A_BASE + 15:
292 regs->areg[regno - REG_A_BASE] = val;
293 break;
294
295 case REG_PC:
296 regs->pc = val;
297 break;
298
299 case SYSCALL_NR:
300 regs->syscall = val;
301 break;
302
303 default:
304 return -EIO;
305 }
306 return 0;
307 }
308
309 #ifdef CONFIG_HAVE_HW_BREAKPOINT
310 static void ptrace_hbptriggered(struct perf_event *bp,
311 struct perf_sample_data *data,
312 struct pt_regs *regs)
313 {
314 int i;
315 siginfo_t info;
316 struct arch_hw_breakpoint *bkpt = counter_arch_bp(bp);
317
318 if (bp->attr.bp_type & HW_BREAKPOINT_X) {
319 for (i = 0; i < XCHAL_NUM_IBREAK; ++i)
320 if (current->thread.ptrace_bp[i] == bp)
321 break;
322 i <<= 1;
323 } else {
324 for (i = 0; i < XCHAL_NUM_DBREAK; ++i)
325 if (current->thread.ptrace_wp[i] == bp)
326 break;
327 i = (i << 1) | 1;
328 }
329
330 info.si_signo = SIGTRAP;
331 info.si_errno = i;
332 info.si_code = TRAP_HWBKPT;
333 info.si_addr = (void __user *)bkpt->address;
334
335 force_sig_info(SIGTRAP, &info, current);
336 }
337
338 static struct perf_event *ptrace_hbp_create(struct task_struct *tsk, int type)
339 {
340 struct perf_event_attr attr;
341
342 ptrace_breakpoint_init(&attr);
343
344 /* Initialise fields to sane defaults. */
345 attr.bp_addr = 0;
346 attr.bp_len = 1;
347 attr.bp_type = type;
348 attr.disabled = 1;
349
350 return register_user_hw_breakpoint(&attr, ptrace_hbptriggered, NULL,
351 tsk);
352 }
353
354 /*
355 * Address bit 0 choose instruction (0) or data (1) break register, bits
356 * 31..1 are the register number.
357 * Both PTRACE_GETHBPREGS and PTRACE_SETHBPREGS transfer two 32-bit words:
358 * address (0) and control (1).
359 * Instruction breakpoint contorl word is 0 to clear breakpoint, 1 to set.
360 * Data breakpoint control word bit 31 is 'trigger on store', bit 30 is
361 * 'trigger on load, bits 29..0 are length. Length 0 is used to clear a
362 * breakpoint. To set a breakpoint length must be a power of 2 in the range
363 * 1..64 and the address must be length-aligned.
364 */
365
366 static long ptrace_gethbpregs(struct task_struct *child, long addr,
367 long __user *datap)
368 {
369 struct perf_event *bp;
370 u32 user_data[2] = {0};
371 bool dbreak = addr & 1;
372 unsigned idx = addr >> 1;
373
374 if ((!dbreak && idx >= XCHAL_NUM_IBREAK) ||
375 (dbreak && idx >= XCHAL_NUM_DBREAK))
376 return -EINVAL;
377
378 if (dbreak)
379 bp = child->thread.ptrace_wp[idx];
380 else
381 bp = child->thread.ptrace_bp[idx];
382
383 if (bp) {
384 user_data[0] = bp->attr.bp_addr;
385 user_data[1] = bp->attr.disabled ? 0 : bp->attr.bp_len;
386 if (dbreak) {
387 if (bp->attr.bp_type & HW_BREAKPOINT_R)
388 user_data[1] |= DBREAKC_LOAD_MASK;
389 if (bp->attr.bp_type & HW_BREAKPOINT_W)
390 user_data[1] |= DBREAKC_STOR_MASK;
391 }
392 }
393
394 if (copy_to_user(datap, user_data, sizeof(user_data)))
395 return -EFAULT;
396
397 return 0;
398 }
399
400 static long ptrace_sethbpregs(struct task_struct *child, long addr,
401 long __user *datap)
402 {
403 struct perf_event *bp;
404 struct perf_event_attr attr;
405 u32 user_data[2];
406 bool dbreak = addr & 1;
407 unsigned idx = addr >> 1;
408 int bp_type = 0;
409
410 if ((!dbreak && idx >= XCHAL_NUM_IBREAK) ||
411 (dbreak && idx >= XCHAL_NUM_DBREAK))
412 return -EINVAL;
413
414 if (copy_from_user(user_data, datap, sizeof(user_data)))
415 return -EFAULT;
416
417 if (dbreak) {
418 bp = child->thread.ptrace_wp[idx];
419 if (user_data[1] & DBREAKC_LOAD_MASK)
420 bp_type |= HW_BREAKPOINT_R;
421 if (user_data[1] & DBREAKC_STOR_MASK)
422 bp_type |= HW_BREAKPOINT_W;
423 } else {
424 bp = child->thread.ptrace_bp[idx];
425 bp_type = HW_BREAKPOINT_X;
426 }
427
428 if (!bp) {
429 bp = ptrace_hbp_create(child,
430 bp_type ? bp_type : HW_BREAKPOINT_RW);
431 if (IS_ERR(bp))
432 return PTR_ERR(bp);
433 if (dbreak)
434 child->thread.ptrace_wp[idx] = bp;
435 else
436 child->thread.ptrace_bp[idx] = bp;
437 }
438
439 attr = bp->attr;
440 attr.bp_addr = user_data[0];
441 attr.bp_len = user_data[1] & ~(DBREAKC_LOAD_MASK | DBREAKC_STOR_MASK);
442 attr.bp_type = bp_type;
443 attr.disabled = !attr.bp_len;
444
445 return modify_user_hw_breakpoint(bp, &attr);
446 }
447 #endif
448
449 long arch_ptrace(struct task_struct *child, long request,
450 unsigned long addr, unsigned long data)
451 {
452 int ret = -EPERM;
453 void __user *datap = (void __user *) data;
454
455 switch (request) {
456 case PTRACE_PEEKTEXT: /* read word at location addr. */
457 case PTRACE_PEEKDATA:
458 ret = generic_ptrace_peekdata(child, addr, data);
459 break;
460
461 case PTRACE_PEEKUSR: /* read register specified by addr. */
462 ret = ptrace_peekusr(child, addr, datap);
463 break;
464
465 case PTRACE_POKETEXT: /* write the word at location addr. */
466 case PTRACE_POKEDATA:
467 ret = generic_ptrace_pokedata(child, addr, data);
468 break;
469
470 case PTRACE_POKEUSR: /* write register specified by addr. */
471 ret = ptrace_pokeusr(child, addr, data);
472 break;
473
474 case PTRACE_GETREGS:
475 ret = ptrace_getregs(child, datap);
476 break;
477
478 case PTRACE_SETREGS:
479 ret = ptrace_setregs(child, datap);
480 break;
481
482 case PTRACE_GETXTREGS:
483 ret = ptrace_getxregs(child, datap);
484 break;
485
486 case PTRACE_SETXTREGS:
487 ret = ptrace_setxregs(child, datap);
488 break;
489 #ifdef CONFIG_HAVE_HW_BREAKPOINT
490 case PTRACE_GETHBPREGS:
491 ret = ptrace_gethbpregs(child, addr, datap);
492 break;
493
494 case PTRACE_SETHBPREGS:
495 ret = ptrace_sethbpregs(child, addr, datap);
496 break;
497 #endif
498 default:
499 ret = ptrace_request(child, request, addr, data);
500 break;
501 }
502
503 return ret;
504 }
505
506 unsigned long do_syscall_trace_enter(struct pt_regs *regs)
507 {
508 if (test_thread_flag(TIF_SYSCALL_TRACE) &&
509 tracehook_report_syscall_entry(regs))
510 return -1;
511
512 return regs->areg[2];
513 }
514
515 void do_syscall_trace_leave(struct pt_regs *regs)
516 {
517 int step;
518
519 step = test_thread_flag(TIF_SINGLESTEP);
520
521 if (step || test_thread_flag(TIF_SYSCALL_TRACE))
522 tracehook_report_syscall_exit(regs, step);
523 }
Linux with added FPC-III support