| blob | 8213ca15abd2e8c654a238ea40254ceef85483b2 |
1 /*
2 * Low-level exception handling code
3 *
4 * Copyright (C) 2012 ARM Ltd.
5 * Authors: Catalin Marinas <catalin.marinas@arm.com>
6 * Will Deacon <will.deacon@arm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
21 #include <linux/init.h>
22 #include <linux/linkage.h>
24 #include <asm/alternative.h>
25 #include <asm/assembler.h>
26 #include <asm/asm-offsets.h>
27 #include <asm/cpufeature.h>
28 #include <asm/errno.h>
29 #include <asm/esr.h>
30 #include <asm/thread_info.h>
31 #include <asm/unistd.h>
33 /*
34 * Context tracking subsystem. Used to instrument transitions
35 * between user and kernel mode.
36 */
37 .macro ct_user_exit, syscall = 0
38 #ifdef CONFIG_CONTEXT_TRACKING
39 bl context_tracking_user_exit
40 .if \syscall == 1
41 /*
42 * Save/restore needed during syscalls. Restore syscall arguments from
43 * the values already saved on stack during kernel_entry.
44 */
45 ldp x0, x1, [sp]
46 ldp x2, x3, [sp, #S_X2]
47 ldp x4, x5, [sp, #S_X4]
48 ldp x6, x7, [sp, #S_X6]
49 .endif
50 #endif
51 .endm
53 .macro ct_user_enter
54 #ifdef CONFIG_CONTEXT_TRACKING
55 bl context_tracking_user_enter
56 #endif
57 .endm
59 /*
60 * Bad Abort numbers
61 *-----------------
62 */
63 #define BAD_SYNC 0
64 #define BAD_IRQ 1
65 #define BAD_FIQ 2
66 #define BAD_ERROR 3
68 .macro kernel_entry, el, regsize = 64
69 sub sp, sp, #S_FRAME_SIZE
70 .if \regsize == 32
71 mov w0, w0 // zero upper 32 bits of x0
72 .endif
73 stp x0, x1, [sp, #16 * 0]
74 stp x2, x3, [sp, #16 * 1]
75 stp x4, x5, [sp, #16 * 2]
76 stp x6, x7, [sp, #16 * 3]
77 stp x8, x9, [sp, #16 * 4]
78 stp x10, x11, [sp, #16 * 5]
79 stp x12, x13, [sp, #16 * 6]
80 stp x14, x15, [sp, #16 * 7]
81 stp x16, x17, [sp, #16 * 8]
82 stp x18, x19, [sp, #16 * 9]
83 stp x20, x21, [sp, #16 * 10]
84 stp x22, x23, [sp, #16 * 11]
85 stp x24, x25, [sp, #16 * 12]
86 stp x26, x27, [sp, #16 * 13]
87 stp x28, x29, [sp, #16 * 14]
89 .if \el == 0
90 mrs x21, sp_el0
91 get_thread_info tsk // Ensure MDSCR_EL1.SS is clear,
92 ldr x19, [tsk, #TI_FLAGS] // since we can unmask debug
93 disable_step_tsk x19, x20 // exceptions when scheduling.
94 .else
95 add x21, sp, #S_FRAME_SIZE
96 .endif
97 mrs x22, elr_el1
98 mrs x23, spsr_el1
99 stp lr, x21, [sp, #S_LR]
100 stp x22, x23, [sp, #S_PC]
102 /*
103 * Set syscallno to -1 by default (overridden later if real syscall).
104 */
105 .if \el == 0
106 mvn x21, xzr
107 str x21, [sp, #S_SYSCALLNO]
108 .endif
110 /*
111 * Registers that may be useful after this macro is invoked:
112 *
113 * x21 - aborted SP
114 * x22 - aborted PC
115 * x23 - aborted PSTATE
116 */
117 .endm
119 .macro kernel_exit, el
120 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
121 .if \el == 0
122 ct_user_enter
123 ldr x23, [sp, #S_SP] // load return stack pointer
124 msr sp_el0, x23
126 #ifdef CONFIG_ARM64_ERRATUM_845719
128 #undef SEQUENCE_ORG
129 #undef SEQUENCE_ALT
131 #ifdef CONFIG_PID_IN_CONTEXTIDR
133 #define SEQUENCE_ORG "nop ; nop ; nop"
134 #define SEQUENCE_ALT "tbz x22, #4, 1f ; mrs x29, contextidr_el1; msr contextidr_el1, x29; 1:"
136 #else
138 #define SEQUENCE_ORG "nop ; nop"
139 #define SEQUENCE_ALT "tbz x22, #4, 1f ; msr contextidr_el1, xzr; 1:"
141 #endif
143 alternative_insn SEQUENCE_ORG, SEQUENCE_ALT, ARM64_WORKAROUND_845719
145 #endif
146 .endif
147 msr elr_el1, x21 // set up the return data
148 msr spsr_el1, x22
149 ldp x0, x1, [sp, #16 * 0]
150 ldp x2, x3, [sp, #16 * 1]
151 ldp x4, x5, [sp, #16 * 2]
152 ldp x6, x7, [sp, #16 * 3]
153 ldp x8, x9, [sp, #16 * 4]
154 ldp x10, x11, [sp, #16 * 5]
155 ldp x12, x13, [sp, #16 * 6]
156 ldp x14, x15, [sp, #16 * 7]
157 ldp x16, x17, [sp, #16 * 8]
158 ldp x18, x19, [sp, #16 * 9]
159 ldp x20, x21, [sp, #16 * 10]
160 ldp x22, x23, [sp, #16 * 11]
161 ldp x24, x25, [sp, #16 * 12]
162 ldp x26, x27, [sp, #16 * 13]
163 ldp x28, x29, [sp, #16 * 14]
164 ldr lr, [sp, #S_LR]
165 add sp, sp, #S_FRAME_SIZE // restore sp
166 eret // return to kernel
167 .endm
169 .macro get_thread_info, rd
170 mov \rd, sp
171 and \rd, \rd, #~(THREAD_SIZE - 1) // top of stack
172 .endm
174 /*
175 * These are the registers used in the syscall handler, and allow us to
176 * have in theory up to 7 arguments to a function - x0 to x6.
177 *
178 * x7 is reserved for the system call number in 32-bit mode.
179 */
180 sc_nr .req x25 // number of system calls
181 scno .req x26 // syscall number
182 stbl .req x27 // syscall table pointer
183 tsk .req x28 // current thread_info
185 /*
186 * Interrupt handling.
187 */
188 .macro irq_handler
189 adrp x1, handle_arch_irq
190 ldr x1, [x1, #:lo12:handle_arch_irq]
191 mov x0, sp
192 blr x1
193 .endm
195 .text
197 /*
198 * Exception vectors.
199 */
201 .align 11
202 ENTRY(vectors)
203 ventry el1_sync_invalid // Synchronous EL1t
204 ventry el1_irq_invalid // IRQ EL1t
205 ventry el1_fiq_invalid // FIQ EL1t
206 ventry el1_error_invalid // Error EL1t
208 ventry el1_sync // Synchronous EL1h
209 ventry el1_irq // IRQ EL1h
210 ventry el1_fiq_invalid // FIQ EL1h
211 ventry el1_error_invalid // Error EL1h
213 ventry el0_sync // Synchronous 64-bit EL0
214 ventry el0_irq // IRQ 64-bit EL0
215 ventry el0_fiq_invalid // FIQ 64-bit EL0
216 ventry el0_error_invalid // Error 64-bit EL0
218 #ifdef CONFIG_COMPAT
219 ventry el0_sync_compat // Synchronous 32-bit EL0
220 ventry el0_irq_compat // IRQ 32-bit EL0
221 ventry el0_fiq_invalid_compat // FIQ 32-bit EL0
222 ventry el0_error_invalid_compat // Error 32-bit EL0
223 #else
224 ventry el0_sync_invalid // Synchronous 32-bit EL0
225 ventry el0_irq_invalid // IRQ 32-bit EL0
226 ventry el0_fiq_invalid // FIQ 32-bit EL0
227 ventry el0_error_invalid // Error 32-bit EL0
228 #endif
229 END(vectors)
231 /*
232 * Invalid mode handlers
233 */
234 .macro inv_entry, el, reason, regsize = 64
235 kernel_entry el, \regsize
236 mov x0, sp
237 mov x1, #\reason
238 mrs x2, esr_el1
239 b bad_mode
240 .endm
242 el0_sync_invalid:
243 inv_entry 0, BAD_SYNC
244 ENDPROC(el0_sync_invalid)
246 el0_irq_invalid:
247 inv_entry 0, BAD_IRQ
248 ENDPROC(el0_irq_invalid)
250 el0_fiq_invalid:
251 inv_entry 0, BAD_FIQ
252 ENDPROC(el0_fiq_invalid)
254 el0_error_invalid:
255 inv_entry 0, BAD_ERROR
256 ENDPROC(el0_error_invalid)
258 #ifdef CONFIG_COMPAT
259 el0_fiq_invalid_compat:
260 inv_entry 0, BAD_FIQ, 32
261 ENDPROC(el0_fiq_invalid_compat)
263 el0_error_invalid_compat:
264 inv_entry 0, BAD_ERROR, 32
265 ENDPROC(el0_error_invalid_compat)
266 #endif
268 el1_sync_invalid:
269 inv_entry 1, BAD_SYNC
270 ENDPROC(el1_sync_invalid)
272 el1_irq_invalid:
273 inv_entry 1, BAD_IRQ
274 ENDPROC(el1_irq_invalid)
276 el1_fiq_invalid:
277 inv_entry 1, BAD_FIQ
278 ENDPROC(el1_fiq_invalid)
280 el1_error_invalid:
281 inv_entry 1, BAD_ERROR
282 ENDPROC(el1_error_invalid)
284 /*
285 * EL1 mode handlers.
286 */
287 .align 6
288 el1_sync:
289 kernel_entry 1
290 mrs x1, esr_el1 // read the syndrome register
291 lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class
292 cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1
293 b.eq el1_da
294 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
295 b.eq el1_undef
296 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
297 b.eq el1_sp_pc
298 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
299 b.eq el1_sp_pc
300 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1
301 b.eq el1_undef
302 cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1
303 b.ge el1_dbg
304 b el1_inv
305 el1_da:
306 /*
307 * Data abort handling
308 */
309 mrs x0, far_el1
310 enable_dbg
311 // re-enable interrupts if they were enabled in the aborted context
312 tbnz x23, #7, 1f // PSR_I_BIT
313 enable_irq
314 1:
315 mov x2, sp // struct pt_regs
316 bl do_mem_abort
318 // disable interrupts before pulling preserved data off the stack
319 disable_irq
320 kernel_exit 1
321 el1_sp_pc:
322 /*
323 * Stack or PC alignment exception handling
324 */
325 mrs x0, far_el1
326 enable_dbg
327 mov x2, sp
328 b do_sp_pc_abort
329 el1_undef:
330 /*
331 * Undefined instruction
332 */
333 enable_dbg
334 mov x0, sp
335 b do_undefinstr
336 el1_dbg:
337 /*
338 * Debug exception handling
339 */
340 cmp x24, #ESR_ELx_EC_BRK64 // if BRK64
341 cinc x24, x24, eq // set bit '0'
342 tbz x24, #0, el1_inv // EL1 only
343 mrs x0, far_el1
344 mov x2, sp // struct pt_regs
345 bl do_debug_exception
346 kernel_exit 1
347 el1_inv:
348 // TODO: add support for undefined instructions in kernel mode
349 enable_dbg
350 mov x0, sp
351 mov x2, x1
352 mov x1, #BAD_SYNC
353 b bad_mode
354 ENDPROC(el1_sync)
356 .align 6
357 el1_irq:
358 kernel_entry 1
359 enable_dbg
360 #ifdef CONFIG_TRACE_IRQFLAGS
361 bl trace_hardirqs_off
362 #endif
364 irq_handler
366 #ifdef CONFIG_PREEMPT
367 get_thread_info tsk
368 ldr w24, [tsk, #TI_PREEMPT] // get preempt count
369 cbnz w24, 1f // preempt count != 0
370 ldr x0, [tsk, #TI_FLAGS] // get flags
371 tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling?
372 bl el1_preempt
373 1:
374 #endif
375 #ifdef CONFIG_TRACE_IRQFLAGS
376 bl trace_hardirqs_on
377 #endif
378 kernel_exit 1
379 ENDPROC(el1_irq)
381 #ifdef CONFIG_PREEMPT
382 el1_preempt:
383 mov x24, lr
384 1: bl preempt_schedule_irq // irq en/disable is done inside
385 ldr x0, [tsk, #TI_FLAGS] // get new tasks TI_FLAGS
386 tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling?
387 ret x24
388 #endif
390 /*
391 * EL0 mode handlers.
392 */
393 .align 6
394 el0_sync:
395 kernel_entry 0
396 mrs x25, esr_el1 // read the syndrome register
397 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
398 cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state
399 b.eq el0_svc
400 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
401 b.eq el0_da
402 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
403 b.eq el0_ia
404 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
405 b.eq el0_fpsimd_acc
406 cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception
407 b.eq el0_fpsimd_exc
408 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
409 b.eq el0_undef
410 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
411 b.eq el0_sp_pc
412 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
413 b.eq el0_sp_pc
414 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
415 b.eq el0_undef
416 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
417 b.ge el0_dbg
418 b el0_inv
420 #ifdef CONFIG_COMPAT
421 .align 6
422 el0_sync_compat:
423 kernel_entry 0, 32
424 mrs x25, esr_el1 // read the syndrome register
425 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
426 cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state
427 b.eq el0_svc_compat
428 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
429 b.eq el0_da
430 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
431 b.eq el0_ia
432 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
433 b.eq el0_fpsimd_acc
434 cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception
435 b.eq el0_fpsimd_exc
436 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
437 b.eq el0_undef
438 cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap
439 b.eq el0_undef
440 cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap
441 b.eq el0_undef
442 cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap
443 b.eq el0_undef
444 cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap
445 b.eq el0_undef
446 cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap
447 b.eq el0_undef
448 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
449 b.ge el0_dbg
450 b el0_inv
451 el0_svc_compat:
452 /*
453 * AArch32 syscall handling
454 */
455 adrp stbl, compat_sys_call_table // load compat syscall table pointer
456 uxtw scno, w7 // syscall number in w7 (r7)
457 mov sc_nr, #__NR_compat_syscalls
458 b el0_svc_naked
460 .align 6
461 el0_irq_compat:
462 kernel_entry 0, 32
463 b el0_irq_naked
464 #endif
466 el0_da:
467 /*
468 * Data abort handling
469 */
470 mrs x26, far_el1
471 // enable interrupts before calling the main handler
472 enable_dbg_and_irq
473 ct_user_exit
474 bic x0, x26, #(0xff << 56)
475 mov x1, x25
476 mov x2, sp
477 bl do_mem_abort
478 b ret_to_user
479 el0_ia:
480 /*
481 * Instruction abort handling
482 */
483 mrs x26, far_el1
484 // enable interrupts before calling the main handler
485 enable_dbg_and_irq
486 ct_user_exit
487 mov x0, x26
488 orr x1, x25, #1 << 24 // use reserved ISS bit for instruction aborts
489 mov x2, sp
490 bl do_mem_abort
491 b ret_to_user
492 el0_fpsimd_acc:
493 /*
494 * Floating Point or Advanced SIMD access
495 */
496 enable_dbg
497 ct_user_exit
498 mov x0, x25
499 mov x1, sp
500 bl do_fpsimd_acc
501 b ret_to_user
502 el0_fpsimd_exc:
503 /*
504 * Floating Point or Advanced SIMD exception
505 */
506 enable_dbg
507 ct_user_exit
508 mov x0, x25
509 mov x1, sp
510 bl do_fpsimd_exc
511 b ret_to_user
512 el0_sp_pc:
513 /*
514 * Stack or PC alignment exception handling
515 */
516 mrs x26, far_el1
517 // enable interrupts before calling the main handler
518 enable_dbg_and_irq
519 ct_user_exit
520 mov x0, x26
521 mov x1, x25
522 mov x2, sp
523 bl do_sp_pc_abort
524 b ret_to_user
525 el0_undef:
526 /*
527 * Undefined instruction
528 */
529 // enable interrupts before calling the main handler
530 enable_dbg_and_irq
531 ct_user_exit
532 mov x0, sp
533 bl do_undefinstr
534 b ret_to_user
535 el0_dbg:
536 /*
537 * Debug exception handling
538 */
539 tbnz x24, #0, el0_inv // EL0 only
540 mrs x0, far_el1
541 mov x1, x25
542 mov x2, sp
543 bl do_debug_exception
544 enable_dbg
545 ct_user_exit
546 b ret_to_user
547 el0_inv:
548 enable_dbg
549 ct_user_exit
550 mov x0, sp
551 mov x1, #BAD_SYNC
552 mov x2, x25
553 bl bad_mode
554 b ret_to_user
555 ENDPROC(el0_sync)
557 .align 6
558 el0_irq:
559 kernel_entry 0
560 el0_irq_naked:
561 enable_dbg
562 #ifdef CONFIG_TRACE_IRQFLAGS
563 bl trace_hardirqs_off
564 #endif
566 ct_user_exit
567 irq_handler
569 #ifdef CONFIG_TRACE_IRQFLAGS
570 bl trace_hardirqs_on
571 #endif
572 b ret_to_user
573 ENDPROC(el0_irq)
575 /*
576 * Register switch for AArch64. The callee-saved registers need to be saved
577 * and restored. On entry:
578 * x0 = previous task_struct (must be preserved across the switch)
579 * x1 = next task_struct
580 * Previous and next are guaranteed not to be the same.
581 *
582 */
583 ENTRY(cpu_switch_to)
584 mov x10, #THREAD_CPU_CONTEXT
585 add x8, x0, x10
586 mov x9, sp
587 stp x19, x20, [x8], #16 // store callee-saved registers
588 stp x21, x22, [x8], #16
589 stp x23, x24, [x8], #16
590 stp x25, x26, [x8], #16
591 stp x27, x28, [x8], #16
592 stp x29, x9, [x8], #16
593 str lr, [x8]
594 add x8, x1, x10
595 ldp x19, x20, [x8], #16 // restore callee-saved registers
596 ldp x21, x22, [x8], #16
597 ldp x23, x24, [x8], #16
598 ldp x25, x26, [x8], #16
599 ldp x27, x28, [x8], #16
600 ldp x29, x9, [x8], #16
601 ldr lr, [x8]
602 mov sp, x9
603 ret
604 ENDPROC(cpu_switch_to)
606 /*
607 * This is the fast syscall return path. We do as little as possible here,
608 * and this includes saving x0 back into the kernel stack.
609 */
610 ret_fast_syscall:
611 disable_irq // disable interrupts
612 str x0, [sp, #S_X0] // returned x0
613 ldr x1, [tsk, #TI_FLAGS] // re-check for syscall tracing
614 and x2, x1, #_TIF_SYSCALL_WORK
615 cbnz x2, ret_fast_syscall_trace
616 and x2, x1, #_TIF_WORK_MASK
617 cbnz x2, work_pending
618 enable_step_tsk x1, x2
619 kernel_exit 0
620 ret_fast_syscall_trace:
621 enable_irq // enable interrupts
622 b __sys_trace_return_skipped // we already saved x0
624 /*
625 * Ok, we need to do extra processing, enter the slow path.
626 */
627 work_pending:
628 tbnz x1, #TIF_NEED_RESCHED, work_resched
629 /* TIF_SIGPENDING, TIF_NOTIFY_RESUME or TIF_FOREIGN_FPSTATE case */
630 ldr x2, [sp, #S_PSTATE]
631 mov x0, sp // 'regs'
632 tst x2, #PSR_MODE_MASK // user mode regs?
633 b.ne no_work_pending // returning to kernel
634 enable_irq // enable interrupts for do_notify_resume()
635 bl do_notify_resume
636 b ret_to_user
637 work_resched:
638 bl schedule
640 /*
641 * "slow" syscall return path.
642 */
643 ret_to_user:
644 disable_irq // disable interrupts
645 ldr x1, [tsk, #TI_FLAGS]
646 and x2, x1, #_TIF_WORK_MASK
647 cbnz x2, work_pending
648 enable_step_tsk x1, x2
649 no_work_pending:
650 kernel_exit 0
651 ENDPROC(ret_to_user)
653 /*
654 * This is how we return from a fork.
655 */
656 ENTRY(ret_from_fork)
657 bl schedule_tail
658 cbz x19, 1f // not a kernel thread
659 mov x0, x20
660 blr x19
661 1: get_thread_info tsk
662 b ret_to_user
663 ENDPROC(ret_from_fork)
665 /*
666 * SVC handler.
667 */
668 .align 6
669 el0_svc:
670 adrp stbl, sys_call_table // load syscall table pointer
671 uxtw scno, w8 // syscall number in w8
672 mov sc_nr, #__NR_syscalls
673 el0_svc_naked: // compat entry point
674 stp x0, scno, [sp, #S_ORIG_X0] // save the original x0 and syscall number
675 enable_dbg_and_irq
676 ct_user_exit 1
678 ldr x16, [tsk, #TI_FLAGS] // check for syscall hooks
679 tst x16, #_TIF_SYSCALL_WORK
680 b.ne __sys_trace
681 cmp scno, sc_nr // check upper syscall limit
682 b.hs ni_sys
683 ldr x16, [stbl, scno, lsl #3] // address in the syscall table
684 blr x16 // call sys_* routine
685 b ret_fast_syscall
686 ni_sys:
687 mov x0, sp
688 bl do_ni_syscall
689 b ret_fast_syscall
690 ENDPROC(el0_svc)
692 /*
693 * This is the really slow path. We're going to be doing context
694 * switches, and waiting for our parent to respond.
695 */
696 __sys_trace:
697 mov w0, #-1 // set default errno for
698 cmp scno, x0 // user-issued syscall(-1)
699 b.ne 1f
700 mov x0, #-ENOSYS
701 str x0, [sp, #S_X0]
702 1: mov x0, sp
703 bl syscall_trace_enter
704 cmp w0, #-1 // skip the syscall?
705 b.eq __sys_trace_return_skipped
706 uxtw scno, w0 // syscall number (possibly new)
707 mov x1, sp // pointer to regs
708 cmp scno, sc_nr // check upper syscall limit
709 b.hs __ni_sys_trace
710 ldp x0, x1, [sp] // restore the syscall args
711 ldp x2, x3, [sp, #S_X2]
712 ldp x4, x5, [sp, #S_X4]
713 ldp x6, x7, [sp, #S_X6]
714 ldr x16, [stbl, scno, lsl #3] // address in the syscall table
715 blr x16 // call sys_* routine
717 __sys_trace_return:
718 str x0, [sp, #S_X0] // save returned x0
719 __sys_trace_return_skipped:
720 mov x0, sp
721 bl syscall_trace_exit
722 b ret_to_user
724 __ni_sys_trace:
725 mov x0, sp
726 bl do_ni_syscall
727 b __sys_trace_return
729 /*
730 * Special system call wrappers.
731 */
732 ENTRY(sys_rt_sigreturn_wrapper)
733 mov x0, sp
734 b sys_rt_sigreturn
735 ENDPROC(sys_rt_sigreturn_wrapper)