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Linux 4.2.2
[linux/fpc-iii.git] / arch / x86 / kvm / x86.c
blob8f0f6eca69da1dc6db95c16782871580bf57091d
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "assigned-dev.h"
31 #include "pmu.h"
32
33 #include <linux/clocksource.h>
34 #include <linux/interrupt.h>
35 #include <linux/kvm.h>
36 #include <linux/fs.h>
37 #include <linux/vmalloc.h>
38 #include <linux/module.h>
39 #include <linux/mman.h>
40 #include <linux/highmem.h>
41 #include <linux/iommu.h>
42 #include <linux/intel-iommu.h>
43 #include <linux/cpufreq.h>
44 #include <linux/user-return-notifier.h>
45 #include <linux/srcu.h>
46 #include <linux/slab.h>
47 #include <linux/perf_event.h>
48 #include <linux/uaccess.h>
49 #include <linux/hash.h>
50 #include <linux/pci.h>
51 #include <linux/timekeeper_internal.h>
52 #include <linux/pvclock_gtod.h>
53 #include <trace/events/kvm.h>
54
55 #define CREATE_TRACE_POINTS
56 #include "trace.h"
57
58 #include <asm/debugreg.h>
59 #include <asm/msr.h>
60 #include <asm/desc.h>
61 #include <asm/mce.h>
62 #include <linux/kernel_stat.h>
63 #include <asm/fpu/internal.h> /* Ugh! */
64 #include <asm/pvclock.h>
65 #include <asm/div64.h>
66
67 #define MAX_IO_MSRS 256
68 #define KVM_MAX_MCE_BANKS 32
69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
70
71 #define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
74 /* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78 #ifdef CONFIG_X86_64
79 static
80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
81 #else
82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
83 #endif
84
85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
87
88 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
89 static void process_nmi(struct kvm_vcpu *vcpu);
90 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
91
92 struct kvm_x86_ops *kvm_x86_ops;
93 EXPORT_SYMBOL_GPL(kvm_x86_ops);
94
95 static bool ignore_msrs = 0;
96 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
97
98 unsigned int min_timer_period_us = 500;
99 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
100
101 static bool __read_mostly kvmclock_periodic_sync = true;
102 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
103
104 bool kvm_has_tsc_control;
105 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
106 u32 kvm_max_guest_tsc_khz;
107 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
108
109 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
110 static u32 tsc_tolerance_ppm = 250;
111 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
112
113 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
114 unsigned int lapic_timer_advance_ns = 0;
115 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
116
117 static bool backwards_tsc_observed = false;
118
119 #define KVM_NR_SHARED_MSRS 16
120
121 struct kvm_shared_msrs_global {
122 int nr;
123 u32 msrs[KVM_NR_SHARED_MSRS];
124 };
125
126 struct kvm_shared_msrs {
127 struct user_return_notifier urn;
128 bool registered;
129 struct kvm_shared_msr_values {
130 u64 host;
131 u64 curr;
132 } values[KVM_NR_SHARED_MSRS];
133 };
134
135 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
136 static struct kvm_shared_msrs __percpu *shared_msrs;
137
138 struct kvm_stats_debugfs_item debugfs_entries[] = {
139 { "pf_fixed", VCPU_STAT(pf_fixed) },
140 { "pf_guest", VCPU_STAT(pf_guest) },
141 { "tlb_flush", VCPU_STAT(tlb_flush) },
142 { "invlpg", VCPU_STAT(invlpg) },
143 { "exits", VCPU_STAT(exits) },
144 { "io_exits", VCPU_STAT(io_exits) },
145 { "mmio_exits", VCPU_STAT(mmio_exits) },
146 { "signal_exits", VCPU_STAT(signal_exits) },
147 { "irq_window", VCPU_STAT(irq_window_exits) },
148 { "nmi_window", VCPU_STAT(nmi_window_exits) },
149 { "halt_exits", VCPU_STAT(halt_exits) },
150 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
151 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
152 { "hypercalls", VCPU_STAT(hypercalls) },
153 { "request_irq", VCPU_STAT(request_irq_exits) },
154 { "irq_exits", VCPU_STAT(irq_exits) },
155 { "host_state_reload", VCPU_STAT(host_state_reload) },
156 { "efer_reload", VCPU_STAT(efer_reload) },
157 { "fpu_reload", VCPU_STAT(fpu_reload) },
158 { "insn_emulation", VCPU_STAT(insn_emulation) },
159 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
160 { "irq_injections", VCPU_STAT(irq_injections) },
161 { "nmi_injections", VCPU_STAT(nmi_injections) },
162 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
163 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
164 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
165 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
166 { "mmu_flooded", VM_STAT(mmu_flooded) },
167 { "mmu_recycled", VM_STAT(mmu_recycled) },
168 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
169 { "mmu_unsync", VM_STAT(mmu_unsync) },
170 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
171 { "largepages", VM_STAT(lpages) },
172 { NULL }
173 };
174
175 u64 __read_mostly host_xcr0;
176
177 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
178
179 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
180 {
181 int i;
182 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
183 vcpu->arch.apf.gfns[i] = ~0;
184 }
185
186 static void kvm_on_user_return(struct user_return_notifier *urn)
187 {
188 unsigned slot;
189 struct kvm_shared_msrs *locals
190 = container_of(urn, struct kvm_shared_msrs, urn);
191 struct kvm_shared_msr_values *values;
192
193 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
194 values = &locals->values[slot];
195 if (values->host != values->curr) {
196 wrmsrl(shared_msrs_global.msrs[slot], values->host);
197 values->curr = values->host;
198 }
199 }
200 locals->registered = false;
201 user_return_notifier_unregister(urn);
202 }
203
204 static void shared_msr_update(unsigned slot, u32 msr)
205 {
206 u64 value;
207 unsigned int cpu = smp_processor_id();
208 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
209
210 /* only read, and nobody should modify it at this time,
211 * so don't need lock */
212 if (slot >= shared_msrs_global.nr) {
213 printk(KERN_ERR "kvm: invalid MSR slot!");
214 return;
215 }
216 rdmsrl_safe(msr, &value);
217 smsr->values[slot].host = value;
218 smsr->values[slot].curr = value;
219 }
220
221 void kvm_define_shared_msr(unsigned slot, u32 msr)
222 {
223 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
224 if (slot >= shared_msrs_global.nr)
225 shared_msrs_global.nr = slot + 1;
226 shared_msrs_global.msrs[slot] = msr;
227 /* we need ensured the shared_msr_global have been updated */
228 smp_wmb();
229 }
230 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
231
232 static void kvm_shared_msr_cpu_online(void)
233 {
234 unsigned i;
235
236 for (i = 0; i < shared_msrs_global.nr; ++i)
237 shared_msr_update(i, shared_msrs_global.msrs[i]);
238 }
239
240 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
241 {
242 unsigned int cpu = smp_processor_id();
243 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
244 int err;
245
246 if (((value ^ smsr->values[slot].curr) & mask) == 0)
247 return 0;
248 smsr->values[slot].curr = value;
249 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
250 if (err)
251 return 1;
252
253 if (!smsr->registered) {
254 smsr->urn.on_user_return = kvm_on_user_return;
255 user_return_notifier_register(&smsr->urn);
256 smsr->registered = true;
257 }
258 return 0;
259 }
260 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
261
262 static void drop_user_return_notifiers(void)
263 {
264 unsigned int cpu = smp_processor_id();
265 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
266
267 if (smsr->registered)
268 kvm_on_user_return(&smsr->urn);
269 }
270
271 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
272 {
273 return vcpu->arch.apic_base;
274 }
275 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
276
277 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
278 {
279 u64 old_state = vcpu->arch.apic_base &
280 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
281 u64 new_state = msr_info->data &
282 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
283 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
284 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
285
286 if (!msr_info->host_initiated &&
287 ((msr_info->data & reserved_bits) != 0 ||
288 new_state == X2APIC_ENABLE ||
289 (new_state == MSR_IA32_APICBASE_ENABLE &&
290 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
291 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
292 old_state == 0)))
293 return 1;
294
295 kvm_lapic_set_base(vcpu, msr_info->data);
296 return 0;
297 }
298 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
299
300 asmlinkage __visible void kvm_spurious_fault(void)
301 {
302 /* Fault while not rebooting. We want the trace. */
303 BUG();
304 }
305 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
306
307 #define EXCPT_BENIGN 0
308 #define EXCPT_CONTRIBUTORY 1
309 #define EXCPT_PF 2
310
311 static int exception_class(int vector)
312 {
313 switch (vector) {
314 case PF_VECTOR:
315 return EXCPT_PF;
316 case DE_VECTOR:
317 case TS_VECTOR:
318 case NP_VECTOR:
319 case SS_VECTOR:
320 case GP_VECTOR:
321 return EXCPT_CONTRIBUTORY;
322 default:
323 break;
324 }
325 return EXCPT_BENIGN;
326 }
327
328 #define EXCPT_FAULT 0
329 #define EXCPT_TRAP 1
330 #define EXCPT_ABORT 2
331 #define EXCPT_INTERRUPT 3
332
333 static int exception_type(int vector)
334 {
335 unsigned int mask;
336
337 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
338 return EXCPT_INTERRUPT;
339
340 mask = 1 << vector;
341
342 /* #DB is trap, as instruction watchpoints are handled elsewhere */
343 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
344 return EXCPT_TRAP;
345
346 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
347 return EXCPT_ABORT;
348
349 /* Reserved exceptions will result in fault */
350 return EXCPT_FAULT;
351 }
352
353 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
354 unsigned nr, bool has_error, u32 error_code,
355 bool reinject)
356 {
357 u32 prev_nr;
358 int class1, class2;
359
360 kvm_make_request(KVM_REQ_EVENT, vcpu);
361
362 if (!vcpu->arch.exception.pending) {
363 queue:
364 if (has_error && !is_protmode(vcpu))
365 has_error = false;
366 vcpu->arch.exception.pending = true;
367 vcpu->arch.exception.has_error_code = has_error;
368 vcpu->arch.exception.nr = nr;
369 vcpu->arch.exception.error_code = error_code;
370 vcpu->arch.exception.reinject = reinject;
371 return;
372 }
373
374 /* to check exception */
375 prev_nr = vcpu->arch.exception.nr;
376 if (prev_nr == DF_VECTOR) {
377 /* triple fault -> shutdown */
378 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
379 return;
380 }
381 class1 = exception_class(prev_nr);
382 class2 = exception_class(nr);
383 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
384 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
385 /* generate double fault per SDM Table 5-5 */
386 vcpu->arch.exception.pending = true;
387 vcpu->arch.exception.has_error_code = true;
388 vcpu->arch.exception.nr = DF_VECTOR;
389 vcpu->arch.exception.error_code = 0;
390 } else
391 /* replace previous exception with a new one in a hope
392 that instruction re-execution will regenerate lost
393 exception */
394 goto queue;
395 }
396
397 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
398 {
399 kvm_multiple_exception(vcpu, nr, false, 0, false);
400 }
401 EXPORT_SYMBOL_GPL(kvm_queue_exception);
402
403 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
404 {
405 kvm_multiple_exception(vcpu, nr, false, 0, true);
406 }
407 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
408
409 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
410 {
411 if (err)
412 kvm_inject_gp(vcpu, 0);
413 else
414 kvm_x86_ops->skip_emulated_instruction(vcpu);
415 }
416 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
417
418 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
419 {
420 ++vcpu->stat.pf_guest;
421 vcpu->arch.cr2 = fault->address;
422 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
423 }
424 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
425
426 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
427 {
428 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
429 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
430 else
431 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
432
433 return fault->nested_page_fault;
434 }
435
436 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
437 {
438 atomic_inc(&vcpu->arch.nmi_queued);
439 kvm_make_request(KVM_REQ_NMI, vcpu);
440 }
441 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
442
443 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
444 {
445 kvm_multiple_exception(vcpu, nr, true, error_code, false);
446 }
447 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
448
449 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
450 {
451 kvm_multiple_exception(vcpu, nr, true, error_code, true);
452 }
453 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
454
455 /*
456 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
457 * a #GP and return false.
458 */
459 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
460 {
461 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
462 return true;
463 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
464 return false;
465 }
466 EXPORT_SYMBOL_GPL(kvm_require_cpl);
467
468 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
469 {
470 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
471 return true;
472
473 kvm_queue_exception(vcpu, UD_VECTOR);
474 return false;
475 }
476 EXPORT_SYMBOL_GPL(kvm_require_dr);
477
478 /*
479 * This function will be used to read from the physical memory of the currently
480 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
481 * can read from guest physical or from the guest's guest physical memory.
482 */
483 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
484 gfn_t ngfn, void *data, int offset, int len,
485 u32 access)
486 {
487 struct x86_exception exception;
488 gfn_t real_gfn;
489 gpa_t ngpa;
490
491 ngpa = gfn_to_gpa(ngfn);
492 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
493 if (real_gfn == UNMAPPED_GVA)
494 return -EFAULT;
495
496 real_gfn = gpa_to_gfn(real_gfn);
497
498 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
499 }
500 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
501
502 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
503 void *data, int offset, int len, u32 access)
504 {
505 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
506 data, offset, len, access);
507 }
508
509 /*
510 * Load the pae pdptrs. Return true is they are all valid.
511 */
512 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
513 {
514 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
515 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
516 int i;
517 int ret;
518 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
519
520 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
521 offset * sizeof(u64), sizeof(pdpte),
522 PFERR_USER_MASK|PFERR_WRITE_MASK);
523 if (ret < 0) {
524 ret = 0;
525 goto out;
526 }
527 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
528 if (is_present_gpte(pdpte[i]) &&
529 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
530 ret = 0;
531 goto out;
532 }
533 }
534 ret = 1;
535
536 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
537 __set_bit(VCPU_EXREG_PDPTR,
538 (unsigned long *)&vcpu->arch.regs_avail);
539 __set_bit(VCPU_EXREG_PDPTR,
540 (unsigned long *)&vcpu->arch.regs_dirty);
541 out:
542
543 return ret;
544 }
545 EXPORT_SYMBOL_GPL(load_pdptrs);
546
547 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
548 {
549 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
550 bool changed = true;
551 int offset;
552 gfn_t gfn;
553 int r;
554
555 if (is_long_mode(vcpu) || !is_pae(vcpu))
556 return false;
557
558 if (!test_bit(VCPU_EXREG_PDPTR,
559 (unsigned long *)&vcpu->arch.regs_avail))
560 return true;
561
562 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
563 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
564 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
565 PFERR_USER_MASK | PFERR_WRITE_MASK);
566 if (r < 0)
567 goto out;
568 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
569 out:
570
571 return changed;
572 }
573
574 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
575 {
576 unsigned long old_cr0 = kvm_read_cr0(vcpu);
577 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
578
579 cr0 |= X86_CR0_ET;
580
581 #ifdef CONFIG_X86_64
582 if (cr0 & 0xffffffff00000000UL)
583 return 1;
584 #endif
585
586 cr0 &= ~CR0_RESERVED_BITS;
587
588 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
589 return 1;
590
591 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
592 return 1;
593
594 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
595 #ifdef CONFIG_X86_64
596 if ((vcpu->arch.efer & EFER_LME)) {
597 int cs_db, cs_l;
598
599 if (!is_pae(vcpu))
600 return 1;
601 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
602 if (cs_l)
603 return 1;
604 } else
605 #endif
606 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
607 kvm_read_cr3(vcpu)))
608 return 1;
609 }
610
611 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
612 return 1;
613
614 kvm_x86_ops->set_cr0(vcpu, cr0);
615
616 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
617 kvm_clear_async_pf_completion_queue(vcpu);
618 kvm_async_pf_hash_reset(vcpu);
619 }
620
621 if ((cr0 ^ old_cr0) & update_bits)
622 kvm_mmu_reset_context(vcpu);
623
624 if ((cr0 ^ old_cr0) & X86_CR0_CD)
625 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
626
627 return 0;
628 }
629 EXPORT_SYMBOL_GPL(kvm_set_cr0);
630
631 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
632 {
633 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
634 }
635 EXPORT_SYMBOL_GPL(kvm_lmsw);
636
637 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
638 {
639 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
640 !vcpu->guest_xcr0_loaded) {
641 /* kvm_set_xcr() also depends on this */
642 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
643 vcpu->guest_xcr0_loaded = 1;
644 }
645 }
646
647 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
648 {
649 if (vcpu->guest_xcr0_loaded) {
650 if (vcpu->arch.xcr0 != host_xcr0)
651 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
652 vcpu->guest_xcr0_loaded = 0;
653 }
654 }
655
656 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
657 {
658 u64 xcr0 = xcr;
659 u64 old_xcr0 = vcpu->arch.xcr0;
660 u64 valid_bits;
661
662 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
663 if (index != XCR_XFEATURE_ENABLED_MASK)
664 return 1;
665 if (!(xcr0 & XSTATE_FP))
666 return 1;
667 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
668 return 1;
669
670 /*
671 * Do not allow the guest to set bits that we do not support
672 * saving. However, xcr0 bit 0 is always set, even if the
673 * emulated CPU does not support XSAVE (see fx_init).
674 */
675 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
676 if (xcr0 & ~valid_bits)
677 return 1;
678
679 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
680 return 1;
681
682 if (xcr0 & XSTATE_AVX512) {
683 if (!(xcr0 & XSTATE_YMM))
684 return 1;
685 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
686 return 1;
687 }
688 kvm_put_guest_xcr0(vcpu);
689 vcpu->arch.xcr0 = xcr0;
690
691 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
692 kvm_update_cpuid(vcpu);
693 return 0;
694 }
695
696 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
697 {
698 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
699 __kvm_set_xcr(vcpu, index, xcr)) {
700 kvm_inject_gp(vcpu, 0);
701 return 1;
702 }
703 return 0;
704 }
705 EXPORT_SYMBOL_GPL(kvm_set_xcr);
706
707 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
708 {
709 unsigned long old_cr4 = kvm_read_cr4(vcpu);
710 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
711 X86_CR4_SMEP | X86_CR4_SMAP;
712
713 if (cr4 & CR4_RESERVED_BITS)
714 return 1;
715
716 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
717 return 1;
718
719 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
720 return 1;
721
722 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
723 return 1;
724
725 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
726 return 1;
727
728 if (is_long_mode(vcpu)) {
729 if (!(cr4 & X86_CR4_PAE))
730 return 1;
731 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
732 && ((cr4 ^ old_cr4) & pdptr_bits)
733 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
734 kvm_read_cr3(vcpu)))
735 return 1;
736
737 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
738 if (!guest_cpuid_has_pcid(vcpu))
739 return 1;
740
741 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
742 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
743 return 1;
744 }
745
746 if (kvm_x86_ops->set_cr4(vcpu, cr4))
747 return 1;
748
749 if (((cr4 ^ old_cr4) & pdptr_bits) ||
750 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
751 kvm_mmu_reset_context(vcpu);
752
753 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
754 kvm_update_cpuid(vcpu);
755
756 return 0;
757 }
758 EXPORT_SYMBOL_GPL(kvm_set_cr4);
759
760 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
761 {
762 #ifdef CONFIG_X86_64
763 cr3 &= ~CR3_PCID_INVD;
764 #endif
765
766 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
767 kvm_mmu_sync_roots(vcpu);
768 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
769 return 0;
770 }
771
772 if (is_long_mode(vcpu)) {
773 if (cr3 & CR3_L_MODE_RESERVED_BITS)
774 return 1;
775 } else if (is_pae(vcpu) && is_paging(vcpu) &&
776 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
777 return 1;
778
779 vcpu->arch.cr3 = cr3;
780 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
781 kvm_mmu_new_cr3(vcpu);
782 return 0;
783 }
784 EXPORT_SYMBOL_GPL(kvm_set_cr3);
785
786 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
787 {
788 if (cr8 & CR8_RESERVED_BITS)
789 return 1;
790 if (irqchip_in_kernel(vcpu->kvm))
791 kvm_lapic_set_tpr(vcpu, cr8);
792 else
793 vcpu->arch.cr8 = cr8;
794 return 0;
795 }
796 EXPORT_SYMBOL_GPL(kvm_set_cr8);
797
798 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
799 {
800 if (irqchip_in_kernel(vcpu->kvm))
801 return kvm_lapic_get_cr8(vcpu);
802 else
803 return vcpu->arch.cr8;
804 }
805 EXPORT_SYMBOL_GPL(kvm_get_cr8);
806
807 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
808 {
809 int i;
810
811 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
812 for (i = 0; i < KVM_NR_DB_REGS; i++)
813 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
814 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
815 }
816 }
817
818 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
819 {
820 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
821 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
822 }
823
824 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
825 {
826 unsigned long dr7;
827
828 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
829 dr7 = vcpu->arch.guest_debug_dr7;
830 else
831 dr7 = vcpu->arch.dr7;
832 kvm_x86_ops->set_dr7(vcpu, dr7);
833 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
834 if (dr7 & DR7_BP_EN_MASK)
835 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
836 }
837
838 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
839 {
840 u64 fixed = DR6_FIXED_1;
841
842 if (!guest_cpuid_has_rtm(vcpu))
843 fixed |= DR6_RTM;
844 return fixed;
845 }
846
847 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
848 {
849 switch (dr) {
850 case 0 ... 3:
851 vcpu->arch.db[dr] = val;
852 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
853 vcpu->arch.eff_db[dr] = val;
854 break;
855 case 4:
856 /* fall through */
857 case 6:
858 if (val & 0xffffffff00000000ULL)
859 return -1; /* #GP */
860 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
861 kvm_update_dr6(vcpu);
862 break;
863 case 5:
864 /* fall through */
865 default: /* 7 */
866 if (val & 0xffffffff00000000ULL)
867 return -1; /* #GP */
868 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
869 kvm_update_dr7(vcpu);
870 break;
871 }
872
873 return 0;
874 }
875
876 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
877 {
878 if (__kvm_set_dr(vcpu, dr, val)) {
879 kvm_inject_gp(vcpu, 0);
880 return 1;
881 }
882 return 0;
883 }
884 EXPORT_SYMBOL_GPL(kvm_set_dr);
885
886 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
887 {
888 switch (dr) {
889 case 0 ... 3:
890 *val = vcpu->arch.db[dr];
891 break;
892 case 4:
893 /* fall through */
894 case 6:
895 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
896 *val = vcpu->arch.dr6;
897 else
898 *val = kvm_x86_ops->get_dr6(vcpu);
899 break;
900 case 5:
901 /* fall through */
902 default: /* 7 */
903 *val = vcpu->arch.dr7;
904 break;
905 }
906 return 0;
907 }
908 EXPORT_SYMBOL_GPL(kvm_get_dr);
909
910 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
911 {
912 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
913 u64 data;
914 int err;
915
916 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
917 if (err)
918 return err;
919 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
920 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
921 return err;
922 }
923 EXPORT_SYMBOL_GPL(kvm_rdpmc);
924
925 /*
926 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
927 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
928 *
929 * This list is modified at module load time to reflect the
930 * capabilities of the host cpu. This capabilities test skips MSRs that are
931 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
932 * may depend on host virtualization features rather than host cpu features.
933 */
934
935 static u32 msrs_to_save[] = {
936 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
937 MSR_STAR,
938 #ifdef CONFIG_X86_64
939 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
940 #endif
941 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
942 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
943 };
944
945 static unsigned num_msrs_to_save;
946
947 static u32 emulated_msrs[] = {
948 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
949 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
950 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
951 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
952 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
953 MSR_KVM_PV_EOI_EN,
954
955 MSR_IA32_TSC_ADJUST,
956 MSR_IA32_TSCDEADLINE,
957 MSR_IA32_MISC_ENABLE,
958 MSR_IA32_MCG_STATUS,
959 MSR_IA32_MCG_CTL,
960 MSR_IA32_SMBASE,
961 };
962
963 static unsigned num_emulated_msrs;
964
965 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
966 {
967 if (efer & efer_reserved_bits)
968 return false;
969
970 if (efer & EFER_FFXSR) {
971 struct kvm_cpuid_entry2 *feat;
972
973 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
974 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
975 return false;
976 }
977
978 if (efer & EFER_SVME) {
979 struct kvm_cpuid_entry2 *feat;
980
981 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
982 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
983 return false;
984 }
985
986 return true;
987 }
988 EXPORT_SYMBOL_GPL(kvm_valid_efer);
989
990 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
991 {
992 u64 old_efer = vcpu->arch.efer;
993
994 if (!kvm_valid_efer(vcpu, efer))
995 return 1;
996
997 if (is_paging(vcpu)
998 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
999 return 1;
1000
1001 efer &= ~EFER_LMA;
1002 efer |= vcpu->arch.efer & EFER_LMA;
1003
1004 kvm_x86_ops->set_efer(vcpu, efer);
1005
1006 /* Update reserved bits */
1007 if ((efer ^ old_efer) & EFER_NX)
1008 kvm_mmu_reset_context(vcpu);
1009
1010 return 0;
1011 }
1012
1013 void kvm_enable_efer_bits(u64 mask)
1014 {
1015 efer_reserved_bits &= ~mask;
1016 }
1017 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1018
1019 /*
1020 * Writes msr value into into the appropriate "register".
1021 * Returns 0 on success, non-0 otherwise.
1022 * Assumes vcpu_load() was already called.
1023 */
1024 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1025 {
1026 switch (msr->index) {
1027 case MSR_FS_BASE:
1028 case MSR_GS_BASE:
1029 case MSR_KERNEL_GS_BASE:
1030 case MSR_CSTAR:
1031 case MSR_LSTAR:
1032 if (is_noncanonical_address(msr->data))
1033 return 1;
1034 break;
1035 case MSR_IA32_SYSENTER_EIP:
1036 case MSR_IA32_SYSENTER_ESP:
1037 /*
1038 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1039 * non-canonical address is written on Intel but not on
1040 * AMD (which ignores the top 32-bits, because it does
1041 * not implement 64-bit SYSENTER).
1042 *
1043 * 64-bit code should hence be able to write a non-canonical
1044 * value on AMD. Making the address canonical ensures that
1045 * vmentry does not fail on Intel after writing a non-canonical
1046 * value, and that something deterministic happens if the guest
1047 * invokes 64-bit SYSENTER.
1048 */
1049 msr->data = get_canonical(msr->data);
1050 }
1051 return kvm_x86_ops->set_msr(vcpu, msr);
1052 }
1053 EXPORT_SYMBOL_GPL(kvm_set_msr);
1054
1055 /*
1056 * Adapt set_msr() to msr_io()'s calling convention
1057 */
1058 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1059 {
1060 struct msr_data msr;
1061 int r;
1062
1063 msr.index = index;
1064 msr.host_initiated = true;
1065 r = kvm_get_msr(vcpu, &msr);
1066 if (r)
1067 return r;
1068
1069 *data = msr.data;
1070 return 0;
1071 }
1072
1073 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1074 {
1075 struct msr_data msr;
1076
1077 msr.data = *data;
1078 msr.index = index;
1079 msr.host_initiated = true;
1080 return kvm_set_msr(vcpu, &msr);
1081 }
1082
1083 #ifdef CONFIG_X86_64
1084 struct pvclock_gtod_data {
1085 seqcount_t seq;
1086
1087 struct { /* extract of a clocksource struct */
1088 int vclock_mode;
1089 cycle_t cycle_last;
1090 cycle_t mask;
1091 u32 mult;
1092 u32 shift;
1093 } clock;
1094
1095 u64 boot_ns;
1096 u64 nsec_base;
1097 };
1098
1099 static struct pvclock_gtod_data pvclock_gtod_data;
1100
1101 static void update_pvclock_gtod(struct timekeeper *tk)
1102 {
1103 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1104 u64 boot_ns;
1105
1106 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1107
1108 write_seqcount_begin(&vdata->seq);
1109
1110 /* copy pvclock gtod data */
1111 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1112 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1113 vdata->clock.mask = tk->tkr_mono.mask;
1114 vdata->clock.mult = tk->tkr_mono.mult;
1115 vdata->clock.shift = tk->tkr_mono.shift;
1116
1117 vdata->boot_ns = boot_ns;
1118 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1119
1120 write_seqcount_end(&vdata->seq);
1121 }
1122 #endif
1123
1124 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1125 {
1126 /*
1127 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1128 * vcpu_enter_guest. This function is only called from
1129 * the physical CPU that is running vcpu.
1130 */
1131 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1132 }
1133
1134 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1135 {
1136 int version;
1137 int r;
1138 struct pvclock_wall_clock wc;
1139 struct timespec boot;
1140
1141 if (!wall_clock)
1142 return;
1143
1144 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1145 if (r)
1146 return;
1147
1148 if (version & 1)
1149 ++version; /* first time write, random junk */
1150
1151 ++version;
1152
1153 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1154
1155 /*
1156 * The guest calculates current wall clock time by adding
1157 * system time (updated by kvm_guest_time_update below) to the
1158 * wall clock specified here. guest system time equals host
1159 * system time for us, thus we must fill in host boot time here.
1160 */
1161 getboottime(&boot);
1162
1163 if (kvm->arch.kvmclock_offset) {
1164 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1165 boot = timespec_sub(boot, ts);
1166 }
1167 wc.sec = boot.tv_sec;
1168 wc.nsec = boot.tv_nsec;
1169 wc.version = version;
1170
1171 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1172
1173 version++;
1174 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1175 }
1176
1177 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1178 {
1179 uint32_t quotient, remainder;
1180
1181 /* Don't try to replace with do_div(), this one calculates
1182 * "(dividend << 32) / divisor" */
1183 __asm__ ( "divl %4"
1184 : "=a" (quotient), "=d" (remainder)
1185 : "0" (0), "1" (dividend), "r" (divisor) );
1186 return quotient;
1187 }
1188
1189 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1190 s8 *pshift, u32 *pmultiplier)
1191 {
1192 uint64_t scaled64;
1193 int32_t shift = 0;
1194 uint64_t tps64;
1195 uint32_t tps32;
1196
1197 tps64 = base_khz * 1000LL;
1198 scaled64 = scaled_khz * 1000LL;
1199 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1200 tps64 >>= 1;
1201 shift--;
1202 }
1203
1204 tps32 = (uint32_t)tps64;
1205 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1206 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1207 scaled64 >>= 1;
1208 else
1209 tps32 <<= 1;
1210 shift++;
1211 }
1212
1213 *pshift = shift;
1214 *pmultiplier = div_frac(scaled64, tps32);
1215
1216 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1217 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1218 }
1219
1220 static inline u64 get_kernel_ns(void)
1221 {
1222 return ktime_get_boot_ns();
1223 }
1224
1225 #ifdef CONFIG_X86_64
1226 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1227 #endif
1228
1229 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1230 static unsigned long max_tsc_khz;
1231
1232 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1233 {
1234 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1235 vcpu->arch.virtual_tsc_shift);
1236 }
1237
1238 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1239 {
1240 u64 v = (u64)khz * (1000000 + ppm);
1241 do_div(v, 1000000);
1242 return v;
1243 }
1244
1245 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1246 {
1247 u32 thresh_lo, thresh_hi;
1248 int use_scaling = 0;
1249
1250 /* tsc_khz can be zero if TSC calibration fails */
1251 if (this_tsc_khz == 0)
1252 return;
1253
1254 /* Compute a scale to convert nanoseconds in TSC cycles */
1255 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1256 &vcpu->arch.virtual_tsc_shift,
1257 &vcpu->arch.virtual_tsc_mult);
1258 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1259
1260 /*
1261 * Compute the variation in TSC rate which is acceptable
1262 * within the range of tolerance and decide if the
1263 * rate being applied is within that bounds of the hardware
1264 * rate. If so, no scaling or compensation need be done.
1265 */
1266 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1267 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1268 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1269 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1270 use_scaling = 1;
1271 }
1272 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1273 }
1274
1275 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1276 {
1277 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1278 vcpu->arch.virtual_tsc_mult,
1279 vcpu->arch.virtual_tsc_shift);
1280 tsc += vcpu->arch.this_tsc_write;
1281 return tsc;
1282 }
1283
1284 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1285 {
1286 #ifdef CONFIG_X86_64
1287 bool vcpus_matched;
1288 struct kvm_arch *ka = &vcpu->kvm->arch;
1289 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1290
1291 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1292 atomic_read(&vcpu->kvm->online_vcpus));
1293
1294 /*
1295 * Once the masterclock is enabled, always perform request in
1296 * order to update it.
1297 *
1298 * In order to enable masterclock, the host clocksource must be TSC
1299 * and the vcpus need to have matched TSCs. When that happens,
1300 * perform request to enable masterclock.
1301 */
1302 if (ka->use_master_clock ||
1303 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1304 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1305
1306 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1307 atomic_read(&vcpu->kvm->online_vcpus),
1308 ka->use_master_clock, gtod->clock.vclock_mode);
1309 #endif
1310 }
1311
1312 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1313 {
1314 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1315 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1316 }
1317
1318 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1319 {
1320 struct kvm *kvm = vcpu->kvm;
1321 u64 offset, ns, elapsed;
1322 unsigned long flags;
1323 s64 usdiff;
1324 bool matched;
1325 bool already_matched;
1326 u64 data = msr->data;
1327
1328 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1329 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1330 ns = get_kernel_ns();
1331 elapsed = ns - kvm->arch.last_tsc_nsec;
1332
1333 if (vcpu->arch.virtual_tsc_khz) {
1334 int faulted = 0;
1335
1336 /* n.b - signed multiplication and division required */
1337 usdiff = data - kvm->arch.last_tsc_write;
1338 #ifdef CONFIG_X86_64
1339 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1340 #else
1341 /* do_div() only does unsigned */
1342 asm("1: idivl %[divisor]\n"
1343 "2: xor %%edx, %%edx\n"
1344 " movl $0, %[faulted]\n"
1345 "3:\n"
1346 ".section .fixup,\"ax\"\n"
1347 "4: movl $1, %[faulted]\n"
1348 " jmp 3b\n"
1349 ".previous\n"
1350
1351 _ASM_EXTABLE(1b, 4b)
1352
1353 : "=A"(usdiff), [faulted] "=r" (faulted)
1354 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1355
1356 #endif
1357 do_div(elapsed, 1000);
1358 usdiff -= elapsed;
1359 if (usdiff < 0)
1360 usdiff = -usdiff;
1361
1362 /* idivl overflow => difference is larger than USEC_PER_SEC */
1363 if (faulted)
1364 usdiff = USEC_PER_SEC;
1365 } else
1366 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1367
1368 /*
1369 * Special case: TSC write with a small delta (1 second) of virtual
1370 * cycle time against real time is interpreted as an attempt to
1371 * synchronize the CPU.
1372 *
1373 * For a reliable TSC, we can match TSC offsets, and for an unstable
1374 * TSC, we add elapsed time in this computation. We could let the
1375 * compensation code attempt to catch up if we fall behind, but
1376 * it's better to try to match offsets from the beginning.
1377 */
1378 if (usdiff < USEC_PER_SEC &&
1379 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1380 if (!check_tsc_unstable()) {
1381 offset = kvm->arch.cur_tsc_offset;
1382 pr_debug("kvm: matched tsc offset for %llu\n", data);
1383 } else {
1384 u64 delta = nsec_to_cycles(vcpu, elapsed);
1385 data += delta;
1386 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1387 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1388 }
1389 matched = true;
1390 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1391 } else {
1392 /*
1393 * We split periods of matched TSC writes into generations.
1394 * For each generation, we track the original measured
1395 * nanosecond time, offset, and write, so if TSCs are in
1396 * sync, we can match exact offset, and if not, we can match
1397 * exact software computation in compute_guest_tsc()
1398 *
1399 * These values are tracked in kvm->arch.cur_xxx variables.
1400 */
1401 kvm->arch.cur_tsc_generation++;
1402 kvm->arch.cur_tsc_nsec = ns;
1403 kvm->arch.cur_tsc_write = data;
1404 kvm->arch.cur_tsc_offset = offset;
1405 matched = false;
1406 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1407 kvm->arch.cur_tsc_generation, data);
1408 }
1409
1410 /*
1411 * We also track th most recent recorded KHZ, write and time to
1412 * allow the matching interval to be extended at each write.
1413 */
1414 kvm->arch.last_tsc_nsec = ns;
1415 kvm->arch.last_tsc_write = data;
1416 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1417
1418 vcpu->arch.last_guest_tsc = data;
1419
1420 /* Keep track of which generation this VCPU has synchronized to */
1421 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1422 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1423 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1424
1425 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1426 update_ia32_tsc_adjust_msr(vcpu, offset);
1427 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1428 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1429
1430 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1431 if (!matched) {
1432 kvm->arch.nr_vcpus_matched_tsc = 0;
1433 } else if (!already_matched) {
1434 kvm->arch.nr_vcpus_matched_tsc++;
1435 }
1436
1437 kvm_track_tsc_matching(vcpu);
1438 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1439 }
1440
1441 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1442
1443 #ifdef CONFIG_X86_64
1444
1445 static cycle_t read_tsc(void)
1446 {
1447 cycle_t ret;
1448 u64 last;
1449
1450 /*
1451 * Empirically, a fence (of type that depends on the CPU)
1452 * before rdtsc is enough to ensure that rdtsc is ordered
1453 * with respect to loads. The various CPU manuals are unclear
1454 * as to whether rdtsc can be reordered with later loads,
1455 * but no one has ever seen it happen.
1456 */
1457 rdtsc_barrier();
1458 ret = (cycle_t)vget_cycles();
1459
1460 last = pvclock_gtod_data.clock.cycle_last;
1461
1462 if (likely(ret >= last))
1463 return ret;
1464
1465 /*
1466 * GCC likes to generate cmov here, but this branch is extremely
1467 * predictable (it's just a funciton of time and the likely is
1468 * very likely) and there's a data dependence, so force GCC
1469 * to generate a branch instead. I don't barrier() because
1470 * we don't actually need a barrier, and if this function
1471 * ever gets inlined it will generate worse code.
1472 */
1473 asm volatile ("");
1474 return last;
1475 }
1476
1477 static inline u64 vgettsc(cycle_t *cycle_now)
1478 {
1479 long v;
1480 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1481
1482 *cycle_now = read_tsc();
1483
1484 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1485 return v * gtod->clock.mult;
1486 }
1487
1488 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
1489 {
1490 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1491 unsigned long seq;
1492 int mode;
1493 u64 ns;
1494
1495 do {
1496 seq = read_seqcount_begin(&gtod->seq);
1497 mode = gtod->clock.vclock_mode;
1498 ns = gtod->nsec_base;
1499 ns += vgettsc(cycle_now);
1500 ns >>= gtod->clock.shift;
1501 ns += gtod->boot_ns;
1502 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1503 *t = ns;
1504
1505 return mode;
1506 }
1507
1508 /* returns true if host is using tsc clocksource */
1509 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1510 {
1511 /* checked again under seqlock below */
1512 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1513 return false;
1514
1515 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1516 }
1517 #endif
1518
1519 /*
1520 *
1521 * Assuming a stable TSC across physical CPUS, and a stable TSC
1522 * across virtual CPUs, the following condition is possible.
1523 * Each numbered line represents an event visible to both
1524 * CPUs at the next numbered event.
1525 *
1526 * "timespecX" represents host monotonic time. "tscX" represents
1527 * RDTSC value.
1528 *
1529 * VCPU0 on CPU0 | VCPU1 on CPU1
1530 *
1531 * 1. read timespec0,tsc0
1532 * 2. | timespec1 = timespec0 + N
1533 * | tsc1 = tsc0 + M
1534 * 3. transition to guest | transition to guest
1535 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1536 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1537 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1538 *
1539 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1540 *
1541 * - ret0 < ret1
1542 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1543 * ...
1544 * - 0 < N - M => M < N
1545 *
1546 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1547 * always the case (the difference between two distinct xtime instances
1548 * might be smaller then the difference between corresponding TSC reads,
1549 * when updating guest vcpus pvclock areas).
1550 *
1551 * To avoid that problem, do not allow visibility of distinct
1552 * system_timestamp/tsc_timestamp values simultaneously: use a master
1553 * copy of host monotonic time values. Update that master copy
1554 * in lockstep.
1555 *
1556 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1557 *
1558 */
1559
1560 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1561 {
1562 #ifdef CONFIG_X86_64
1563 struct kvm_arch *ka = &kvm->arch;
1564 int vclock_mode;
1565 bool host_tsc_clocksource, vcpus_matched;
1566
1567 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1568 atomic_read(&kvm->online_vcpus));
1569
1570 /*
1571 * If the host uses TSC clock, then passthrough TSC as stable
1572 * to the guest.
1573 */
1574 host_tsc_clocksource = kvm_get_time_and_clockread(
1575 &ka->master_kernel_ns,
1576 &ka->master_cycle_now);
1577
1578 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1579 && !backwards_tsc_observed
1580 && !ka->boot_vcpu_runs_old_kvmclock;
1581
1582 if (ka->use_master_clock)
1583 atomic_set(&kvm_guest_has_master_clock, 1);
1584
1585 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1586 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1587 vcpus_matched);
1588 #endif
1589 }
1590
1591 static void kvm_gen_update_masterclock(struct kvm *kvm)
1592 {
1593 #ifdef CONFIG_X86_64
1594 int i;
1595 struct kvm_vcpu *vcpu;
1596 struct kvm_arch *ka = &kvm->arch;
1597
1598 spin_lock(&ka->pvclock_gtod_sync_lock);
1599 kvm_make_mclock_inprogress_request(kvm);
1600 /* no guest entries from this point */
1601 pvclock_update_vm_gtod_copy(kvm);
1602
1603 kvm_for_each_vcpu(i, vcpu, kvm)
1604 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1605
1606 /* guest entries allowed */
1607 kvm_for_each_vcpu(i, vcpu, kvm)
1608 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1609
1610 spin_unlock(&ka->pvclock_gtod_sync_lock);
1611 #endif
1612 }
1613
1614 static int kvm_guest_time_update(struct kvm_vcpu *v)
1615 {
1616 unsigned long flags, this_tsc_khz;
1617 struct kvm_vcpu_arch *vcpu = &v->arch;
1618 struct kvm_arch *ka = &v->kvm->arch;
1619 s64 kernel_ns;
1620 u64 tsc_timestamp, host_tsc;
1621 struct pvclock_vcpu_time_info guest_hv_clock;
1622 u8 pvclock_flags;
1623 bool use_master_clock;
1624
1625 kernel_ns = 0;
1626 host_tsc = 0;
1627
1628 /*
1629 * If the host uses TSC clock, then passthrough TSC as stable
1630 * to the guest.
1631 */
1632 spin_lock(&ka->pvclock_gtod_sync_lock);
1633 use_master_clock = ka->use_master_clock;
1634 if (use_master_clock) {
1635 host_tsc = ka->master_cycle_now;
1636 kernel_ns = ka->master_kernel_ns;
1637 }
1638 spin_unlock(&ka->pvclock_gtod_sync_lock);
1639
1640 /* Keep irq disabled to prevent changes to the clock */
1641 local_irq_save(flags);
1642 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1643 if (unlikely(this_tsc_khz == 0)) {
1644 local_irq_restore(flags);
1645 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1646 return 1;
1647 }
1648 if (!use_master_clock) {
1649 host_tsc = native_read_tsc();
1650 kernel_ns = get_kernel_ns();
1651 }
1652
1653 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1654
1655 /*
1656 * We may have to catch up the TSC to match elapsed wall clock
1657 * time for two reasons, even if kvmclock is used.
1658 * 1) CPU could have been running below the maximum TSC rate
1659 * 2) Broken TSC compensation resets the base at each VCPU
1660 * entry to avoid unknown leaps of TSC even when running
1661 * again on the same CPU. This may cause apparent elapsed
1662 * time to disappear, and the guest to stand still or run
1663 * very slowly.
1664 */
1665 if (vcpu->tsc_catchup) {
1666 u64 tsc = compute_guest_tsc(v, kernel_ns);
1667 if (tsc > tsc_timestamp) {
1668 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1669 tsc_timestamp = tsc;
1670 }
1671 }
1672
1673 local_irq_restore(flags);
1674
1675 if (!vcpu->pv_time_enabled)
1676 return 0;
1677
1678 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1679 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1680 &vcpu->hv_clock.tsc_shift,
1681 &vcpu->hv_clock.tsc_to_system_mul);
1682 vcpu->hw_tsc_khz = this_tsc_khz;
1683 }
1684
1685 /* With all the info we got, fill in the values */
1686 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1687 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1688 vcpu->last_guest_tsc = tsc_timestamp;
1689
1690 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1691 &guest_hv_clock, sizeof(guest_hv_clock))))
1692 return 0;
1693
1694 /* This VCPU is paused, but it's legal for a guest to read another
1695 * VCPU's kvmclock, so we really have to follow the specification where
1696 * it says that version is odd if data is being modified, and even after
1697 * it is consistent.
1698 *
1699 * Version field updates must be kept separate. This is because
1700 * kvm_write_guest_cached might use a "rep movs" instruction, and
1701 * writes within a string instruction are weakly ordered. So there
1702 * are three writes overall.
1703 *
1704 * As a small optimization, only write the version field in the first
1705 * and third write. The vcpu->pv_time cache is still valid, because the
1706 * version field is the first in the struct.
1707 */
1708 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1709
1710 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1711 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1712 &vcpu->hv_clock,
1713 sizeof(vcpu->hv_clock.version));
1714
1715 smp_wmb();
1716
1717 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1718 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1719
1720 if (vcpu->pvclock_set_guest_stopped_request) {
1721 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1722 vcpu->pvclock_set_guest_stopped_request = false;
1723 }
1724
1725 pvclock_flags |= PVCLOCK_COUNTS_FROM_ZERO;
1726
1727 /* If the host uses TSC clocksource, then it is stable */
1728 if (use_master_clock)
1729 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1730
1731 vcpu->hv_clock.flags = pvclock_flags;
1732
1733 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1734
1735 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1736 &vcpu->hv_clock,
1737 sizeof(vcpu->hv_clock));
1738
1739 smp_wmb();
1740
1741 vcpu->hv_clock.version++;
1742 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1743 &vcpu->hv_clock,
1744 sizeof(vcpu->hv_clock.version));
1745 return 0;
1746 }
1747
1748 /*
1749 * kvmclock updates which are isolated to a given vcpu, such as
1750 * vcpu->cpu migration, should not allow system_timestamp from
1751 * the rest of the vcpus to remain static. Otherwise ntp frequency
1752 * correction applies to one vcpu's system_timestamp but not
1753 * the others.
1754 *
1755 * So in those cases, request a kvmclock update for all vcpus.
1756 * We need to rate-limit these requests though, as they can
1757 * considerably slow guests that have a large number of vcpus.
1758 * The time for a remote vcpu to update its kvmclock is bound
1759 * by the delay we use to rate-limit the updates.
1760 */
1761
1762 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1763
1764 static void kvmclock_update_fn(struct work_struct *work)
1765 {
1766 int i;
1767 struct delayed_work *dwork = to_delayed_work(work);
1768 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1769 kvmclock_update_work);
1770 struct kvm *kvm = container_of(ka, struct kvm, arch);
1771 struct kvm_vcpu *vcpu;
1772
1773 kvm_for_each_vcpu(i, vcpu, kvm) {
1774 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1775 kvm_vcpu_kick(vcpu);
1776 }
1777 }
1778
1779 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1780 {
1781 struct kvm *kvm = v->kvm;
1782
1783 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1784 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1785 KVMCLOCK_UPDATE_DELAY);
1786 }
1787
1788 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1789
1790 static void kvmclock_sync_fn(struct work_struct *work)
1791 {
1792 struct delayed_work *dwork = to_delayed_work(work);
1793 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1794 kvmclock_sync_work);
1795 struct kvm *kvm = container_of(ka, struct kvm, arch);
1796
1797 if (!kvmclock_periodic_sync)
1798 return;
1799
1800 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1801 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1802 KVMCLOCK_SYNC_PERIOD);
1803 }
1804
1805 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1806 {
1807 u64 mcg_cap = vcpu->arch.mcg_cap;
1808 unsigned bank_num = mcg_cap & 0xff;
1809
1810 switch (msr) {
1811 case MSR_IA32_MCG_STATUS:
1812 vcpu->arch.mcg_status = data;
1813 break;
1814 case MSR_IA32_MCG_CTL:
1815 if (!(mcg_cap & MCG_CTL_P))
1816 return 1;
1817 if (data != 0 && data != ~(u64)0)
1818 return -1;
1819 vcpu->arch.mcg_ctl = data;
1820 break;
1821 default:
1822 if (msr >= MSR_IA32_MC0_CTL &&
1823 msr < MSR_IA32_MCx_CTL(bank_num)) {
1824 u32 offset = msr - MSR_IA32_MC0_CTL;
1825 /* only 0 or all 1s can be written to IA32_MCi_CTL
1826 * some Linux kernels though clear bit 10 in bank 4 to
1827 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1828 * this to avoid an uncatched #GP in the guest
1829 */
1830 if ((offset & 0x3) == 0 &&
1831 data != 0 && (data | (1 << 10)) != ~(u64)0)
1832 return -1;
1833 vcpu->arch.mce_banks[offset] = data;
1834 break;
1835 }
1836 return 1;
1837 }
1838 return 0;
1839 }
1840
1841 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1842 {
1843 struct kvm *kvm = vcpu->kvm;
1844 int lm = is_long_mode(vcpu);
1845 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1846 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1847 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1848 : kvm->arch.xen_hvm_config.blob_size_32;
1849 u32 page_num = data & ~PAGE_MASK;
1850 u64 page_addr = data & PAGE_MASK;
1851 u8 *page;
1852 int r;
1853
1854 r = -E2BIG;
1855 if (page_num >= blob_size)
1856 goto out;
1857 r = -ENOMEM;
1858 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1859 if (IS_ERR(page)) {
1860 r = PTR_ERR(page);
1861 goto out;
1862 }
1863 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
1864 goto out_free;
1865 r = 0;
1866 out_free:
1867 kfree(page);
1868 out:
1869 return r;
1870 }
1871
1872 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1873 {
1874 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1875 }
1876
1877 static bool kvm_hv_msr_partition_wide(u32 msr)
1878 {
1879 bool r = false;
1880 switch (msr) {
1881 case HV_X64_MSR_GUEST_OS_ID:
1882 case HV_X64_MSR_HYPERCALL:
1883 case HV_X64_MSR_REFERENCE_TSC:
1884 case HV_X64_MSR_TIME_REF_COUNT:
1885 r = true;
1886 break;
1887 }
1888
1889 return r;
1890 }
1891
1892 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1893 {
1894 struct kvm *kvm = vcpu->kvm;
1895
1896 switch (msr) {
1897 case HV_X64_MSR_GUEST_OS_ID:
1898 kvm->arch.hv_guest_os_id = data;
1899 /* setting guest os id to zero disables hypercall page */
1900 if (!kvm->arch.hv_guest_os_id)
1901 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1902 break;
1903 case HV_X64_MSR_HYPERCALL: {
1904 u64 gfn;
1905 unsigned long addr;
1906 u8 instructions[4];
1907
1908 /* if guest os id is not set hypercall should remain disabled */
1909 if (!kvm->arch.hv_guest_os_id)
1910 break;
1911 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1912 kvm->arch.hv_hypercall = data;
1913 break;
1914 }
1915 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1916 addr = gfn_to_hva(kvm, gfn);
1917 if (kvm_is_error_hva(addr))
1918 return 1;
1919 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1920 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1921 if (__copy_to_user((void __user *)addr, instructions, 4))
1922 return 1;
1923 kvm->arch.hv_hypercall = data;
1924 mark_page_dirty(kvm, gfn);
1925 break;
1926 }
1927 case HV_X64_MSR_REFERENCE_TSC: {
1928 u64 gfn;
1929 HV_REFERENCE_TSC_PAGE tsc_ref;
1930 memset(&tsc_ref, 0, sizeof(tsc_ref));
1931 kvm->arch.hv_tsc_page = data;
1932 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1933 break;
1934 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1935 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
1936 &tsc_ref, sizeof(tsc_ref)))
1937 return 1;
1938 mark_page_dirty(kvm, gfn);
1939 break;
1940 }
1941 default:
1942 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1943 "data 0x%llx\n", msr, data);
1944 return 1;
1945 }
1946 return 0;
1947 }
1948
1949 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1950 {
1951 switch (msr) {
1952 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1953 u64 gfn;
1954 unsigned long addr;
1955
1956 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1957 vcpu->arch.hv_vapic = data;
1958 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
1959 return 1;
1960 break;
1961 }
1962 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1963 addr = kvm_vcpu_gfn_to_hva(vcpu, gfn);
1964 if (kvm_is_error_hva(addr))
1965 return 1;
1966 if (__clear_user((void __user *)addr, PAGE_SIZE))
1967 return 1;
1968 vcpu->arch.hv_vapic = data;
1969 kvm_vcpu_mark_page_dirty(vcpu, gfn);
1970 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
1971 return 1;
1972 break;
1973 }
1974 case HV_X64_MSR_EOI:
1975 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1976 case HV_X64_MSR_ICR:
1977 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1978 case HV_X64_MSR_TPR:
1979 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1980 default:
1981 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1982 "data 0x%llx\n", msr, data);
1983 return 1;
1984 }
1985
1986 return 0;
1987 }
1988
1989 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1990 {
1991 gpa_t gpa = data & ~0x3f;
1992
1993 /* Bits 2:5 are reserved, Should be zero */
1994 if (data & 0x3c)
1995 return 1;
1996
1997 vcpu->arch.apf.msr_val = data;
1998
1999 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2000 kvm_clear_async_pf_completion_queue(vcpu);
2001 kvm_async_pf_hash_reset(vcpu);
2002 return 0;
2003 }
2004
2005 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2006 sizeof(u32)))
2007 return 1;
2008
2009 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2010 kvm_async_pf_wakeup_all(vcpu);
2011 return 0;
2012 }
2013
2014 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2015 {
2016 vcpu->arch.pv_time_enabled = false;
2017 }
2018
2019 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2020 {
2021 u64 delta;
2022
2023 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2024 return;
2025
2026 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2027 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2028 vcpu->arch.st.accum_steal = delta;
2029 }
2030
2031 static void record_steal_time(struct kvm_vcpu *vcpu)
2032 {
2033 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2034 return;
2035
2036 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2037 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2038 return;
2039
2040 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2041 vcpu->arch.st.steal.version += 2;
2042 vcpu->arch.st.accum_steal = 0;
2043
2044 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2045 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2046 }
2047
2048 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2049 {
2050 bool pr = false;
2051 u32 msr = msr_info->index;
2052 u64 data = msr_info->data;
2053
2054 switch (msr) {
2055 case MSR_AMD64_NB_CFG:
2056 case MSR_IA32_UCODE_REV:
2057 case MSR_IA32_UCODE_WRITE:
2058 case MSR_VM_HSAVE_PA:
2059 case MSR_AMD64_PATCH_LOADER:
2060 case MSR_AMD64_BU_CFG2:
2061 break;
2062
2063 case MSR_EFER:
2064 return set_efer(vcpu, data);
2065 case MSR_K7_HWCR:
2066 data &= ~(u64)0x40; /* ignore flush filter disable */
2067 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2068 data &= ~(u64)0x8; /* ignore TLB cache disable */
2069 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2070 if (data != 0) {
2071 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2072 data);
2073 return 1;
2074 }
2075 break;
2076 case MSR_FAM10H_MMIO_CONF_BASE:
2077 if (data != 0) {
2078 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2079 "0x%llx\n", data);
2080 return 1;
2081 }
2082 break;
2083 case MSR_IA32_DEBUGCTLMSR:
2084 if (!data) {
2085 /* We support the non-activated case already */
2086 break;
2087 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2088 /* Values other than LBR and BTF are vendor-specific,
2089 thus reserved and should throw a #GP */
2090 return 1;
2091 }
2092 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2093 __func__, data);
2094 break;
2095 case 0x200 ... 0x2ff:
2096 return kvm_mtrr_set_msr(vcpu, msr, data);
2097 case MSR_IA32_APICBASE:
2098 return kvm_set_apic_base(vcpu, msr_info);
2099 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2100 return kvm_x2apic_msr_write(vcpu, msr, data);
2101 case MSR_IA32_TSCDEADLINE:
2102 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2103 break;
2104 case MSR_IA32_TSC_ADJUST:
2105 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2106 if (!msr_info->host_initiated) {
2107 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2108 adjust_tsc_offset_guest(vcpu, adj);
2109 }
2110 vcpu->arch.ia32_tsc_adjust_msr = data;
2111 }
2112 break;
2113 case MSR_IA32_MISC_ENABLE:
2114 vcpu->arch.ia32_misc_enable_msr = data;
2115 break;
2116 case MSR_IA32_SMBASE:
2117 if (!msr_info->host_initiated)
2118 return 1;
2119 vcpu->arch.smbase = data;
2120 break;
2121 case MSR_KVM_WALL_CLOCK_NEW:
2122 case MSR_KVM_WALL_CLOCK:
2123 vcpu->kvm->arch.wall_clock = data;
2124 kvm_write_wall_clock(vcpu->kvm, data);
2125 break;
2126 case MSR_KVM_SYSTEM_TIME_NEW:
2127 case MSR_KVM_SYSTEM_TIME: {
2128 u64 gpa_offset;
2129 struct kvm_arch *ka = &vcpu->kvm->arch;
2130
2131 kvmclock_reset(vcpu);
2132
2133 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2134 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2135
2136 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2137 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2138 &vcpu->requests);
2139
2140 ka->boot_vcpu_runs_old_kvmclock = tmp;
2141
2142 ka->kvmclock_offset = -get_kernel_ns();
2143 }
2144
2145 vcpu->arch.time = data;
2146 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2147
2148 /* we verify if the enable bit is set... */
2149 if (!(data & 1))
2150 break;
2151
2152 gpa_offset = data & ~(PAGE_MASK | 1);
2153
2154 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2155 &vcpu->arch.pv_time, data & ~1ULL,
2156 sizeof(struct pvclock_vcpu_time_info)))
2157 vcpu->arch.pv_time_enabled = false;
2158 else
2159 vcpu->arch.pv_time_enabled = true;
2160
2161 break;
2162 }
2163 case MSR_KVM_ASYNC_PF_EN:
2164 if (kvm_pv_enable_async_pf(vcpu, data))
2165 return 1;
2166 break;
2167 case MSR_KVM_STEAL_TIME:
2168
2169 if (unlikely(!sched_info_on()))
2170 return 1;
2171
2172 if (data & KVM_STEAL_RESERVED_MASK)
2173 return 1;
2174
2175 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2176 data & KVM_STEAL_VALID_BITS,
2177 sizeof(struct kvm_steal_time)))
2178 return 1;
2179
2180 vcpu->arch.st.msr_val = data;
2181
2182 if (!(data & KVM_MSR_ENABLED))
2183 break;
2184
2185 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2186
2187 preempt_disable();
2188 accumulate_steal_time(vcpu);
2189 preempt_enable();
2190
2191 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2192
2193 break;
2194 case MSR_KVM_PV_EOI_EN:
2195 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2196 return 1;
2197 break;
2198
2199 case MSR_IA32_MCG_CTL:
2200 case MSR_IA32_MCG_STATUS:
2201 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2202 return set_msr_mce(vcpu, msr, data);
2203
2204 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2205 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2206 pr = true; /* fall through */
2207 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2208 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2209 if (kvm_pmu_is_valid_msr(vcpu, msr))
2210 return kvm_pmu_set_msr(vcpu, msr_info);
2211
2212 if (pr || data != 0)
2213 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2214 "0x%x data 0x%llx\n", msr, data);
2215 break;
2216 case MSR_K7_CLK_CTL:
2217 /*
2218 * Ignore all writes to this no longer documented MSR.
2219 * Writes are only relevant for old K7 processors,
2220 * all pre-dating SVM, but a recommended workaround from
2221 * AMD for these chips. It is possible to specify the
2222 * affected processor models on the command line, hence
2223 * the need to ignore the workaround.
2224 */
2225 break;
2226 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2227 if (kvm_hv_msr_partition_wide(msr)) {
2228 int r;
2229 mutex_lock(&vcpu->kvm->lock);
2230 r = set_msr_hyperv_pw(vcpu, msr, data);
2231 mutex_unlock(&vcpu->kvm->lock);
2232 return r;
2233 } else
2234 return set_msr_hyperv(vcpu, msr, data);
2235 break;
2236 case MSR_IA32_BBL_CR_CTL3:
2237 /* Drop writes to this legacy MSR -- see rdmsr
2238 * counterpart for further detail.
2239 */
2240 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2241 break;
2242 case MSR_AMD64_OSVW_ID_LENGTH:
2243 if (!guest_cpuid_has_osvw(vcpu))
2244 return 1;
2245 vcpu->arch.osvw.length = data;
2246 break;
2247 case MSR_AMD64_OSVW_STATUS:
2248 if (!guest_cpuid_has_osvw(vcpu))
2249 return 1;
2250 vcpu->arch.osvw.status = data;
2251 break;
2252 default:
2253 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2254 return xen_hvm_config(vcpu, data);
2255 if (kvm_pmu_is_valid_msr(vcpu, msr))
2256 return kvm_pmu_set_msr(vcpu, msr_info);
2257 if (!ignore_msrs) {
2258 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2259 msr, data);
2260 return 1;
2261 } else {
2262 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2263 msr, data);
2264 break;
2265 }
2266 }
2267 return 0;
2268 }
2269 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2270
2271
2272 /*
2273 * Reads an msr value (of 'msr_index') into 'pdata'.
2274 * Returns 0 on success, non-0 otherwise.
2275 * Assumes vcpu_load() was already called.
2276 */
2277 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2278 {
2279 return kvm_x86_ops->get_msr(vcpu, msr);
2280 }
2281 EXPORT_SYMBOL_GPL(kvm_get_msr);
2282
2283 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2284 {
2285 u64 data;
2286 u64 mcg_cap = vcpu->arch.mcg_cap;
2287 unsigned bank_num = mcg_cap & 0xff;
2288
2289 switch (msr) {
2290 case MSR_IA32_P5_MC_ADDR:
2291 case MSR_IA32_P5_MC_TYPE:
2292 data = 0;
2293 break;
2294 case MSR_IA32_MCG_CAP:
2295 data = vcpu->arch.mcg_cap;
2296 break;
2297 case MSR_IA32_MCG_CTL:
2298 if (!(mcg_cap & MCG_CTL_P))
2299 return 1;
2300 data = vcpu->arch.mcg_ctl;
2301 break;
2302 case MSR_IA32_MCG_STATUS:
2303 data = vcpu->arch.mcg_status;
2304 break;
2305 default:
2306 if (msr >= MSR_IA32_MC0_CTL &&
2307 msr < MSR_IA32_MCx_CTL(bank_num)) {
2308 u32 offset = msr - MSR_IA32_MC0_CTL;
2309 data = vcpu->arch.mce_banks[offset];
2310 break;
2311 }
2312 return 1;
2313 }
2314 *pdata = data;
2315 return 0;
2316 }
2317
2318 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2319 {
2320 u64 data = 0;
2321 struct kvm *kvm = vcpu->kvm;
2322
2323 switch (msr) {
2324 case HV_X64_MSR_GUEST_OS_ID:
2325 data = kvm->arch.hv_guest_os_id;
2326 break;
2327 case HV_X64_MSR_HYPERCALL:
2328 data = kvm->arch.hv_hypercall;
2329 break;
2330 case HV_X64_MSR_TIME_REF_COUNT: {
2331 data =
2332 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2333 break;
2334 }
2335 case HV_X64_MSR_REFERENCE_TSC:
2336 data = kvm->arch.hv_tsc_page;
2337 break;
2338 default:
2339 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2340 return 1;
2341 }
2342
2343 *pdata = data;
2344 return 0;
2345 }
2346
2347 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2348 {
2349 u64 data = 0;
2350
2351 switch (msr) {
2352 case HV_X64_MSR_VP_INDEX: {
2353 int r;
2354 struct kvm_vcpu *v;
2355 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2356 if (v == vcpu) {
2357 data = r;
2358 break;
2359 }
2360 }
2361 break;
2362 }
2363 case HV_X64_MSR_EOI:
2364 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2365 case HV_X64_MSR_ICR:
2366 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2367 case HV_X64_MSR_TPR:
2368 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2369 case HV_X64_MSR_APIC_ASSIST_PAGE:
2370 data = vcpu->arch.hv_vapic;
2371 break;
2372 default:
2373 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2374 return 1;
2375 }
2376 *pdata = data;
2377 return 0;
2378 }
2379
2380 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2381 {
2382 switch (msr_info->index) {
2383 case MSR_IA32_PLATFORM_ID:
2384 case MSR_IA32_EBL_CR_POWERON:
2385 case MSR_IA32_DEBUGCTLMSR:
2386 case MSR_IA32_LASTBRANCHFROMIP:
2387 case MSR_IA32_LASTBRANCHTOIP:
2388 case MSR_IA32_LASTINTFROMIP:
2389 case MSR_IA32_LASTINTTOIP:
2390 case MSR_K8_SYSCFG:
2391 case MSR_K7_HWCR:
2392 case MSR_VM_HSAVE_PA:
2393 case MSR_K8_INT_PENDING_MSG:
2394 case MSR_AMD64_NB_CFG:
2395 case MSR_FAM10H_MMIO_CONF_BASE:
2396 case MSR_AMD64_BU_CFG2:
2397 msr_info->data = 0;
2398 break;
2399 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2400 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2401 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2402 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2403 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2404 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2405 msr_info->data = 0;
2406 break;
2407 case MSR_IA32_UCODE_REV:
2408 msr_info->data = 0x100000000ULL;
2409 break;
2410 case MSR_MTRRcap:
2411 case 0x200 ... 0x2ff:
2412 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2413 case 0xcd: /* fsb frequency */
2414 msr_info->data = 3;
2415 break;
2416 /*
2417 * MSR_EBC_FREQUENCY_ID
2418 * Conservative value valid for even the basic CPU models.
2419 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2420 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2421 * and 266MHz for model 3, or 4. Set Core Clock
2422 * Frequency to System Bus Frequency Ratio to 1 (bits
2423 * 31:24) even though these are only valid for CPU
2424 * models > 2, however guests may end up dividing or
2425 * multiplying by zero otherwise.
2426 */
2427 case MSR_EBC_FREQUENCY_ID:
2428 msr_info->data = 1 << 24;
2429 break;
2430 case MSR_IA32_APICBASE:
2431 msr_info->data = kvm_get_apic_base(vcpu);
2432 break;
2433 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2434 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2435 break;
2436 case MSR_IA32_TSCDEADLINE:
2437 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2438 break;
2439 case MSR_IA32_TSC_ADJUST:
2440 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2441 break;
2442 case MSR_IA32_MISC_ENABLE:
2443 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2444 break;
2445 case MSR_IA32_SMBASE:
2446 if (!msr_info->host_initiated)
2447 return 1;
2448 msr_info->data = vcpu->arch.smbase;
2449 break;
2450 case MSR_IA32_PERF_STATUS:
2451 /* TSC increment by tick */
2452 msr_info->data = 1000ULL;
2453 /* CPU multiplier */
2454 msr_info->data |= (((uint64_t)4ULL) << 40);
2455 break;
2456 case MSR_EFER:
2457 msr_info->data = vcpu->arch.efer;
2458 break;
2459 case MSR_KVM_WALL_CLOCK:
2460 case MSR_KVM_WALL_CLOCK_NEW:
2461 msr_info->data = vcpu->kvm->arch.wall_clock;
2462 break;
2463 case MSR_KVM_SYSTEM_TIME:
2464 case MSR_KVM_SYSTEM_TIME_NEW:
2465 msr_info->data = vcpu->arch.time;
2466 break;
2467 case MSR_KVM_ASYNC_PF_EN:
2468 msr_info->data = vcpu->arch.apf.msr_val;
2469 break;
2470 case MSR_KVM_STEAL_TIME:
2471 msr_info->data = vcpu->arch.st.msr_val;
2472 break;
2473 case MSR_KVM_PV_EOI_EN:
2474 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2475 break;
2476 case MSR_IA32_P5_MC_ADDR:
2477 case MSR_IA32_P5_MC_TYPE:
2478 case MSR_IA32_MCG_CAP:
2479 case MSR_IA32_MCG_CTL:
2480 case MSR_IA32_MCG_STATUS:
2481 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2482 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2483 case MSR_K7_CLK_CTL:
2484 /*
2485 * Provide expected ramp-up count for K7. All other
2486 * are set to zero, indicating minimum divisors for
2487 * every field.
2488 *
2489 * This prevents guest kernels on AMD host with CPU
2490 * type 6, model 8 and higher from exploding due to
2491 * the rdmsr failing.
2492 */
2493 msr_info->data = 0x20000000;
2494 break;
2495 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2496 if (kvm_hv_msr_partition_wide(msr_info->index)) {
2497 int r;
2498 mutex_lock(&vcpu->kvm->lock);
2499 r = get_msr_hyperv_pw(vcpu, msr_info->index, &msr_info->data);
2500 mutex_unlock(&vcpu->kvm->lock);
2501 return r;
2502 } else
2503 return get_msr_hyperv(vcpu, msr_info->index, &msr_info->data);
2504 break;
2505 case MSR_IA32_BBL_CR_CTL3:
2506 /* This legacy MSR exists but isn't fully documented in current
2507 * silicon. It is however accessed by winxp in very narrow
2508 * scenarios where it sets bit #19, itself documented as
2509 * a "reserved" bit. Best effort attempt to source coherent
2510 * read data here should the balance of the register be
2511 * interpreted by the guest:
2512 *
2513 * L2 cache control register 3: 64GB range, 256KB size,
2514 * enabled, latency 0x1, configured
2515 */
2516 msr_info->data = 0xbe702111;
2517 break;
2518 case MSR_AMD64_OSVW_ID_LENGTH:
2519 if (!guest_cpuid_has_osvw(vcpu))
2520 return 1;
2521 msr_info->data = vcpu->arch.osvw.length;
2522 break;
2523 case MSR_AMD64_OSVW_STATUS:
2524 if (!guest_cpuid_has_osvw(vcpu))
2525 return 1;
2526 msr_info->data = vcpu->arch.osvw.status;
2527 break;
2528 default:
2529 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2530 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2531 if (!ignore_msrs) {
2532 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
2533 return 1;
2534 } else {
2535 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2536 msr_info->data = 0;
2537 }
2538 break;
2539 }
2540 return 0;
2541 }
2542 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2543
2544 /*
2545 * Read or write a bunch of msrs. All parameters are kernel addresses.
2546 *
2547 * @return number of msrs set successfully.
2548 */
2549 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2550 struct kvm_msr_entry *entries,
2551 int (*do_msr)(struct kvm_vcpu *vcpu,
2552 unsigned index, u64 *data))
2553 {
2554 int i, idx;
2555
2556 idx = srcu_read_lock(&vcpu->kvm->srcu);
2557 for (i = 0; i < msrs->nmsrs; ++i)
2558 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2559 break;
2560 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2561
2562 return i;
2563 }
2564
2565 /*
2566 * Read or write a bunch of msrs. Parameters are user addresses.
2567 *
2568 * @return number of msrs set successfully.
2569 */
2570 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2571 int (*do_msr)(struct kvm_vcpu *vcpu,
2572 unsigned index, u64 *data),
2573 int writeback)
2574 {
2575 struct kvm_msrs msrs;
2576 struct kvm_msr_entry *entries;
2577 int r, n;
2578 unsigned size;
2579
2580 r = -EFAULT;
2581 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2582 goto out;
2583
2584 r = -E2BIG;
2585 if (msrs.nmsrs >= MAX_IO_MSRS)
2586 goto out;
2587
2588 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2589 entries = memdup_user(user_msrs->entries, size);
2590 if (IS_ERR(entries)) {
2591 r = PTR_ERR(entries);
2592 goto out;
2593 }
2594
2595 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2596 if (r < 0)
2597 goto out_free;
2598
2599 r = -EFAULT;
2600 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2601 goto out_free;
2602
2603 r = n;
2604
2605 out_free:
2606 kfree(entries);
2607 out:
2608 return r;
2609 }
2610
2611 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2612 {
2613 int r;
2614
2615 switch (ext) {
2616 case KVM_CAP_IRQCHIP:
2617 case KVM_CAP_HLT:
2618 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2619 case KVM_CAP_SET_TSS_ADDR:
2620 case KVM_CAP_EXT_CPUID:
2621 case KVM_CAP_EXT_EMUL_CPUID:
2622 case KVM_CAP_CLOCKSOURCE:
2623 case KVM_CAP_PIT:
2624 case KVM_CAP_NOP_IO_DELAY:
2625 case KVM_CAP_MP_STATE:
2626 case KVM_CAP_SYNC_MMU:
2627 case KVM_CAP_USER_NMI:
2628 case KVM_CAP_REINJECT_CONTROL:
2629 case KVM_CAP_IRQ_INJECT_STATUS:
2630 case KVM_CAP_IOEVENTFD:
2631 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2632 case KVM_CAP_PIT2:
2633 case KVM_CAP_PIT_STATE2:
2634 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2635 case KVM_CAP_XEN_HVM:
2636 case KVM_CAP_ADJUST_CLOCK:
2637 case KVM_CAP_VCPU_EVENTS:
2638 case KVM_CAP_HYPERV:
2639 case KVM_CAP_HYPERV_VAPIC:
2640 case KVM_CAP_HYPERV_SPIN:
2641 case KVM_CAP_PCI_SEGMENT:
2642 case KVM_CAP_DEBUGREGS:
2643 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2644 case KVM_CAP_XSAVE:
2645 case KVM_CAP_ASYNC_PF:
2646 case KVM_CAP_GET_TSC_KHZ:
2647 case KVM_CAP_KVMCLOCK_CTRL:
2648 case KVM_CAP_READONLY_MEM:
2649 case KVM_CAP_HYPERV_TIME:
2650 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2651 case KVM_CAP_TSC_DEADLINE_TIMER:
2652 case KVM_CAP_ENABLE_CAP_VM:
2653 case KVM_CAP_DISABLE_QUIRKS:
2654 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2655 case KVM_CAP_ASSIGN_DEV_IRQ:
2656 case KVM_CAP_PCI_2_3:
2657 #endif
2658 r = 1;
2659 break;
2660 case KVM_CAP_X86_SMM:
2661 /* SMBASE is usually relocated above 1M on modern chipsets,
2662 * and SMM handlers might indeed rely on 4G segment limits,
2663 * so do not report SMM to be available if real mode is
2664 * emulated via vm86 mode. Still, do not go to great lengths
2665 * to avoid userspace's usage of the feature, because it is a
2666 * fringe case that is not enabled except via specific settings
2667 * of the module parameters.
2668 */
2669 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2670 break;
2671 case KVM_CAP_COALESCED_MMIO:
2672 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2673 break;
2674 case KVM_CAP_VAPIC:
2675 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2676 break;
2677 case KVM_CAP_NR_VCPUS:
2678 r = KVM_SOFT_MAX_VCPUS;
2679 break;
2680 case KVM_CAP_MAX_VCPUS:
2681 r = KVM_MAX_VCPUS;
2682 break;
2683 case KVM_CAP_NR_MEMSLOTS:
2684 r = KVM_USER_MEM_SLOTS;
2685 break;
2686 case KVM_CAP_PV_MMU: /* obsolete */
2687 r = 0;
2688 break;
2689 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2690 case KVM_CAP_IOMMU:
2691 r = iommu_present(&pci_bus_type);
2692 break;
2693 #endif
2694 case KVM_CAP_MCE:
2695 r = KVM_MAX_MCE_BANKS;
2696 break;
2697 case KVM_CAP_XCRS:
2698 r = cpu_has_xsave;
2699 break;
2700 case KVM_CAP_TSC_CONTROL:
2701 r = kvm_has_tsc_control;
2702 break;
2703 default:
2704 r = 0;
2705 break;
2706 }
2707 return r;
2708
2709 }
2710
2711 long kvm_arch_dev_ioctl(struct file *filp,
2712 unsigned int ioctl, unsigned long arg)
2713 {
2714 void __user *argp = (void __user *)arg;
2715 long r;
2716
2717 switch (ioctl) {
2718 case KVM_GET_MSR_INDEX_LIST: {
2719 struct kvm_msr_list __user *user_msr_list = argp;
2720 struct kvm_msr_list msr_list;
2721 unsigned n;
2722
2723 r = -EFAULT;
2724 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2725 goto out;
2726 n = msr_list.nmsrs;
2727 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2728 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2729 goto out;
2730 r = -E2BIG;
2731 if (n < msr_list.nmsrs)
2732 goto out;
2733 r = -EFAULT;
2734 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2735 num_msrs_to_save * sizeof(u32)))
2736 goto out;
2737 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2738 &emulated_msrs,
2739 num_emulated_msrs * sizeof(u32)))
2740 goto out;
2741 r = 0;
2742 break;
2743 }
2744 case KVM_GET_SUPPORTED_CPUID:
2745 case KVM_GET_EMULATED_CPUID: {
2746 struct kvm_cpuid2 __user *cpuid_arg = argp;
2747 struct kvm_cpuid2 cpuid;
2748
2749 r = -EFAULT;
2750 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2751 goto out;
2752
2753 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2754 ioctl);
2755 if (r)
2756 goto out;
2757
2758 r = -EFAULT;
2759 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2760 goto out;
2761 r = 0;
2762 break;
2763 }
2764 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2765 u64 mce_cap;
2766
2767 mce_cap = KVM_MCE_CAP_SUPPORTED;
2768 r = -EFAULT;
2769 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2770 goto out;
2771 r = 0;
2772 break;
2773 }
2774 default:
2775 r = -EINVAL;
2776 }
2777 out:
2778 return r;
2779 }
2780
2781 static void wbinvd_ipi(void *garbage)
2782 {
2783 wbinvd();
2784 }
2785
2786 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2787 {
2788 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2789 }
2790
2791 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2792 {
2793 /* Address WBINVD may be executed by guest */
2794 if (need_emulate_wbinvd(vcpu)) {
2795 if (kvm_x86_ops->has_wbinvd_exit())
2796 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2797 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2798 smp_call_function_single(vcpu->cpu,
2799 wbinvd_ipi, NULL, 1);
2800 }
2801
2802 kvm_x86_ops->vcpu_load(vcpu, cpu);
2803
2804 /* Apply any externally detected TSC adjustments (due to suspend) */
2805 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2806 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2807 vcpu->arch.tsc_offset_adjustment = 0;
2808 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2809 }
2810
2811 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2812 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2813 native_read_tsc() - vcpu->arch.last_host_tsc;
2814 if (tsc_delta < 0)
2815 mark_tsc_unstable("KVM discovered backwards TSC");
2816 if (check_tsc_unstable()) {
2817 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2818 vcpu->arch.last_guest_tsc);
2819 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2820 vcpu->arch.tsc_catchup = 1;
2821 }
2822 /*
2823 * On a host with synchronized TSC, there is no need to update
2824 * kvmclock on vcpu->cpu migration
2825 */
2826 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2827 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2828 if (vcpu->cpu != cpu)
2829 kvm_migrate_timers(vcpu);
2830 vcpu->cpu = cpu;
2831 }
2832
2833 accumulate_steal_time(vcpu);
2834 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2835 }
2836
2837 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2838 {
2839 kvm_x86_ops->vcpu_put(vcpu);
2840 kvm_put_guest_fpu(vcpu);
2841 vcpu->arch.last_host_tsc = native_read_tsc();
2842 }
2843
2844 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2845 struct kvm_lapic_state *s)
2846 {
2847 kvm_x86_ops->sync_pir_to_irr(vcpu);
2848 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2849
2850 return 0;
2851 }
2852
2853 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2854 struct kvm_lapic_state *s)
2855 {
2856 kvm_apic_post_state_restore(vcpu, s);
2857 update_cr8_intercept(vcpu);
2858
2859 return 0;
2860 }
2861
2862 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2863 struct kvm_interrupt *irq)
2864 {
2865 if (irq->irq >= KVM_NR_INTERRUPTS)
2866 return -EINVAL;
2867 if (irqchip_in_kernel(vcpu->kvm))
2868 return -ENXIO;
2869
2870 kvm_queue_interrupt(vcpu, irq->irq, false);
2871 kvm_make_request(KVM_REQ_EVENT, vcpu);
2872
2873 return 0;
2874 }
2875
2876 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2877 {
2878 kvm_inject_nmi(vcpu);
2879
2880 return 0;
2881 }
2882
2883 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2884 {
2885 kvm_make_request(KVM_REQ_SMI, vcpu);
2886
2887 return 0;
2888 }
2889
2890 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2891 struct kvm_tpr_access_ctl *tac)
2892 {
2893 if (tac->flags)
2894 return -EINVAL;
2895 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2896 return 0;
2897 }
2898
2899 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2900 u64 mcg_cap)
2901 {
2902 int r;
2903 unsigned bank_num = mcg_cap & 0xff, bank;
2904
2905 r = -EINVAL;
2906 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2907 goto out;
2908 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2909 goto out;
2910 r = 0;
2911 vcpu->arch.mcg_cap = mcg_cap;
2912 /* Init IA32_MCG_CTL to all 1s */
2913 if (mcg_cap & MCG_CTL_P)
2914 vcpu->arch.mcg_ctl = ~(u64)0;
2915 /* Init IA32_MCi_CTL to all 1s */
2916 for (bank = 0; bank < bank_num; bank++)
2917 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2918 out:
2919 return r;
2920 }
2921
2922 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2923 struct kvm_x86_mce *mce)
2924 {
2925 u64 mcg_cap = vcpu->arch.mcg_cap;
2926 unsigned bank_num = mcg_cap & 0xff;
2927 u64 *banks = vcpu->arch.mce_banks;
2928
2929 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2930 return -EINVAL;
2931 /*
2932 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2933 * reporting is disabled
2934 */
2935 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2936 vcpu->arch.mcg_ctl != ~(u64)0)
2937 return 0;
2938 banks += 4 * mce->bank;
2939 /*
2940 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2941 * reporting is disabled for the bank
2942 */
2943 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2944 return 0;
2945 if (mce->status & MCI_STATUS_UC) {
2946 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2947 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2948 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2949 return 0;
2950 }
2951 if (banks[1] & MCI_STATUS_VAL)
2952 mce->status |= MCI_STATUS_OVER;
2953 banks[2] = mce->addr;
2954 banks[3] = mce->misc;
2955 vcpu->arch.mcg_status = mce->mcg_status;
2956 banks[1] = mce->status;
2957 kvm_queue_exception(vcpu, MC_VECTOR);
2958 } else if (!(banks[1] & MCI_STATUS_VAL)
2959 || !(banks[1] & MCI_STATUS_UC)) {
2960 if (banks[1] & MCI_STATUS_VAL)
2961 mce->status |= MCI_STATUS_OVER;
2962 banks[2] = mce->addr;
2963 banks[3] = mce->misc;
2964 banks[1] = mce->status;
2965 } else
2966 banks[1] |= MCI_STATUS_OVER;
2967 return 0;
2968 }
2969
2970 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2971 struct kvm_vcpu_events *events)
2972 {
2973 process_nmi(vcpu);
2974 events->exception.injected =
2975 vcpu->arch.exception.pending &&
2976 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2977 events->exception.nr = vcpu->arch.exception.nr;
2978 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2979 events->exception.pad = 0;
2980 events->exception.error_code = vcpu->arch.exception.error_code;
2981
2982 events->interrupt.injected =
2983 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2984 events->interrupt.nr = vcpu->arch.interrupt.nr;
2985 events->interrupt.soft = 0;
2986 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
2987
2988 events->nmi.injected = vcpu->arch.nmi_injected;
2989 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2990 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2991 events->nmi.pad = 0;
2992
2993 events->sipi_vector = 0; /* never valid when reporting to user space */
2994
2995 events->smi.smm = is_smm(vcpu);
2996 events->smi.pending = vcpu->arch.smi_pending;
2997 events->smi.smm_inside_nmi =
2998 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2999 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3000
3001 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3002 | KVM_VCPUEVENT_VALID_SHADOW
3003 | KVM_VCPUEVENT_VALID_SMM);
3004 memset(&events->reserved, 0, sizeof(events->reserved));
3005 }
3006
3007 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3008 struct kvm_vcpu_events *events)
3009 {
3010 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3011 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3012 | KVM_VCPUEVENT_VALID_SHADOW
3013 | KVM_VCPUEVENT_VALID_SMM))
3014 return -EINVAL;
3015
3016 process_nmi(vcpu);
3017 vcpu->arch.exception.pending = events->exception.injected;
3018 vcpu->arch.exception.nr = events->exception.nr;
3019 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3020 vcpu->arch.exception.error_code = events->exception.error_code;
3021
3022 vcpu->arch.interrupt.pending = events->interrupt.injected;
3023 vcpu->arch.interrupt.nr = events->interrupt.nr;
3024 vcpu->arch.interrupt.soft = events->interrupt.soft;
3025 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3026 kvm_x86_ops->set_interrupt_shadow(vcpu,
3027 events->interrupt.shadow);
3028
3029 vcpu->arch.nmi_injected = events->nmi.injected;
3030 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3031 vcpu->arch.nmi_pending = events->nmi.pending;
3032 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3033
3034 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3035 kvm_vcpu_has_lapic(vcpu))
3036 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3037
3038 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3039 if (events->smi.smm)
3040 vcpu->arch.hflags |= HF_SMM_MASK;
3041 else
3042 vcpu->arch.hflags &= ~HF_SMM_MASK;
3043 vcpu->arch.smi_pending = events->smi.pending;
3044 if (events->smi.smm_inside_nmi)
3045 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3046 else
3047 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3048 if (kvm_vcpu_has_lapic(vcpu)) {
3049 if (events->smi.latched_init)
3050 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3051 else
3052 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3053 }
3054 }
3055
3056 kvm_make_request(KVM_REQ_EVENT, vcpu);
3057
3058 return 0;
3059 }
3060
3061 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3062 struct kvm_debugregs *dbgregs)
3063 {
3064 unsigned long val;
3065
3066 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3067 kvm_get_dr(vcpu, 6, &val);
3068 dbgregs->dr6 = val;
3069 dbgregs->dr7 = vcpu->arch.dr7;
3070 dbgregs->flags = 0;
3071 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3072 }
3073
3074 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3075 struct kvm_debugregs *dbgregs)
3076 {
3077 if (dbgregs->flags)
3078 return -EINVAL;
3079
3080 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3081 kvm_update_dr0123(vcpu);
3082 vcpu->arch.dr6 = dbgregs->dr6;
3083 kvm_update_dr6(vcpu);
3084 vcpu->arch.dr7 = dbgregs->dr7;
3085 kvm_update_dr7(vcpu);
3086
3087 return 0;
3088 }
3089
3090 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3091
3092 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3093 {
3094 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3095 u64 xstate_bv = xsave->header.xfeatures;
3096 u64 valid;
3097
3098 /*
3099 * Copy legacy XSAVE area, to avoid complications with CPUID
3100 * leaves 0 and 1 in the loop below.
3101 */
3102 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3103
3104 /* Set XSTATE_BV */
3105 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3106
3107 /*
3108 * Copy each region from the possibly compacted offset to the
3109 * non-compacted offset.
3110 */
3111 valid = xstate_bv & ~XSTATE_FPSSE;
3112 while (valid) {
3113 u64 feature = valid & -valid;
3114 int index = fls64(feature) - 1;
3115 void *src = get_xsave_addr(xsave, feature);
3116
3117 if (src) {
3118 u32 size, offset, ecx, edx;
3119 cpuid_count(XSTATE_CPUID, index,
3120 &size, &offset, &ecx, &edx);
3121 memcpy(dest + offset, src, size);
3122 }
3123
3124 valid -= feature;
3125 }
3126 }
3127
3128 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3129 {
3130 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3131 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3132 u64 valid;
3133
3134 /*
3135 * Copy legacy XSAVE area, to avoid complications with CPUID
3136 * leaves 0 and 1 in the loop below.
3137 */
3138 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3139
3140 /* Set XSTATE_BV and possibly XCOMP_BV. */
3141 xsave->header.xfeatures = xstate_bv;
3142 if (cpu_has_xsaves)
3143 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3144
3145 /*
3146 * Copy each region from the non-compacted offset to the
3147 * possibly compacted offset.
3148 */
3149 valid = xstate_bv & ~XSTATE_FPSSE;
3150 while (valid) {
3151 u64 feature = valid & -valid;
3152 int index = fls64(feature) - 1;
3153 void *dest = get_xsave_addr(xsave, feature);
3154
3155 if (dest) {
3156 u32 size, offset, ecx, edx;
3157 cpuid_count(XSTATE_CPUID, index,
3158 &size, &offset, &ecx, &edx);
3159 memcpy(dest, src + offset, size);
3160 }
3161
3162 valid -= feature;
3163 }
3164 }
3165
3166 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3167 struct kvm_xsave *guest_xsave)
3168 {
3169 if (cpu_has_xsave) {
3170 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3171 fill_xsave((u8 *) guest_xsave->region, vcpu);
3172 } else {
3173 memcpy(guest_xsave->region,
3174 &vcpu->arch.guest_fpu.state.fxsave,
3175 sizeof(struct fxregs_state));
3176 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3177 XSTATE_FPSSE;
3178 }
3179 }
3180
3181 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3182 struct kvm_xsave *guest_xsave)
3183 {
3184 u64 xstate_bv =
3185 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3186
3187 if (cpu_has_xsave) {
3188 /*
3189 * Here we allow setting states that are not present in
3190 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3191 * with old userspace.
3192 */
3193 if (xstate_bv & ~kvm_supported_xcr0())
3194 return -EINVAL;
3195 load_xsave(vcpu, (u8 *)guest_xsave->region);
3196 } else {
3197 if (xstate_bv & ~XSTATE_FPSSE)
3198 return -EINVAL;
3199 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3200 guest_xsave->region, sizeof(struct fxregs_state));
3201 }
3202 return 0;
3203 }
3204
3205 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3206 struct kvm_xcrs *guest_xcrs)
3207 {
3208 if (!cpu_has_xsave) {
3209 guest_xcrs->nr_xcrs = 0;
3210 return;
3211 }
3212
3213 guest_xcrs->nr_xcrs = 1;
3214 guest_xcrs->flags = 0;
3215 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3216 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3217 }
3218
3219 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3220 struct kvm_xcrs *guest_xcrs)
3221 {
3222 int i, r = 0;
3223
3224 if (!cpu_has_xsave)
3225 return -EINVAL;
3226
3227 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3228 return -EINVAL;
3229
3230 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3231 /* Only support XCR0 currently */
3232 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3233 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3234 guest_xcrs->xcrs[i].value);
3235 break;
3236 }
3237 if (r)
3238 r = -EINVAL;
3239 return r;
3240 }
3241
3242 /*
3243 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3244 * stopped by the hypervisor. This function will be called from the host only.
3245 * EINVAL is returned when the host attempts to set the flag for a guest that
3246 * does not support pv clocks.
3247 */
3248 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3249 {
3250 if (!vcpu->arch.pv_time_enabled)
3251 return -EINVAL;
3252 vcpu->arch.pvclock_set_guest_stopped_request = true;
3253 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3254 return 0;
3255 }
3256
3257 long kvm_arch_vcpu_ioctl(struct file *filp,
3258 unsigned int ioctl, unsigned long arg)
3259 {
3260 struct kvm_vcpu *vcpu = filp->private_data;
3261 void __user *argp = (void __user *)arg;
3262 int r;
3263 union {
3264 struct kvm_lapic_state *lapic;
3265 struct kvm_xsave *xsave;
3266 struct kvm_xcrs *xcrs;
3267 void *buffer;
3268 } u;
3269
3270 u.buffer = NULL;
3271 switch (ioctl) {
3272 case KVM_GET_LAPIC: {
3273 r = -EINVAL;
3274 if (!vcpu->arch.apic)
3275 goto out;
3276 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3277
3278 r = -ENOMEM;
3279 if (!u.lapic)
3280 goto out;
3281 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3282 if (r)
3283 goto out;
3284 r = -EFAULT;
3285 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3286 goto out;
3287 r = 0;
3288 break;
3289 }
3290 case KVM_SET_LAPIC: {
3291 r = -EINVAL;
3292 if (!vcpu->arch.apic)
3293 goto out;
3294 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3295 if (IS_ERR(u.lapic))
3296 return PTR_ERR(u.lapic);
3297
3298 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3299 break;
3300 }
3301 case KVM_INTERRUPT: {
3302 struct kvm_interrupt irq;
3303
3304 r = -EFAULT;
3305 if (copy_from_user(&irq, argp, sizeof irq))
3306 goto out;
3307 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3308 break;
3309 }
3310 case KVM_NMI: {
3311 r = kvm_vcpu_ioctl_nmi(vcpu);
3312 break;
3313 }
3314 case KVM_SMI: {
3315 r = kvm_vcpu_ioctl_smi(vcpu);
3316 break;
3317 }
3318 case KVM_SET_CPUID: {
3319 struct kvm_cpuid __user *cpuid_arg = argp;
3320 struct kvm_cpuid cpuid;
3321
3322 r = -EFAULT;
3323 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3324 goto out;
3325 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3326 break;
3327 }
3328 case KVM_SET_CPUID2: {
3329 struct kvm_cpuid2 __user *cpuid_arg = argp;
3330 struct kvm_cpuid2 cpuid;
3331
3332 r = -EFAULT;
3333 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3334 goto out;
3335 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3336 cpuid_arg->entries);
3337 break;
3338 }
3339 case KVM_GET_CPUID2: {
3340 struct kvm_cpuid2 __user *cpuid_arg = argp;
3341 struct kvm_cpuid2 cpuid;
3342
3343 r = -EFAULT;
3344 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3345 goto out;
3346 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3347 cpuid_arg->entries);
3348 if (r)
3349 goto out;
3350 r = -EFAULT;
3351 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3352 goto out;
3353 r = 0;
3354 break;
3355 }
3356 case KVM_GET_MSRS:
3357 r = msr_io(vcpu, argp, do_get_msr, 1);
3358 break;
3359 case KVM_SET_MSRS:
3360 r = msr_io(vcpu, argp, do_set_msr, 0);
3361 break;
3362 case KVM_TPR_ACCESS_REPORTING: {
3363 struct kvm_tpr_access_ctl tac;
3364
3365 r = -EFAULT;
3366 if (copy_from_user(&tac, argp, sizeof tac))
3367 goto out;
3368 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3369 if (r)
3370 goto out;
3371 r = -EFAULT;
3372 if (copy_to_user(argp, &tac, sizeof tac))
3373 goto out;
3374 r = 0;
3375 break;
3376 };
3377 case KVM_SET_VAPIC_ADDR: {
3378 struct kvm_vapic_addr va;
3379
3380 r = -EINVAL;
3381 if (!irqchip_in_kernel(vcpu->kvm))
3382 goto out;
3383 r = -EFAULT;
3384 if (copy_from_user(&va, argp, sizeof va))
3385 goto out;
3386 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3387 break;
3388 }
3389 case KVM_X86_SETUP_MCE: {
3390 u64 mcg_cap;
3391
3392 r = -EFAULT;
3393 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3394 goto out;
3395 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3396 break;
3397 }
3398 case KVM_X86_SET_MCE: {
3399 struct kvm_x86_mce mce;
3400
3401 r = -EFAULT;
3402 if (copy_from_user(&mce, argp, sizeof mce))
3403 goto out;
3404 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3405 break;
3406 }
3407 case KVM_GET_VCPU_EVENTS: {
3408 struct kvm_vcpu_events events;
3409
3410 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3411
3412 r = -EFAULT;
3413 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3414 break;
3415 r = 0;
3416 break;
3417 }
3418 case KVM_SET_VCPU_EVENTS: {
3419 struct kvm_vcpu_events events;
3420
3421 r = -EFAULT;
3422 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3423 break;
3424
3425 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3426 break;
3427 }
3428 case KVM_GET_DEBUGREGS: {
3429 struct kvm_debugregs dbgregs;
3430
3431 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3432
3433 r = -EFAULT;
3434 if (copy_to_user(argp, &dbgregs,
3435 sizeof(struct kvm_debugregs)))
3436 break;
3437 r = 0;
3438 break;
3439 }
3440 case KVM_SET_DEBUGREGS: {
3441 struct kvm_debugregs dbgregs;
3442
3443 r = -EFAULT;
3444 if (copy_from_user(&dbgregs, argp,
3445 sizeof(struct kvm_debugregs)))
3446 break;
3447
3448 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3449 break;
3450 }
3451 case KVM_GET_XSAVE: {
3452 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3453 r = -ENOMEM;
3454 if (!u.xsave)
3455 break;
3456
3457 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3458
3459 r = -EFAULT;
3460 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3461 break;
3462 r = 0;
3463 break;
3464 }
3465 case KVM_SET_XSAVE: {
3466 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3467 if (IS_ERR(u.xsave))
3468 return PTR_ERR(u.xsave);
3469
3470 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3471 break;
3472 }
3473 case KVM_GET_XCRS: {
3474 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3475 r = -ENOMEM;
3476 if (!u.xcrs)
3477 break;
3478
3479 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3480
3481 r = -EFAULT;
3482 if (copy_to_user(argp, u.xcrs,
3483 sizeof(struct kvm_xcrs)))
3484 break;
3485 r = 0;
3486 break;
3487 }
3488 case KVM_SET_XCRS: {
3489 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3490 if (IS_ERR(u.xcrs))
3491 return PTR_ERR(u.xcrs);
3492
3493 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3494 break;
3495 }
3496 case KVM_SET_TSC_KHZ: {
3497 u32 user_tsc_khz;
3498
3499 r = -EINVAL;
3500 user_tsc_khz = (u32)arg;
3501
3502 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3503 goto out;
3504
3505 if (user_tsc_khz == 0)
3506 user_tsc_khz = tsc_khz;
3507
3508 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3509
3510 r = 0;
3511 goto out;
3512 }
3513 case KVM_GET_TSC_KHZ: {
3514 r = vcpu->arch.virtual_tsc_khz;
3515 goto out;
3516 }
3517 case KVM_KVMCLOCK_CTRL: {
3518 r = kvm_set_guest_paused(vcpu);
3519 goto out;
3520 }
3521 default:
3522 r = -EINVAL;
3523 }
3524 out:
3525 kfree(u.buffer);
3526 return r;
3527 }
3528
3529 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3530 {
3531 return VM_FAULT_SIGBUS;
3532 }
3533
3534 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3535 {
3536 int ret;
3537
3538 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3539 return -EINVAL;
3540 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3541 return ret;
3542 }
3543
3544 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3545 u64 ident_addr)
3546 {
3547 kvm->arch.ept_identity_map_addr = ident_addr;
3548 return 0;
3549 }
3550
3551 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3552 u32 kvm_nr_mmu_pages)
3553 {
3554 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3555 return -EINVAL;
3556
3557 mutex_lock(&kvm->slots_lock);
3558
3559 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3560 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3561
3562 mutex_unlock(&kvm->slots_lock);
3563 return 0;
3564 }
3565
3566 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3567 {
3568 return kvm->arch.n_max_mmu_pages;
3569 }
3570
3571 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3572 {
3573 int r;
3574
3575 r = 0;
3576 switch (chip->chip_id) {
3577 case KVM_IRQCHIP_PIC_MASTER:
3578 memcpy(&chip->chip.pic,
3579 &pic_irqchip(kvm)->pics[0],
3580 sizeof(struct kvm_pic_state));
3581 break;
3582 case KVM_IRQCHIP_PIC_SLAVE:
3583 memcpy(&chip->chip.pic,
3584 &pic_irqchip(kvm)->pics[1],
3585 sizeof(struct kvm_pic_state));
3586 break;
3587 case KVM_IRQCHIP_IOAPIC:
3588 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3589 break;
3590 default:
3591 r = -EINVAL;
3592 break;
3593 }
3594 return r;
3595 }
3596
3597 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3598 {
3599 int r;
3600
3601 r = 0;
3602 switch (chip->chip_id) {
3603 case KVM_IRQCHIP_PIC_MASTER:
3604 spin_lock(&pic_irqchip(kvm)->lock);
3605 memcpy(&pic_irqchip(kvm)->pics[0],
3606 &chip->chip.pic,
3607 sizeof(struct kvm_pic_state));
3608 spin_unlock(&pic_irqchip(kvm)->lock);
3609 break;
3610 case KVM_IRQCHIP_PIC_SLAVE:
3611 spin_lock(&pic_irqchip(kvm)->lock);
3612 memcpy(&pic_irqchip(kvm)->pics[1],
3613 &chip->chip.pic,
3614 sizeof(struct kvm_pic_state));
3615 spin_unlock(&pic_irqchip(kvm)->lock);
3616 break;
3617 case KVM_IRQCHIP_IOAPIC:
3618 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3619 break;
3620 default:
3621 r = -EINVAL;
3622 break;
3623 }
3624 kvm_pic_update_irq(pic_irqchip(kvm));
3625 return r;
3626 }
3627
3628 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3629 {
3630 int r = 0;
3631
3632 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3633 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3634 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3635 return r;
3636 }
3637
3638 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3639 {
3640 int r = 0;
3641
3642 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3643 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3644 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3645 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3646 return r;
3647 }
3648
3649 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3650 {
3651 int r = 0;
3652
3653 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3654 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3655 sizeof(ps->channels));
3656 ps->flags = kvm->arch.vpit->pit_state.flags;
3657 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3658 memset(&ps->reserved, 0, sizeof(ps->reserved));
3659 return r;
3660 }
3661
3662 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3663 {
3664 int r = 0, start = 0;
3665 u32 prev_legacy, cur_legacy;
3666 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3667 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3668 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3669 if (!prev_legacy && cur_legacy)
3670 start = 1;
3671 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3672 sizeof(kvm->arch.vpit->pit_state.channels));
3673 kvm->arch.vpit->pit_state.flags = ps->flags;
3674 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3675 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3676 return r;
3677 }
3678
3679 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3680 struct kvm_reinject_control *control)
3681 {
3682 if (!kvm->arch.vpit)
3683 return -ENXIO;
3684 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3685 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3686 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3687 return 0;
3688 }
3689
3690 /**
3691 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3692 * @kvm: kvm instance
3693 * @log: slot id and address to which we copy the log
3694 *
3695 * Steps 1-4 below provide general overview of dirty page logging. See
3696 * kvm_get_dirty_log_protect() function description for additional details.
3697 *
3698 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3699 * always flush the TLB (step 4) even if previous step failed and the dirty
3700 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3701 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3702 * writes will be marked dirty for next log read.
3703 *
3704 * 1. Take a snapshot of the bit and clear it if needed.
3705 * 2. Write protect the corresponding page.
3706 * 3. Copy the snapshot to the userspace.
3707 * 4. Flush TLB's if needed.
3708 */
3709 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3710 {
3711 bool is_dirty = false;
3712 int r;
3713
3714 mutex_lock(&kvm->slots_lock);
3715
3716 /*
3717 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3718 */
3719 if (kvm_x86_ops->flush_log_dirty)
3720 kvm_x86_ops->flush_log_dirty(kvm);
3721
3722 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3723
3724 /*
3725 * All the TLBs can be flushed out of mmu lock, see the comments in
3726 * kvm_mmu_slot_remove_write_access().
3727 */
3728 lockdep_assert_held(&kvm->slots_lock);
3729 if (is_dirty)
3730 kvm_flush_remote_tlbs(kvm);
3731
3732 mutex_unlock(&kvm->slots_lock);
3733 return r;
3734 }
3735
3736 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3737 bool line_status)
3738 {
3739 if (!irqchip_in_kernel(kvm))
3740 return -ENXIO;
3741
3742 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3743 irq_event->irq, irq_event->level,
3744 line_status);
3745 return 0;
3746 }
3747
3748 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3749 struct kvm_enable_cap *cap)
3750 {
3751 int r;
3752
3753 if (cap->flags)
3754 return -EINVAL;
3755
3756 switch (cap->cap) {
3757 case KVM_CAP_DISABLE_QUIRKS:
3758 kvm->arch.disabled_quirks = cap->args[0];
3759 r = 0;
3760 break;
3761 default:
3762 r = -EINVAL;
3763 break;
3764 }
3765 return r;
3766 }
3767
3768 long kvm_arch_vm_ioctl(struct file *filp,
3769 unsigned int ioctl, unsigned long arg)
3770 {
3771 struct kvm *kvm = filp->private_data;
3772 void __user *argp = (void __user *)arg;
3773 int r = -ENOTTY;
3774 /*
3775 * This union makes it completely explicit to gcc-3.x
3776 * that these two variables' stack usage should be
3777 * combined, not added together.
3778 */
3779 union {
3780 struct kvm_pit_state ps;
3781 struct kvm_pit_state2 ps2;
3782 struct kvm_pit_config pit_config;
3783 } u;
3784
3785 switch (ioctl) {
3786 case KVM_SET_TSS_ADDR:
3787 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3788 break;
3789 case KVM_SET_IDENTITY_MAP_ADDR: {
3790 u64 ident_addr;
3791
3792 r = -EFAULT;
3793 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3794 goto out;
3795 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3796 break;
3797 }
3798 case KVM_SET_NR_MMU_PAGES:
3799 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3800 break;
3801 case KVM_GET_NR_MMU_PAGES:
3802 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3803 break;
3804 case KVM_CREATE_IRQCHIP: {
3805 struct kvm_pic *vpic;
3806
3807 mutex_lock(&kvm->lock);
3808 r = -EEXIST;
3809 if (kvm->arch.vpic)
3810 goto create_irqchip_unlock;
3811 r = -EINVAL;
3812 if (atomic_read(&kvm->online_vcpus))
3813 goto create_irqchip_unlock;
3814 r = -ENOMEM;
3815 vpic = kvm_create_pic(kvm);
3816 if (vpic) {
3817 r = kvm_ioapic_init(kvm);
3818 if (r) {
3819 mutex_lock(&kvm->slots_lock);
3820 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3821 &vpic->dev_master);
3822 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3823 &vpic->dev_slave);
3824 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3825 &vpic->dev_eclr);
3826 mutex_unlock(&kvm->slots_lock);
3827 kfree(vpic);
3828 goto create_irqchip_unlock;
3829 }
3830 } else
3831 goto create_irqchip_unlock;
3832 smp_wmb();
3833 kvm->arch.vpic = vpic;
3834 smp_wmb();
3835 r = kvm_setup_default_irq_routing(kvm);
3836 if (r) {
3837 mutex_lock(&kvm->slots_lock);
3838 mutex_lock(&kvm->irq_lock);
3839 kvm_ioapic_destroy(kvm);
3840 kvm_destroy_pic(kvm);
3841 mutex_unlock(&kvm->irq_lock);
3842 mutex_unlock(&kvm->slots_lock);
3843 }
3844 create_irqchip_unlock:
3845 mutex_unlock(&kvm->lock);
3846 break;
3847 }
3848 case KVM_CREATE_PIT:
3849 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3850 goto create_pit;
3851 case KVM_CREATE_PIT2:
3852 r = -EFAULT;
3853 if (copy_from_user(&u.pit_config, argp,
3854 sizeof(struct kvm_pit_config)))
3855 goto out;
3856 create_pit:
3857 mutex_lock(&kvm->slots_lock);
3858 r = -EEXIST;
3859 if (kvm->arch.vpit)
3860 goto create_pit_unlock;
3861 r = -ENOMEM;
3862 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3863 if (kvm->arch.vpit)
3864 r = 0;
3865 create_pit_unlock:
3866 mutex_unlock(&kvm->slots_lock);
3867 break;
3868 case KVM_GET_IRQCHIP: {
3869 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3870 struct kvm_irqchip *chip;
3871
3872 chip = memdup_user(argp, sizeof(*chip));
3873 if (IS_ERR(chip)) {
3874 r = PTR_ERR(chip);
3875 goto out;
3876 }
3877
3878 r = -ENXIO;
3879 if (!irqchip_in_kernel(kvm))
3880 goto get_irqchip_out;
3881 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3882 if (r)
3883 goto get_irqchip_out;
3884 r = -EFAULT;
3885 if (copy_to_user(argp, chip, sizeof *chip))
3886 goto get_irqchip_out;
3887 r = 0;
3888 get_irqchip_out:
3889 kfree(chip);
3890 break;
3891 }
3892 case KVM_SET_IRQCHIP: {
3893 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3894 struct kvm_irqchip *chip;
3895
3896 chip = memdup_user(argp, sizeof(*chip));
3897 if (IS_ERR(chip)) {
3898 r = PTR_ERR(chip);
3899 goto out;
3900 }
3901
3902 r = -ENXIO;
3903 if (!irqchip_in_kernel(kvm))
3904 goto set_irqchip_out;
3905 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3906 if (r)
3907 goto set_irqchip_out;
3908 r = 0;
3909 set_irqchip_out:
3910 kfree(chip);
3911 break;
3912 }
3913 case KVM_GET_PIT: {
3914 r = -EFAULT;
3915 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3916 goto out;
3917 r = -ENXIO;
3918 if (!kvm->arch.vpit)
3919 goto out;
3920 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3921 if (r)
3922 goto out;
3923 r = -EFAULT;
3924 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3925 goto out;
3926 r = 0;
3927 break;
3928 }
3929 case KVM_SET_PIT: {
3930 r = -EFAULT;
3931 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3932 goto out;
3933 r = -ENXIO;
3934 if (!kvm->arch.vpit)
3935 goto out;
3936 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3937 break;
3938 }
3939 case KVM_GET_PIT2: {
3940 r = -ENXIO;
3941 if (!kvm->arch.vpit)
3942 goto out;
3943 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3944 if (r)
3945 goto out;
3946 r = -EFAULT;
3947 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3948 goto out;
3949 r = 0;
3950 break;
3951 }
3952 case KVM_SET_PIT2: {
3953 r = -EFAULT;
3954 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3955 goto out;
3956 r = -ENXIO;
3957 if (!kvm->arch.vpit)
3958 goto out;
3959 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3960 break;
3961 }
3962 case KVM_REINJECT_CONTROL: {
3963 struct kvm_reinject_control control;
3964 r = -EFAULT;
3965 if (copy_from_user(&control, argp, sizeof(control)))
3966 goto out;
3967 r = kvm_vm_ioctl_reinject(kvm, &control);
3968 break;
3969 }
3970 case KVM_XEN_HVM_CONFIG: {
3971 r = -EFAULT;
3972 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3973 sizeof(struct kvm_xen_hvm_config)))
3974 goto out;
3975 r = -EINVAL;
3976 if (kvm->arch.xen_hvm_config.flags)
3977 goto out;
3978 r = 0;
3979 break;
3980 }
3981 case KVM_SET_CLOCK: {
3982 struct kvm_clock_data user_ns;
3983 u64 now_ns;
3984 s64 delta;
3985
3986 r = -EFAULT;
3987 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3988 goto out;
3989
3990 r = -EINVAL;
3991 if (user_ns.flags)
3992 goto out;
3993
3994 r = 0;
3995 local_irq_disable();
3996 now_ns = get_kernel_ns();
3997 delta = user_ns.clock - now_ns;
3998 local_irq_enable();
3999 kvm->arch.kvmclock_offset = delta;
4000 kvm_gen_update_masterclock(kvm);
4001 break;
4002 }
4003 case KVM_GET_CLOCK: {
4004 struct kvm_clock_data user_ns;
4005 u64 now_ns;
4006
4007 local_irq_disable();
4008 now_ns = get_kernel_ns();
4009 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
4010 local_irq_enable();
4011 user_ns.flags = 0;
4012 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4013
4014 r = -EFAULT;
4015 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4016 goto out;
4017 r = 0;
4018 break;
4019 }
4020 case KVM_ENABLE_CAP: {
4021 struct kvm_enable_cap cap;
4022
4023 r = -EFAULT;
4024 if (copy_from_user(&cap, argp, sizeof(cap)))
4025 goto out;
4026 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4027 break;
4028 }
4029 default:
4030 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
4031 }
4032 out:
4033 return r;
4034 }
4035
4036 static void kvm_init_msr_list(void)
4037 {
4038 u32 dummy[2];
4039 unsigned i, j;
4040
4041 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4042 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4043 continue;
4044
4045 /*
4046 * Even MSRs that are valid in the host may not be exposed
4047 * to the guests in some cases. We could work around this
4048 * in VMX with the generic MSR save/load machinery, but it
4049 * is not really worthwhile since it will really only
4050 * happen with nested virtualization.
4051 */
4052 switch (msrs_to_save[i]) {
4053 case MSR_IA32_BNDCFGS:
4054 if (!kvm_x86_ops->mpx_supported())
4055 continue;
4056 break;
4057 default:
4058 break;
4059 }
4060
4061 if (j < i)
4062 msrs_to_save[j] = msrs_to_save[i];
4063 j++;
4064 }
4065 num_msrs_to_save = j;
4066
4067 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4068 switch (emulated_msrs[i]) {
4069 case MSR_IA32_SMBASE:
4070 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4071 continue;
4072 break;
4073 default:
4074 break;
4075 }
4076
4077 if (j < i)
4078 emulated_msrs[j] = emulated_msrs[i];
4079 j++;
4080 }
4081 num_emulated_msrs = j;
4082 }
4083
4084 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4085 const void *v)
4086 {
4087 int handled = 0;
4088 int n;
4089
4090 do {
4091 n = min(len, 8);
4092 if (!(vcpu->arch.apic &&
4093 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4094 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4095 break;
4096 handled += n;
4097 addr += n;
4098 len -= n;
4099 v += n;
4100 } while (len);
4101
4102 return handled;
4103 }
4104
4105 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4106 {
4107 int handled = 0;
4108 int n;
4109
4110 do {
4111 n = min(len, 8);
4112 if (!(vcpu->arch.apic &&
4113 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4114 addr, n, v))
4115 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4116 break;
4117 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4118 handled += n;
4119 addr += n;
4120 len -= n;
4121 v += n;
4122 } while (len);
4123
4124 return handled;
4125 }
4126
4127 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4128 struct kvm_segment *var, int seg)
4129 {
4130 kvm_x86_ops->set_segment(vcpu, var, seg);
4131 }
4132
4133 void kvm_get_segment(struct kvm_vcpu *vcpu,
4134 struct kvm_segment *var, int seg)
4135 {
4136 kvm_x86_ops->get_segment(vcpu, var, seg);
4137 }
4138
4139 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4140 struct x86_exception *exception)
4141 {
4142 gpa_t t_gpa;
4143
4144 BUG_ON(!mmu_is_nested(vcpu));
4145
4146 /* NPT walks are always user-walks */
4147 access |= PFERR_USER_MASK;
4148 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4149
4150 return t_gpa;
4151 }
4152
4153 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4154 struct x86_exception *exception)
4155 {
4156 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4157 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4158 }
4159
4160 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4161 struct x86_exception *exception)
4162 {
4163 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4164 access |= PFERR_FETCH_MASK;
4165 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4166 }
4167
4168 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4169 struct x86_exception *exception)
4170 {
4171 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4172 access |= PFERR_WRITE_MASK;
4173 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4174 }
4175
4176 /* uses this to access any guest's mapped memory without checking CPL */
4177 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4178 struct x86_exception *exception)
4179 {
4180 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4181 }
4182
4183 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4184 struct kvm_vcpu *vcpu, u32 access,
4185 struct x86_exception *exception)
4186 {
4187 void *data = val;
4188 int r = X86EMUL_CONTINUE;
4189
4190 while (bytes) {
4191 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4192 exception);
4193 unsigned offset = addr & (PAGE_SIZE-1);
4194 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4195 int ret;
4196
4197 if (gpa == UNMAPPED_GVA)
4198 return X86EMUL_PROPAGATE_FAULT;
4199 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4200 offset, toread);
4201 if (ret < 0) {
4202 r = X86EMUL_IO_NEEDED;
4203 goto out;
4204 }
4205
4206 bytes -= toread;
4207 data += toread;
4208 addr += toread;
4209 }
4210 out:
4211 return r;
4212 }
4213
4214 /* used for instruction fetching */
4215 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4216 gva_t addr, void *val, unsigned int bytes,
4217 struct x86_exception *exception)
4218 {
4219 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4220 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4221 unsigned offset;
4222 int ret;
4223
4224 /* Inline kvm_read_guest_virt_helper for speed. */
4225 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4226 exception);
4227 if (unlikely(gpa == UNMAPPED_GVA))
4228 return X86EMUL_PROPAGATE_FAULT;
4229
4230 offset = addr & (PAGE_SIZE-1);
4231 if (WARN_ON(offset + bytes > PAGE_SIZE))
4232 bytes = (unsigned)PAGE_SIZE - offset;
4233 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4234 offset, bytes);
4235 if (unlikely(ret < 0))
4236 return X86EMUL_IO_NEEDED;
4237
4238 return X86EMUL_CONTINUE;
4239 }
4240
4241 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4242 gva_t addr, void *val, unsigned int bytes,
4243 struct x86_exception *exception)
4244 {
4245 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4246 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4247
4248 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4249 exception);
4250 }
4251 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4252
4253 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4254 gva_t addr, void *val, unsigned int bytes,
4255 struct x86_exception *exception)
4256 {
4257 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4258 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4259 }
4260
4261 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4262 gva_t addr, void *val,
4263 unsigned int bytes,
4264 struct x86_exception *exception)
4265 {
4266 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4267 void *data = val;
4268 int r = X86EMUL_CONTINUE;
4269
4270 while (bytes) {
4271 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4272 PFERR_WRITE_MASK,
4273 exception);
4274 unsigned offset = addr & (PAGE_SIZE-1);
4275 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4276 int ret;
4277
4278 if (gpa == UNMAPPED_GVA)
4279 return X86EMUL_PROPAGATE_FAULT;
4280 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4281 if (ret < 0) {
4282 r = X86EMUL_IO_NEEDED;
4283 goto out;
4284 }
4285
4286 bytes -= towrite;
4287 data += towrite;
4288 addr += towrite;
4289 }
4290 out:
4291 return r;
4292 }
4293 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4294
4295 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4296 gpa_t *gpa, struct x86_exception *exception,
4297 bool write)
4298 {
4299 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4300 | (write ? PFERR_WRITE_MASK : 0);
4301
4302 if (vcpu_match_mmio_gva(vcpu, gva)
4303 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4304 vcpu->arch.access, access)) {
4305 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4306 (gva & (PAGE_SIZE - 1));
4307 trace_vcpu_match_mmio(gva, *gpa, write, false);
4308 return 1;
4309 }
4310
4311 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4312
4313 if (*gpa == UNMAPPED_GVA)
4314 return -1;
4315
4316 /* For APIC access vmexit */
4317 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4318 return 1;
4319
4320 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4321 trace_vcpu_match_mmio(gva, *gpa, write, true);
4322 return 1;
4323 }
4324
4325 return 0;
4326 }
4327
4328 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4329 const void *val, int bytes)
4330 {
4331 int ret;
4332
4333 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4334 if (ret < 0)
4335 return 0;
4336 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4337 return 1;
4338 }
4339
4340 struct read_write_emulator_ops {
4341 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4342 int bytes);
4343 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4344 void *val, int bytes);
4345 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4346 int bytes, void *val);
4347 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4348 void *val, int bytes);
4349 bool write;
4350 };
4351
4352 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4353 {
4354 if (vcpu->mmio_read_completed) {
4355 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4356 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4357 vcpu->mmio_read_completed = 0;
4358 return 1;
4359 }
4360
4361 return 0;
4362 }
4363
4364 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4365 void *val, int bytes)
4366 {
4367 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4368 }
4369
4370 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4371 void *val, int bytes)
4372 {
4373 return emulator_write_phys(vcpu, gpa, val, bytes);
4374 }
4375
4376 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4377 {
4378 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4379 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4380 }
4381
4382 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4383 void *val, int bytes)
4384 {
4385 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4386 return X86EMUL_IO_NEEDED;
4387 }
4388
4389 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4390 void *val, int bytes)
4391 {
4392 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4393
4394 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4395 return X86EMUL_CONTINUE;
4396 }
4397
4398 static const struct read_write_emulator_ops read_emultor = {
4399 .read_write_prepare = read_prepare,
4400 .read_write_emulate = read_emulate,
4401 .read_write_mmio = vcpu_mmio_read,
4402 .read_write_exit_mmio = read_exit_mmio,
4403 };
4404
4405 static const struct read_write_emulator_ops write_emultor = {
4406 .read_write_emulate = write_emulate,
4407 .read_write_mmio = write_mmio,
4408 .read_write_exit_mmio = write_exit_mmio,
4409 .write = true,
4410 };
4411
4412 static int emulator_read_write_onepage(unsigned long addr, void *val,
4413 unsigned int bytes,
4414 struct x86_exception *exception,
4415 struct kvm_vcpu *vcpu,
4416 const struct read_write_emulator_ops *ops)
4417 {
4418 gpa_t gpa;
4419 int handled, ret;
4420 bool write = ops->write;
4421 struct kvm_mmio_fragment *frag;
4422
4423 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4424
4425 if (ret < 0)
4426 return X86EMUL_PROPAGATE_FAULT;
4427
4428 /* For APIC access vmexit */
4429 if (ret)
4430 goto mmio;
4431
4432 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4433 return X86EMUL_CONTINUE;
4434
4435 mmio:
4436 /*
4437 * Is this MMIO handled locally?
4438 */
4439 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4440 if (handled == bytes)
4441 return X86EMUL_CONTINUE;
4442
4443 gpa += handled;
4444 bytes -= handled;
4445 val += handled;
4446
4447 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4448 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4449 frag->gpa = gpa;
4450 frag->data = val;
4451 frag->len = bytes;
4452 return X86EMUL_CONTINUE;
4453 }
4454
4455 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4456 unsigned long addr,
4457 void *val, unsigned int bytes,
4458 struct x86_exception *exception,
4459 const struct read_write_emulator_ops *ops)
4460 {
4461 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4462 gpa_t gpa;
4463 int rc;
4464
4465 if (ops->read_write_prepare &&
4466 ops->read_write_prepare(vcpu, val, bytes))
4467 return X86EMUL_CONTINUE;
4468
4469 vcpu->mmio_nr_fragments = 0;
4470
4471 /* Crossing a page boundary? */
4472 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4473 int now;
4474
4475 now = -addr & ~PAGE_MASK;
4476 rc = emulator_read_write_onepage(addr, val, now, exception,
4477 vcpu, ops);
4478
4479 if (rc != X86EMUL_CONTINUE)
4480 return rc;
4481 addr += now;
4482 if (ctxt->mode != X86EMUL_MODE_PROT64)
4483 addr = (u32)addr;
4484 val += now;
4485 bytes -= now;
4486 }
4487
4488 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4489 vcpu, ops);
4490 if (rc != X86EMUL_CONTINUE)
4491 return rc;
4492
4493 if (!vcpu->mmio_nr_fragments)
4494 return rc;
4495
4496 gpa = vcpu->mmio_fragments[0].gpa;
4497
4498 vcpu->mmio_needed = 1;
4499 vcpu->mmio_cur_fragment = 0;
4500
4501 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4502 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4503 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4504 vcpu->run->mmio.phys_addr = gpa;
4505
4506 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4507 }
4508
4509 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4510 unsigned long addr,
4511 void *val,
4512 unsigned int bytes,
4513 struct x86_exception *exception)
4514 {
4515 return emulator_read_write(ctxt, addr, val, bytes,
4516 exception, &read_emultor);
4517 }
4518
4519 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4520 unsigned long addr,
4521 const void *val,
4522 unsigned int bytes,
4523 struct x86_exception *exception)
4524 {
4525 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4526 exception, &write_emultor);
4527 }
4528
4529 #define CMPXCHG_TYPE(t, ptr, old, new) \
4530 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4531
4532 #ifdef CONFIG_X86_64
4533 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4534 #else
4535 # define CMPXCHG64(ptr, old, new) \
4536 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4537 #endif
4538
4539 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4540 unsigned long addr,
4541 const void *old,
4542 const void *new,
4543 unsigned int bytes,
4544 struct x86_exception *exception)
4545 {
4546 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4547 gpa_t gpa;
4548 struct page *page;
4549 char *kaddr;
4550 bool exchanged;
4551
4552 /* guests cmpxchg8b have to be emulated atomically */
4553 if (bytes > 8 || (bytes & (bytes - 1)))
4554 goto emul_write;
4555
4556 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4557
4558 if (gpa == UNMAPPED_GVA ||
4559 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4560 goto emul_write;
4561
4562 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4563 goto emul_write;
4564
4565 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
4566 if (is_error_page(page))
4567 goto emul_write;
4568
4569 kaddr = kmap_atomic(page);
4570 kaddr += offset_in_page(gpa);
4571 switch (bytes) {
4572 case 1:
4573 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4574 break;
4575 case 2:
4576 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4577 break;
4578 case 4:
4579 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4580 break;
4581 case 8:
4582 exchanged = CMPXCHG64(kaddr, old, new);
4583 break;
4584 default:
4585 BUG();
4586 }
4587 kunmap_atomic(kaddr);
4588 kvm_release_page_dirty(page);
4589
4590 if (!exchanged)
4591 return X86EMUL_CMPXCHG_FAILED;
4592
4593 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
4594 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4595
4596 return X86EMUL_CONTINUE;
4597
4598 emul_write:
4599 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4600
4601 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4602 }
4603
4604 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4605 {
4606 /* TODO: String I/O for in kernel device */
4607 int r;
4608
4609 if (vcpu->arch.pio.in)
4610 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4611 vcpu->arch.pio.size, pd);
4612 else
4613 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4614 vcpu->arch.pio.port, vcpu->arch.pio.size,
4615 pd);
4616 return r;
4617 }
4618
4619 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4620 unsigned short port, void *val,
4621 unsigned int count, bool in)
4622 {
4623 vcpu->arch.pio.port = port;
4624 vcpu->arch.pio.in = in;
4625 vcpu->arch.pio.count = count;
4626 vcpu->arch.pio.size = size;
4627
4628 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4629 vcpu->arch.pio.count = 0;
4630 return 1;
4631 }
4632
4633 vcpu->run->exit_reason = KVM_EXIT_IO;
4634 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4635 vcpu->run->io.size = size;
4636 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4637 vcpu->run->io.count = count;
4638 vcpu->run->io.port = port;
4639
4640 return 0;
4641 }
4642
4643 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4644 int size, unsigned short port, void *val,
4645 unsigned int count)
4646 {
4647 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4648 int ret;
4649
4650 if (vcpu->arch.pio.count)
4651 goto data_avail;
4652
4653 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4654 if (ret) {
4655 data_avail:
4656 memcpy(val, vcpu->arch.pio_data, size * count);
4657 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4658 vcpu->arch.pio.count = 0;
4659 return 1;
4660 }
4661
4662 return 0;
4663 }
4664
4665 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4666 int size, unsigned short port,
4667 const void *val, unsigned int count)
4668 {
4669 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4670
4671 memcpy(vcpu->arch.pio_data, val, size * count);
4672 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4673 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4674 }
4675
4676 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4677 {
4678 return kvm_x86_ops->get_segment_base(vcpu, seg);
4679 }
4680
4681 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4682 {
4683 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4684 }
4685
4686 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
4687 {
4688 if (!need_emulate_wbinvd(vcpu))
4689 return X86EMUL_CONTINUE;
4690
4691 if (kvm_x86_ops->has_wbinvd_exit()) {
4692 int cpu = get_cpu();
4693
4694 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4695 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4696 wbinvd_ipi, NULL, 1);
4697 put_cpu();
4698 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4699 } else
4700 wbinvd();
4701 return X86EMUL_CONTINUE;
4702 }
4703
4704 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4705 {
4706 kvm_x86_ops->skip_emulated_instruction(vcpu);
4707 return kvm_emulate_wbinvd_noskip(vcpu);
4708 }
4709 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4710
4711
4712
4713 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4714 {
4715 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
4716 }
4717
4718 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4719 unsigned long *dest)
4720 {
4721 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4722 }
4723
4724 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4725 unsigned long value)
4726 {
4727
4728 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4729 }
4730
4731 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4732 {
4733 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4734 }
4735
4736 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4737 {
4738 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4739 unsigned long value;
4740
4741 switch (cr) {
4742 case 0:
4743 value = kvm_read_cr0(vcpu);
4744 break;
4745 case 2:
4746 value = vcpu->arch.cr2;
4747 break;
4748 case 3:
4749 value = kvm_read_cr3(vcpu);
4750 break;
4751 case 4:
4752 value = kvm_read_cr4(vcpu);
4753 break;
4754 case 8:
4755 value = kvm_get_cr8(vcpu);
4756 break;
4757 default:
4758 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4759 return 0;
4760 }
4761
4762 return value;
4763 }
4764
4765 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4766 {
4767 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4768 int res = 0;
4769
4770 switch (cr) {
4771 case 0:
4772 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4773 break;
4774 case 2:
4775 vcpu->arch.cr2 = val;
4776 break;
4777 case 3:
4778 res = kvm_set_cr3(vcpu, val);
4779 break;
4780 case 4:
4781 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4782 break;
4783 case 8:
4784 res = kvm_set_cr8(vcpu, val);
4785 break;
4786 default:
4787 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4788 res = -1;
4789 }
4790
4791 return res;
4792 }
4793
4794 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4795 {
4796 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4797 }
4798
4799 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4800 {
4801 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4802 }
4803
4804 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4805 {
4806 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4807 }
4808
4809 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4810 {
4811 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4812 }
4813
4814 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4815 {
4816 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4817 }
4818
4819 static unsigned long emulator_get_cached_segment_base(
4820 struct x86_emulate_ctxt *ctxt, int seg)
4821 {
4822 return get_segment_base(emul_to_vcpu(ctxt), seg);
4823 }
4824
4825 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4826 struct desc_struct *desc, u32 *base3,
4827 int seg)
4828 {
4829 struct kvm_segment var;
4830
4831 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4832 *selector = var.selector;
4833
4834 if (var.unusable) {
4835 memset(desc, 0, sizeof(*desc));
4836 return false;
4837 }
4838
4839 if (var.g)
4840 var.limit >>= 12;
4841 set_desc_limit(desc, var.limit);
4842 set_desc_base(desc, (unsigned long)var.base);
4843 #ifdef CONFIG_X86_64
4844 if (base3)
4845 *base3 = var.base >> 32;
4846 #endif
4847 desc->type = var.type;
4848 desc->s = var.s;
4849 desc->dpl = var.dpl;
4850 desc->p = var.present;
4851 desc->avl = var.avl;
4852 desc->l = var.l;
4853 desc->d = var.db;
4854 desc->g = var.g;
4855
4856 return true;
4857 }
4858
4859 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4860 struct desc_struct *desc, u32 base3,
4861 int seg)
4862 {
4863 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4864 struct kvm_segment var;
4865
4866 var.selector = selector;
4867 var.base = get_desc_base(desc);
4868 #ifdef CONFIG_X86_64
4869 var.base |= ((u64)base3) << 32;
4870 #endif
4871 var.limit = get_desc_limit(desc);
4872 if (desc->g)
4873 var.limit = (var.limit << 12) | 0xfff;
4874 var.type = desc->type;
4875 var.dpl = desc->dpl;
4876 var.db = desc->d;
4877 var.s = desc->s;
4878 var.l = desc->l;
4879 var.g = desc->g;
4880 var.avl = desc->avl;
4881 var.present = desc->p;
4882 var.unusable = !var.present;
4883 var.padding = 0;
4884
4885 kvm_set_segment(vcpu, &var, seg);
4886 return;
4887 }
4888
4889 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4890 u32 msr_index, u64 *pdata)
4891 {
4892 struct msr_data msr;
4893 int r;
4894
4895 msr.index = msr_index;
4896 msr.host_initiated = false;
4897 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4898 if (r)
4899 return r;
4900
4901 *pdata = msr.data;
4902 return 0;
4903 }
4904
4905 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4906 u32 msr_index, u64 data)
4907 {
4908 struct msr_data msr;
4909
4910 msr.data = data;
4911 msr.index = msr_index;
4912 msr.host_initiated = false;
4913 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4914 }
4915
4916 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4917 {
4918 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4919
4920 return vcpu->arch.smbase;
4921 }
4922
4923 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4924 {
4925 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4926
4927 vcpu->arch.smbase = smbase;
4928 }
4929
4930 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4931 u32 pmc)
4932 {
4933 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
4934 }
4935
4936 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4937 u32 pmc, u64 *pdata)
4938 {
4939 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
4940 }
4941
4942 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4943 {
4944 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4945 }
4946
4947 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4948 {
4949 preempt_disable();
4950 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4951 /*
4952 * CR0.TS may reference the host fpu state, not the guest fpu state,
4953 * so it may be clear at this point.
4954 */
4955 clts();
4956 }
4957
4958 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4959 {
4960 preempt_enable();
4961 }
4962
4963 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4964 struct x86_instruction_info *info,
4965 enum x86_intercept_stage stage)
4966 {
4967 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4968 }
4969
4970 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4971 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4972 {
4973 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4974 }
4975
4976 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4977 {
4978 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4979 }
4980
4981 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4982 {
4983 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4984 }
4985
4986 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
4987 {
4988 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
4989 }
4990
4991 static const struct x86_emulate_ops emulate_ops = {
4992 .read_gpr = emulator_read_gpr,
4993 .write_gpr = emulator_write_gpr,
4994 .read_std = kvm_read_guest_virt_system,
4995 .write_std = kvm_write_guest_virt_system,
4996 .fetch = kvm_fetch_guest_virt,
4997 .read_emulated = emulator_read_emulated,
4998 .write_emulated = emulator_write_emulated,
4999 .cmpxchg_emulated = emulator_cmpxchg_emulated,
5000 .invlpg = emulator_invlpg,
5001 .pio_in_emulated = emulator_pio_in_emulated,
5002 .pio_out_emulated = emulator_pio_out_emulated,
5003 .get_segment = emulator_get_segment,
5004 .set_segment = emulator_set_segment,
5005 .get_cached_segment_base = emulator_get_cached_segment_base,
5006 .get_gdt = emulator_get_gdt,
5007 .get_idt = emulator_get_idt,
5008 .set_gdt = emulator_set_gdt,
5009 .set_idt = emulator_set_idt,
5010 .get_cr = emulator_get_cr,
5011 .set_cr = emulator_set_cr,
5012 .cpl = emulator_get_cpl,
5013 .get_dr = emulator_get_dr,
5014 .set_dr = emulator_set_dr,
5015 .get_smbase = emulator_get_smbase,
5016 .set_smbase = emulator_set_smbase,
5017 .set_msr = emulator_set_msr,
5018 .get_msr = emulator_get_msr,
5019 .check_pmc = emulator_check_pmc,
5020 .read_pmc = emulator_read_pmc,
5021 .halt = emulator_halt,
5022 .wbinvd = emulator_wbinvd,
5023 .fix_hypercall = emulator_fix_hypercall,
5024 .get_fpu = emulator_get_fpu,
5025 .put_fpu = emulator_put_fpu,
5026 .intercept = emulator_intercept,
5027 .get_cpuid = emulator_get_cpuid,
5028 .set_nmi_mask = emulator_set_nmi_mask,
5029 };
5030
5031 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5032 {
5033 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5034 /*
5035 * an sti; sti; sequence only disable interrupts for the first
5036 * instruction. So, if the last instruction, be it emulated or
5037 * not, left the system with the INT_STI flag enabled, it
5038 * means that the last instruction is an sti. We should not
5039 * leave the flag on in this case. The same goes for mov ss
5040 */
5041 if (int_shadow & mask)
5042 mask = 0;
5043 if (unlikely(int_shadow || mask)) {
5044 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5045 if (!mask)
5046 kvm_make_request(KVM_REQ_EVENT, vcpu);
5047 }
5048 }
5049
5050 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5051 {
5052 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5053 if (ctxt->exception.vector == PF_VECTOR)
5054 return kvm_propagate_fault(vcpu, &ctxt->exception);
5055
5056 if (ctxt->exception.error_code_valid)
5057 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5058 ctxt->exception.error_code);
5059 else
5060 kvm_queue_exception(vcpu, ctxt->exception.vector);
5061 return false;
5062 }
5063
5064 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5065 {
5066 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5067 int cs_db, cs_l;
5068
5069 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5070
5071 ctxt->eflags = kvm_get_rflags(vcpu);
5072 ctxt->eip = kvm_rip_read(vcpu);
5073 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5074 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
5075 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
5076 cs_db ? X86EMUL_MODE_PROT32 :
5077 X86EMUL_MODE_PROT16;
5078 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
5079 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5080 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
5081 ctxt->emul_flags = vcpu->arch.hflags;
5082
5083 init_decode_cache(ctxt);
5084 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5085 }
5086
5087 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5088 {
5089 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5090 int ret;
5091
5092 init_emulate_ctxt(vcpu);
5093
5094 ctxt->op_bytes = 2;
5095 ctxt->ad_bytes = 2;
5096 ctxt->_eip = ctxt->eip + inc_eip;
5097 ret = emulate_int_real(ctxt, irq);
5098
5099 if (ret != X86EMUL_CONTINUE)
5100 return EMULATE_FAIL;
5101
5102 ctxt->eip = ctxt->_eip;
5103 kvm_rip_write(vcpu, ctxt->eip);
5104 kvm_set_rflags(vcpu, ctxt->eflags);
5105
5106 if (irq == NMI_VECTOR)
5107 vcpu->arch.nmi_pending = 0;
5108 else
5109 vcpu->arch.interrupt.pending = false;
5110
5111 return EMULATE_DONE;
5112 }
5113 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5114
5115 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5116 {
5117 int r = EMULATE_DONE;
5118
5119 ++vcpu->stat.insn_emulation_fail;
5120 trace_kvm_emulate_insn_failed(vcpu);
5121 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5122 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5123 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5124 vcpu->run->internal.ndata = 0;
5125 r = EMULATE_FAIL;
5126 }
5127 kvm_queue_exception(vcpu, UD_VECTOR);
5128
5129 return r;
5130 }
5131
5132 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5133 bool write_fault_to_shadow_pgtable,
5134 int emulation_type)
5135 {
5136 gpa_t gpa = cr2;
5137 pfn_t pfn;
5138
5139 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5140 return false;
5141
5142 if (!vcpu->arch.mmu.direct_map) {
5143 /*
5144 * Write permission should be allowed since only
5145 * write access need to be emulated.
5146 */
5147 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5148
5149 /*
5150 * If the mapping is invalid in guest, let cpu retry
5151 * it to generate fault.
5152 */
5153 if (gpa == UNMAPPED_GVA)
5154 return true;
5155 }
5156
5157 /*
5158 * Do not retry the unhandleable instruction if it faults on the
5159 * readonly host memory, otherwise it will goto a infinite loop:
5160 * retry instruction -> write #PF -> emulation fail -> retry
5161 * instruction -> ...
5162 */
5163 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5164
5165 /*
5166 * If the instruction failed on the error pfn, it can not be fixed,
5167 * report the error to userspace.
5168 */
5169 if (is_error_noslot_pfn(pfn))
5170 return false;
5171
5172 kvm_release_pfn_clean(pfn);
5173
5174 /* The instructions are well-emulated on direct mmu. */
5175 if (vcpu->arch.mmu.direct_map) {
5176 unsigned int indirect_shadow_pages;
5177
5178 spin_lock(&vcpu->kvm->mmu_lock);
5179 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5180 spin_unlock(&vcpu->kvm->mmu_lock);
5181
5182 if (indirect_shadow_pages)
5183 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5184
5185 return true;
5186 }
5187
5188 /*
5189 * if emulation was due to access to shadowed page table
5190 * and it failed try to unshadow page and re-enter the
5191 * guest to let CPU execute the instruction.
5192 */
5193 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5194
5195 /*
5196 * If the access faults on its page table, it can not
5197 * be fixed by unprotecting shadow page and it should
5198 * be reported to userspace.
5199 */
5200 return !write_fault_to_shadow_pgtable;
5201 }
5202
5203 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5204 unsigned long cr2, int emulation_type)
5205 {
5206 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5207 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5208
5209 last_retry_eip = vcpu->arch.last_retry_eip;
5210 last_retry_addr = vcpu->arch.last_retry_addr;
5211
5212 /*
5213 * If the emulation is caused by #PF and it is non-page_table
5214 * writing instruction, it means the VM-EXIT is caused by shadow
5215 * page protected, we can zap the shadow page and retry this
5216 * instruction directly.
5217 *
5218 * Note: if the guest uses a non-page-table modifying instruction
5219 * on the PDE that points to the instruction, then we will unmap
5220 * the instruction and go to an infinite loop. So, we cache the
5221 * last retried eip and the last fault address, if we meet the eip
5222 * and the address again, we can break out of the potential infinite
5223 * loop.
5224 */
5225 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5226
5227 if (!(emulation_type & EMULTYPE_RETRY))
5228 return false;
5229
5230 if (x86_page_table_writing_insn(ctxt))
5231 return false;
5232
5233 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5234 return false;
5235
5236 vcpu->arch.last_retry_eip = ctxt->eip;
5237 vcpu->arch.last_retry_addr = cr2;
5238
5239 if (!vcpu->arch.mmu.direct_map)
5240 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5241
5242 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5243
5244 return true;
5245 }
5246
5247 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5248 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5249
5250 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5251 {
5252 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5253 /* This is a good place to trace that we are exiting SMM. */
5254 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5255
5256 if (unlikely(vcpu->arch.smi_pending)) {
5257 kvm_make_request(KVM_REQ_SMI, vcpu);
5258 vcpu->arch.smi_pending = 0;
5259 } else {
5260 /* Process a latched INIT, if any. */
5261 kvm_make_request(KVM_REQ_EVENT, vcpu);
5262 }
5263 }
5264
5265 kvm_mmu_reset_context(vcpu);
5266 }
5267
5268 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5269 {
5270 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5271
5272 vcpu->arch.hflags = emul_flags;
5273
5274 if (changed & HF_SMM_MASK)
5275 kvm_smm_changed(vcpu);
5276 }
5277
5278 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5279 unsigned long *db)
5280 {
5281 u32 dr6 = 0;
5282 int i;
5283 u32 enable, rwlen;
5284
5285 enable = dr7;
5286 rwlen = dr7 >> 16;
5287 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5288 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5289 dr6 |= (1 << i);
5290 return dr6;
5291 }
5292
5293 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
5294 {
5295 struct kvm_run *kvm_run = vcpu->run;
5296
5297 /*
5298 * rflags is the old, "raw" value of the flags. The new value has
5299 * not been saved yet.
5300 *
5301 * This is correct even for TF set by the guest, because "the
5302 * processor will not generate this exception after the instruction
5303 * that sets the TF flag".
5304 */
5305 if (unlikely(rflags & X86_EFLAGS_TF)) {
5306 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5307 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5308 DR6_RTM;
5309 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5310 kvm_run->debug.arch.exception = DB_VECTOR;
5311 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5312 *r = EMULATE_USER_EXIT;
5313 } else {
5314 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5315 /*
5316 * "Certain debug exceptions may clear bit 0-3. The
5317 * remaining contents of the DR6 register are never
5318 * cleared by the processor".
5319 */
5320 vcpu->arch.dr6 &= ~15;
5321 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5322 kvm_queue_exception(vcpu, DB_VECTOR);
5323 }
5324 }
5325 }
5326
5327 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5328 {
5329 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5330 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5331 struct kvm_run *kvm_run = vcpu->run;
5332 unsigned long eip = kvm_get_linear_rip(vcpu);
5333 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5334 vcpu->arch.guest_debug_dr7,
5335 vcpu->arch.eff_db);
5336
5337 if (dr6 != 0) {
5338 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5339 kvm_run->debug.arch.pc = eip;
5340 kvm_run->debug.arch.exception = DB_VECTOR;
5341 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5342 *r = EMULATE_USER_EXIT;
5343 return true;
5344 }
5345 }
5346
5347 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5348 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5349 unsigned long eip = kvm_get_linear_rip(vcpu);
5350 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5351 vcpu->arch.dr7,
5352 vcpu->arch.db);
5353
5354 if (dr6 != 0) {
5355 vcpu->arch.dr6 &= ~15;
5356 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5357 kvm_queue_exception(vcpu, DB_VECTOR);
5358 *r = EMULATE_DONE;
5359 return true;
5360 }
5361 }
5362
5363 return false;
5364 }
5365
5366 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5367 unsigned long cr2,
5368 int emulation_type,
5369 void *insn,
5370 int insn_len)
5371 {
5372 int r;
5373 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5374 bool writeback = true;
5375 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5376
5377 /*
5378 * Clear write_fault_to_shadow_pgtable here to ensure it is
5379 * never reused.
5380 */
5381 vcpu->arch.write_fault_to_shadow_pgtable = false;
5382 kvm_clear_exception_queue(vcpu);
5383
5384 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5385 init_emulate_ctxt(vcpu);
5386
5387 /*
5388 * We will reenter on the same instruction since
5389 * we do not set complete_userspace_io. This does not
5390 * handle watchpoints yet, those would be handled in
5391 * the emulate_ops.
5392 */
5393 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5394 return r;
5395
5396 ctxt->interruptibility = 0;
5397 ctxt->have_exception = false;
5398 ctxt->exception.vector = -1;
5399 ctxt->perm_ok = false;
5400
5401 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5402
5403 r = x86_decode_insn(ctxt, insn, insn_len);
5404
5405 trace_kvm_emulate_insn_start(vcpu);
5406 ++vcpu->stat.insn_emulation;
5407 if (r != EMULATION_OK) {
5408 if (emulation_type & EMULTYPE_TRAP_UD)
5409 return EMULATE_FAIL;
5410 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5411 emulation_type))
5412 return EMULATE_DONE;
5413 if (emulation_type & EMULTYPE_SKIP)
5414 return EMULATE_FAIL;
5415 return handle_emulation_failure(vcpu);
5416 }
5417 }
5418
5419 if (emulation_type & EMULTYPE_SKIP) {
5420 kvm_rip_write(vcpu, ctxt->_eip);
5421 if (ctxt->eflags & X86_EFLAGS_RF)
5422 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5423 return EMULATE_DONE;
5424 }
5425
5426 if (retry_instruction(ctxt, cr2, emulation_type))
5427 return EMULATE_DONE;
5428
5429 /* this is needed for vmware backdoor interface to work since it
5430 changes registers values during IO operation */
5431 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5432 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5433 emulator_invalidate_register_cache(ctxt);
5434 }
5435
5436 restart:
5437 r = x86_emulate_insn(ctxt);
5438
5439 if (r == EMULATION_INTERCEPTED)
5440 return EMULATE_DONE;
5441
5442 if (r == EMULATION_FAILED) {
5443 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5444 emulation_type))
5445 return EMULATE_DONE;
5446
5447 return handle_emulation_failure(vcpu);
5448 }
5449
5450 if (ctxt->have_exception) {
5451 r = EMULATE_DONE;
5452 if (inject_emulated_exception(vcpu))
5453 return r;
5454 } else if (vcpu->arch.pio.count) {
5455 if (!vcpu->arch.pio.in) {
5456 /* FIXME: return into emulator if single-stepping. */
5457 vcpu->arch.pio.count = 0;
5458 } else {
5459 writeback = false;
5460 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5461 }
5462 r = EMULATE_USER_EXIT;
5463 } else if (vcpu->mmio_needed) {
5464 if (!vcpu->mmio_is_write)
5465 writeback = false;
5466 r = EMULATE_USER_EXIT;
5467 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5468 } else if (r == EMULATION_RESTART)
5469 goto restart;
5470 else
5471 r = EMULATE_DONE;
5472
5473 if (writeback) {
5474 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5475 toggle_interruptibility(vcpu, ctxt->interruptibility);
5476 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5477 if (vcpu->arch.hflags != ctxt->emul_flags)
5478 kvm_set_hflags(vcpu, ctxt->emul_flags);
5479 kvm_rip_write(vcpu, ctxt->eip);
5480 if (r == EMULATE_DONE)
5481 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5482 if (!ctxt->have_exception ||
5483 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5484 __kvm_set_rflags(vcpu, ctxt->eflags);
5485
5486 /*
5487 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5488 * do nothing, and it will be requested again as soon as
5489 * the shadow expires. But we still need to check here,
5490 * because POPF has no interrupt shadow.
5491 */
5492 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5493 kvm_make_request(KVM_REQ_EVENT, vcpu);
5494 } else
5495 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5496
5497 return r;
5498 }
5499 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5500
5501 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5502 {
5503 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5504 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5505 size, port, &val, 1);
5506 /* do not return to emulator after return from userspace */
5507 vcpu->arch.pio.count = 0;
5508 return ret;
5509 }
5510 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5511
5512 static void tsc_bad(void *info)
5513 {
5514 __this_cpu_write(cpu_tsc_khz, 0);
5515 }
5516
5517 static void tsc_khz_changed(void *data)
5518 {
5519 struct cpufreq_freqs *freq = data;
5520 unsigned long khz = 0;
5521
5522 if (data)
5523 khz = freq->new;
5524 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5525 khz = cpufreq_quick_get(raw_smp_processor_id());
5526 if (!khz)
5527 khz = tsc_khz;
5528 __this_cpu_write(cpu_tsc_khz, khz);
5529 }
5530
5531 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5532 void *data)
5533 {
5534 struct cpufreq_freqs *freq = data;
5535 struct kvm *kvm;
5536 struct kvm_vcpu *vcpu;
5537 int i, send_ipi = 0;
5538
5539 /*
5540 * We allow guests to temporarily run on slowing clocks,
5541 * provided we notify them after, or to run on accelerating
5542 * clocks, provided we notify them before. Thus time never
5543 * goes backwards.
5544 *
5545 * However, we have a problem. We can't atomically update
5546 * the frequency of a given CPU from this function; it is
5547 * merely a notifier, which can be called from any CPU.
5548 * Changing the TSC frequency at arbitrary points in time
5549 * requires a recomputation of local variables related to
5550 * the TSC for each VCPU. We must flag these local variables
5551 * to be updated and be sure the update takes place with the
5552 * new frequency before any guests proceed.
5553 *
5554 * Unfortunately, the combination of hotplug CPU and frequency
5555 * change creates an intractable locking scenario; the order
5556 * of when these callouts happen is undefined with respect to
5557 * CPU hotplug, and they can race with each other. As such,
5558 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5559 * undefined; you can actually have a CPU frequency change take
5560 * place in between the computation of X and the setting of the
5561 * variable. To protect against this problem, all updates of
5562 * the per_cpu tsc_khz variable are done in an interrupt
5563 * protected IPI, and all callers wishing to update the value
5564 * must wait for a synchronous IPI to complete (which is trivial
5565 * if the caller is on the CPU already). This establishes the
5566 * necessary total order on variable updates.
5567 *
5568 * Note that because a guest time update may take place
5569 * anytime after the setting of the VCPU's request bit, the
5570 * correct TSC value must be set before the request. However,
5571 * to ensure the update actually makes it to any guest which
5572 * starts running in hardware virtualization between the set
5573 * and the acquisition of the spinlock, we must also ping the
5574 * CPU after setting the request bit.
5575 *
5576 */
5577
5578 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5579 return 0;
5580 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5581 return 0;
5582
5583 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5584
5585 spin_lock(&kvm_lock);
5586 list_for_each_entry(kvm, &vm_list, vm_list) {
5587 kvm_for_each_vcpu(i, vcpu, kvm) {
5588 if (vcpu->cpu != freq->cpu)
5589 continue;
5590 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5591 if (vcpu->cpu != smp_processor_id())
5592 send_ipi = 1;
5593 }
5594 }
5595 spin_unlock(&kvm_lock);
5596
5597 if (freq->old < freq->new && send_ipi) {
5598 /*
5599 * We upscale the frequency. Must make the guest
5600 * doesn't see old kvmclock values while running with
5601 * the new frequency, otherwise we risk the guest sees
5602 * time go backwards.
5603 *
5604 * In case we update the frequency for another cpu
5605 * (which might be in guest context) send an interrupt
5606 * to kick the cpu out of guest context. Next time
5607 * guest context is entered kvmclock will be updated,
5608 * so the guest will not see stale values.
5609 */
5610 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5611 }
5612 return 0;
5613 }
5614
5615 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5616 .notifier_call = kvmclock_cpufreq_notifier
5617 };
5618
5619 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5620 unsigned long action, void *hcpu)
5621 {
5622 unsigned int cpu = (unsigned long)hcpu;
5623
5624 switch (action) {
5625 case CPU_ONLINE:
5626 case CPU_DOWN_FAILED:
5627 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5628 break;
5629 case CPU_DOWN_PREPARE:
5630 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5631 break;
5632 }
5633 return NOTIFY_OK;
5634 }
5635
5636 static struct notifier_block kvmclock_cpu_notifier_block = {
5637 .notifier_call = kvmclock_cpu_notifier,
5638 .priority = -INT_MAX
5639 };
5640
5641 static void kvm_timer_init(void)
5642 {
5643 int cpu;
5644
5645 max_tsc_khz = tsc_khz;
5646
5647 cpu_notifier_register_begin();
5648 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5649 #ifdef CONFIG_CPU_FREQ
5650 struct cpufreq_policy policy;
5651 memset(&policy, 0, sizeof(policy));
5652 cpu = get_cpu();
5653 cpufreq_get_policy(&policy, cpu);
5654 if (policy.cpuinfo.max_freq)
5655 max_tsc_khz = policy.cpuinfo.max_freq;
5656 put_cpu();
5657 #endif
5658 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5659 CPUFREQ_TRANSITION_NOTIFIER);
5660 }
5661 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5662 for_each_online_cpu(cpu)
5663 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5664
5665 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5666 cpu_notifier_register_done();
5667
5668 }
5669
5670 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5671
5672 int kvm_is_in_guest(void)
5673 {
5674 return __this_cpu_read(current_vcpu) != NULL;
5675 }
5676
5677 static int kvm_is_user_mode(void)
5678 {
5679 int user_mode = 3;
5680
5681 if (__this_cpu_read(current_vcpu))
5682 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5683
5684 return user_mode != 0;
5685 }
5686
5687 static unsigned long kvm_get_guest_ip(void)
5688 {
5689 unsigned long ip = 0;
5690
5691 if (__this_cpu_read(current_vcpu))
5692 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5693
5694 return ip;
5695 }
5696
5697 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5698 .is_in_guest = kvm_is_in_guest,
5699 .is_user_mode = kvm_is_user_mode,
5700 .get_guest_ip = kvm_get_guest_ip,
5701 };
5702
5703 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5704 {
5705 __this_cpu_write(current_vcpu, vcpu);
5706 }
5707 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5708
5709 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5710 {
5711 __this_cpu_write(current_vcpu, NULL);
5712 }
5713 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5714
5715 static void kvm_set_mmio_spte_mask(void)
5716 {
5717 u64 mask;
5718 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5719
5720 /*
5721 * Set the reserved bits and the present bit of an paging-structure
5722 * entry to generate page fault with PFER.RSV = 1.
5723 */
5724 /* Mask the reserved physical address bits. */
5725 mask = rsvd_bits(maxphyaddr, 51);
5726
5727 /* Bit 62 is always reserved for 32bit host. */
5728 mask |= 0x3ull << 62;
5729
5730 /* Set the present bit. */
5731 mask |= 1ull;
5732
5733 #ifdef CONFIG_X86_64
5734 /*
5735 * If reserved bit is not supported, clear the present bit to disable
5736 * mmio page fault.
5737 */
5738 if (maxphyaddr == 52)
5739 mask &= ~1ull;
5740 #endif
5741
5742 kvm_mmu_set_mmio_spte_mask(mask);
5743 }
5744
5745 #ifdef CONFIG_X86_64
5746 static void pvclock_gtod_update_fn(struct work_struct *work)
5747 {
5748 struct kvm *kvm;
5749
5750 struct kvm_vcpu *vcpu;
5751 int i;
5752
5753 spin_lock(&kvm_lock);
5754 list_for_each_entry(kvm, &vm_list, vm_list)
5755 kvm_for_each_vcpu(i, vcpu, kvm)
5756 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
5757 atomic_set(&kvm_guest_has_master_clock, 0);
5758 spin_unlock(&kvm_lock);
5759 }
5760
5761 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5762
5763 /*
5764 * Notification about pvclock gtod data update.
5765 */
5766 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5767 void *priv)
5768 {
5769 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5770 struct timekeeper *tk = priv;
5771
5772 update_pvclock_gtod(tk);
5773
5774 /* disable master clock if host does not trust, or does not
5775 * use, TSC clocksource
5776 */
5777 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5778 atomic_read(&kvm_guest_has_master_clock) != 0)
5779 queue_work(system_long_wq, &pvclock_gtod_work);
5780
5781 return 0;
5782 }
5783
5784 static struct notifier_block pvclock_gtod_notifier = {
5785 .notifier_call = pvclock_gtod_notify,
5786 };
5787 #endif
5788
5789 int kvm_arch_init(void *opaque)
5790 {
5791 int r;
5792 struct kvm_x86_ops *ops = opaque;
5793
5794 if (kvm_x86_ops) {
5795 printk(KERN_ERR "kvm: already loaded the other module\n");
5796 r = -EEXIST;
5797 goto out;
5798 }
5799
5800 if (!ops->cpu_has_kvm_support()) {
5801 printk(KERN_ERR "kvm: no hardware support\n");
5802 r = -EOPNOTSUPP;
5803 goto out;
5804 }
5805 if (ops->disabled_by_bios()) {
5806 printk(KERN_ERR "kvm: disabled by bios\n");
5807 r = -EOPNOTSUPP;
5808 goto out;
5809 }
5810
5811 r = -ENOMEM;
5812 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5813 if (!shared_msrs) {
5814 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5815 goto out;
5816 }
5817
5818 r = kvm_mmu_module_init();
5819 if (r)
5820 goto out_free_percpu;
5821
5822 kvm_set_mmio_spte_mask();
5823
5824 kvm_x86_ops = ops;
5825
5826 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5827 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5828
5829 kvm_timer_init();
5830
5831 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5832
5833 if (cpu_has_xsave)
5834 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5835
5836 kvm_lapic_init();
5837 #ifdef CONFIG_X86_64
5838 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5839 #endif
5840
5841 return 0;
5842
5843 out_free_percpu:
5844 free_percpu(shared_msrs);
5845 out:
5846 return r;
5847 }
5848
5849 void kvm_arch_exit(void)
5850 {
5851 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5852
5853 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5854 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5855 CPUFREQ_TRANSITION_NOTIFIER);
5856 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5857 #ifdef CONFIG_X86_64
5858 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5859 #endif
5860 kvm_x86_ops = NULL;
5861 kvm_mmu_module_exit();
5862 free_percpu(shared_msrs);
5863 }
5864
5865 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
5866 {
5867 ++vcpu->stat.halt_exits;
5868 if (irqchip_in_kernel(vcpu->kvm)) {
5869 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5870 return 1;
5871 } else {
5872 vcpu->run->exit_reason = KVM_EXIT_HLT;
5873 return 0;
5874 }
5875 }
5876 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5877
5878 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5879 {
5880 kvm_x86_ops->skip_emulated_instruction(vcpu);
5881 return kvm_vcpu_halt(vcpu);
5882 }
5883 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5884
5885 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5886 {
5887 u64 param, ingpa, outgpa, ret;
5888 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5889 bool fast, longmode;
5890
5891 /*
5892 * hypercall generates UD from non zero cpl and real mode
5893 * per HYPER-V spec
5894 */
5895 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5896 kvm_queue_exception(vcpu, UD_VECTOR);
5897 return 0;
5898 }
5899
5900 longmode = is_64_bit_mode(vcpu);
5901
5902 if (!longmode) {
5903 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5904 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5905 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5906 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5907 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5908 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5909 }
5910 #ifdef CONFIG_X86_64
5911 else {
5912 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5913 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5914 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5915 }
5916 #endif
5917
5918 code = param & 0xffff;
5919 fast = (param >> 16) & 0x1;
5920 rep_cnt = (param >> 32) & 0xfff;
5921 rep_idx = (param >> 48) & 0xfff;
5922
5923 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5924
5925 switch (code) {
5926 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5927 kvm_vcpu_on_spin(vcpu);
5928 break;
5929 default:
5930 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5931 break;
5932 }
5933
5934 ret = res | (((u64)rep_done & 0xfff) << 32);
5935 if (longmode) {
5936 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5937 } else {
5938 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5939 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5940 }
5941
5942 return 1;
5943 }
5944
5945 /*
5946 * kvm_pv_kick_cpu_op: Kick a vcpu.
5947 *
5948 * @apicid - apicid of vcpu to be kicked.
5949 */
5950 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5951 {
5952 struct kvm_lapic_irq lapic_irq;
5953
5954 lapic_irq.shorthand = 0;
5955 lapic_irq.dest_mode = 0;
5956 lapic_irq.dest_id = apicid;
5957 lapic_irq.msi_redir_hint = false;
5958
5959 lapic_irq.delivery_mode = APIC_DM_REMRD;
5960 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
5961 }
5962
5963 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5964 {
5965 unsigned long nr, a0, a1, a2, a3, ret;
5966 int op_64_bit, r = 1;
5967
5968 kvm_x86_ops->skip_emulated_instruction(vcpu);
5969
5970 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5971 return kvm_hv_hypercall(vcpu);
5972
5973 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5974 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5975 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5976 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5977 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5978
5979 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5980
5981 op_64_bit = is_64_bit_mode(vcpu);
5982 if (!op_64_bit) {
5983 nr &= 0xFFFFFFFF;
5984 a0 &= 0xFFFFFFFF;
5985 a1 &= 0xFFFFFFFF;
5986 a2 &= 0xFFFFFFFF;
5987 a3 &= 0xFFFFFFFF;
5988 }
5989
5990 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5991 ret = -KVM_EPERM;
5992 goto out;
5993 }
5994
5995 switch (nr) {
5996 case KVM_HC_VAPIC_POLL_IRQ:
5997 ret = 0;
5998 break;
5999 case KVM_HC_KICK_CPU:
6000 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6001 ret = 0;
6002 break;
6003 default:
6004 ret = -KVM_ENOSYS;
6005 break;
6006 }
6007 out:
6008 if (!op_64_bit)
6009 ret = (u32)ret;
6010 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6011 ++vcpu->stat.hypercalls;
6012 return r;
6013 }
6014 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6015
6016 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
6017 {
6018 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6019 char instruction[3];
6020 unsigned long rip = kvm_rip_read(vcpu);
6021
6022 kvm_x86_ops->patch_hypercall(vcpu, instruction);
6023
6024 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
6025 }
6026
6027 /*
6028 * Check if userspace requested an interrupt window, and that the
6029 * interrupt window is open.
6030 *
6031 * No need to exit to userspace if we already have an interrupt queued.
6032 */
6033 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
6034 {
6035 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
6036 vcpu->run->request_interrupt_window &&
6037 kvm_arch_interrupt_allowed(vcpu));
6038 }
6039
6040 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
6041 {
6042 struct kvm_run *kvm_run = vcpu->run;
6043
6044 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
6045 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
6046 kvm_run->cr8 = kvm_get_cr8(vcpu);
6047 kvm_run->apic_base = kvm_get_apic_base(vcpu);
6048 if (irqchip_in_kernel(vcpu->kvm))
6049 kvm_run->ready_for_interrupt_injection = 1;
6050 else
6051 kvm_run->ready_for_interrupt_injection =
6052 kvm_arch_interrupt_allowed(vcpu) &&
6053 !kvm_cpu_has_interrupt(vcpu) &&
6054 !kvm_event_needs_reinjection(vcpu);
6055 }
6056
6057 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6058 {
6059 int max_irr, tpr;
6060
6061 if (!kvm_x86_ops->update_cr8_intercept)
6062 return;
6063
6064 if (!vcpu->arch.apic)
6065 return;
6066
6067 if (!vcpu->arch.apic->vapic_addr)
6068 max_irr = kvm_lapic_find_highest_irr(vcpu);
6069 else
6070 max_irr = -1;
6071
6072 if (max_irr != -1)
6073 max_irr >>= 4;
6074
6075 tpr = kvm_lapic_get_cr8(vcpu);
6076
6077 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6078 }
6079
6080 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
6081 {
6082 int r;
6083
6084 /* try to reinject previous events if any */
6085 if (vcpu->arch.exception.pending) {
6086 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6087 vcpu->arch.exception.has_error_code,
6088 vcpu->arch.exception.error_code);
6089
6090 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6091 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6092 X86_EFLAGS_RF);
6093
6094 if (vcpu->arch.exception.nr == DB_VECTOR &&
6095 (vcpu->arch.dr7 & DR7_GD)) {
6096 vcpu->arch.dr7 &= ~DR7_GD;
6097 kvm_update_dr7(vcpu);
6098 }
6099
6100 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6101 vcpu->arch.exception.has_error_code,
6102 vcpu->arch.exception.error_code,
6103 vcpu->arch.exception.reinject);
6104 return 0;
6105 }
6106
6107 if (vcpu->arch.nmi_injected) {
6108 kvm_x86_ops->set_nmi(vcpu);
6109 return 0;
6110 }
6111
6112 if (vcpu->arch.interrupt.pending) {
6113 kvm_x86_ops->set_irq(vcpu);
6114 return 0;
6115 }
6116
6117 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6118 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6119 if (r != 0)
6120 return r;
6121 }
6122
6123 /* try to inject new event if pending */
6124 if (vcpu->arch.nmi_pending) {
6125 if (kvm_x86_ops->nmi_allowed(vcpu)) {
6126 --vcpu->arch.nmi_pending;
6127 vcpu->arch.nmi_injected = true;
6128 kvm_x86_ops->set_nmi(vcpu);
6129 }
6130 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6131 /*
6132 * Because interrupts can be injected asynchronously, we are
6133 * calling check_nested_events again here to avoid a race condition.
6134 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6135 * proposal and current concerns. Perhaps we should be setting
6136 * KVM_REQ_EVENT only on certain events and not unconditionally?
6137 */
6138 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6139 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6140 if (r != 0)
6141 return r;
6142 }
6143 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6144 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6145 false);
6146 kvm_x86_ops->set_irq(vcpu);
6147 }
6148 }
6149 return 0;
6150 }
6151
6152 static void process_nmi(struct kvm_vcpu *vcpu)
6153 {
6154 unsigned limit = 2;
6155
6156 /*
6157 * x86 is limited to one NMI running, and one NMI pending after it.
6158 * If an NMI is already in progress, limit further NMIs to just one.
6159 * Otherwise, allow two (and we'll inject the first one immediately).
6160 */
6161 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6162 limit = 1;
6163
6164 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6165 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6166 kvm_make_request(KVM_REQ_EVENT, vcpu);
6167 }
6168
6169 #define put_smstate(type, buf, offset, val) \
6170 *(type *)((buf) + (offset) - 0x7e00) = val
6171
6172 static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6173 {
6174 u32 flags = 0;
6175 flags |= seg->g << 23;
6176 flags |= seg->db << 22;
6177 flags |= seg->l << 21;
6178 flags |= seg->avl << 20;
6179 flags |= seg->present << 15;
6180 flags |= seg->dpl << 13;
6181 flags |= seg->s << 12;
6182 flags |= seg->type << 8;
6183 return flags;
6184 }
6185
6186 static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6187 {
6188 struct kvm_segment seg;
6189 int offset;
6190
6191 kvm_get_segment(vcpu, &seg, n);
6192 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6193
6194 if (n < 3)
6195 offset = 0x7f84 + n * 12;
6196 else
6197 offset = 0x7f2c + (n - 3) * 12;
6198
6199 put_smstate(u32, buf, offset + 8, seg.base);
6200 put_smstate(u32, buf, offset + 4, seg.limit);
6201 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6202 }
6203
6204 static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6205 {
6206 struct kvm_segment seg;
6207 int offset;
6208 u16 flags;
6209
6210 kvm_get_segment(vcpu, &seg, n);
6211 offset = 0x7e00 + n * 16;
6212
6213 flags = process_smi_get_segment_flags(&seg) >> 8;
6214 put_smstate(u16, buf, offset, seg.selector);
6215 put_smstate(u16, buf, offset + 2, flags);
6216 put_smstate(u32, buf, offset + 4, seg.limit);
6217 put_smstate(u64, buf, offset + 8, seg.base);
6218 }
6219
6220 static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6221 {
6222 struct desc_ptr dt;
6223 struct kvm_segment seg;
6224 unsigned long val;
6225 int i;
6226
6227 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6228 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6229 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6230 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6231
6232 for (i = 0; i < 8; i++)
6233 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6234
6235 kvm_get_dr(vcpu, 6, &val);
6236 put_smstate(u32, buf, 0x7fcc, (u32)val);
6237 kvm_get_dr(vcpu, 7, &val);
6238 put_smstate(u32, buf, 0x7fc8, (u32)val);
6239
6240 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6241 put_smstate(u32, buf, 0x7fc4, seg.selector);
6242 put_smstate(u32, buf, 0x7f64, seg.base);
6243 put_smstate(u32, buf, 0x7f60, seg.limit);
6244 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6245
6246 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6247 put_smstate(u32, buf, 0x7fc0, seg.selector);
6248 put_smstate(u32, buf, 0x7f80, seg.base);
6249 put_smstate(u32, buf, 0x7f7c, seg.limit);
6250 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6251
6252 kvm_x86_ops->get_gdt(vcpu, &dt);
6253 put_smstate(u32, buf, 0x7f74, dt.address);
6254 put_smstate(u32, buf, 0x7f70, dt.size);
6255
6256 kvm_x86_ops->get_idt(vcpu, &dt);
6257 put_smstate(u32, buf, 0x7f58, dt.address);
6258 put_smstate(u32, buf, 0x7f54, dt.size);
6259
6260 for (i = 0; i < 6; i++)
6261 process_smi_save_seg_32(vcpu, buf, i);
6262
6263 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6264
6265 /* revision id */
6266 put_smstate(u32, buf, 0x7efc, 0x00020000);
6267 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6268 }
6269
6270 static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6271 {
6272 #ifdef CONFIG_X86_64
6273 struct desc_ptr dt;
6274 struct kvm_segment seg;
6275 unsigned long val;
6276 int i;
6277
6278 for (i = 0; i < 16; i++)
6279 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6280
6281 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6282 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6283
6284 kvm_get_dr(vcpu, 6, &val);
6285 put_smstate(u64, buf, 0x7f68, val);
6286 kvm_get_dr(vcpu, 7, &val);
6287 put_smstate(u64, buf, 0x7f60, val);
6288
6289 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6290 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6291 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6292
6293 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6294
6295 /* revision id */
6296 put_smstate(u32, buf, 0x7efc, 0x00020064);
6297
6298 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6299
6300 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6301 put_smstate(u16, buf, 0x7e90, seg.selector);
6302 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6303 put_smstate(u32, buf, 0x7e94, seg.limit);
6304 put_smstate(u64, buf, 0x7e98, seg.base);
6305
6306 kvm_x86_ops->get_idt(vcpu, &dt);
6307 put_smstate(u32, buf, 0x7e84, dt.size);
6308 put_smstate(u64, buf, 0x7e88, dt.address);
6309
6310 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6311 put_smstate(u16, buf, 0x7e70, seg.selector);
6312 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6313 put_smstate(u32, buf, 0x7e74, seg.limit);
6314 put_smstate(u64, buf, 0x7e78, seg.base);
6315
6316 kvm_x86_ops->get_gdt(vcpu, &dt);
6317 put_smstate(u32, buf, 0x7e64, dt.size);
6318 put_smstate(u64, buf, 0x7e68, dt.address);
6319
6320 for (i = 0; i < 6; i++)
6321 process_smi_save_seg_64(vcpu, buf, i);
6322 #else
6323 WARN_ON_ONCE(1);
6324 #endif
6325 }
6326
6327 static void process_smi(struct kvm_vcpu *vcpu)
6328 {
6329 struct kvm_segment cs, ds;
6330 struct desc_ptr dt;
6331 char buf[512];
6332 u32 cr0;
6333
6334 if (is_smm(vcpu)) {
6335 vcpu->arch.smi_pending = true;
6336 return;
6337 }
6338
6339 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6340 vcpu->arch.hflags |= HF_SMM_MASK;
6341 memset(buf, 0, 512);
6342 if (guest_cpuid_has_longmode(vcpu))
6343 process_smi_save_state_64(vcpu, buf);
6344 else
6345 process_smi_save_state_32(vcpu, buf);
6346
6347 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6348
6349 if (kvm_x86_ops->get_nmi_mask(vcpu))
6350 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6351 else
6352 kvm_x86_ops->set_nmi_mask(vcpu, true);
6353
6354 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6355 kvm_rip_write(vcpu, 0x8000);
6356
6357 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6358 kvm_x86_ops->set_cr0(vcpu, cr0);
6359 vcpu->arch.cr0 = cr0;
6360
6361 kvm_x86_ops->set_cr4(vcpu, 0);
6362
6363 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6364 dt.address = dt.size = 0;
6365 kvm_x86_ops->set_idt(vcpu, &dt);
6366
6367 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6368
6369 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6370 cs.base = vcpu->arch.smbase;
6371
6372 ds.selector = 0;
6373 ds.base = 0;
6374
6375 cs.limit = ds.limit = 0xffffffff;
6376 cs.type = ds.type = 0x3;
6377 cs.dpl = ds.dpl = 0;
6378 cs.db = ds.db = 0;
6379 cs.s = ds.s = 1;
6380 cs.l = ds.l = 0;
6381 cs.g = ds.g = 1;
6382 cs.avl = ds.avl = 0;
6383 cs.present = ds.present = 1;
6384 cs.unusable = ds.unusable = 0;
6385 cs.padding = ds.padding = 0;
6386
6387 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6388 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6389 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6390 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6391 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6392 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6393
6394 if (guest_cpuid_has_longmode(vcpu))
6395 kvm_x86_ops->set_efer(vcpu, 0);
6396
6397 kvm_update_cpuid(vcpu);
6398 kvm_mmu_reset_context(vcpu);
6399 }
6400
6401 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6402 {
6403 u64 eoi_exit_bitmap[4];
6404 u32 tmr[8];
6405
6406 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6407 return;
6408
6409 memset(eoi_exit_bitmap, 0, 32);
6410 memset(tmr, 0, 32);
6411
6412 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
6413 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6414 kvm_apic_update_tmr(vcpu, tmr);
6415 }
6416
6417 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6418 {
6419 ++vcpu->stat.tlb_flush;
6420 kvm_x86_ops->tlb_flush(vcpu);
6421 }
6422
6423 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6424 {
6425 struct page *page = NULL;
6426
6427 if (!irqchip_in_kernel(vcpu->kvm))
6428 return;
6429
6430 if (!kvm_x86_ops->set_apic_access_page_addr)
6431 return;
6432
6433 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6434 if (is_error_page(page))
6435 return;
6436 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6437
6438 /*
6439 * Do not pin apic access page in memory, the MMU notifier
6440 * will call us again if it is migrated or swapped out.
6441 */
6442 put_page(page);
6443 }
6444 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6445
6446 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6447 unsigned long address)
6448 {
6449 /*
6450 * The physical address of apic access page is stored in the VMCS.
6451 * Update it when it becomes invalid.
6452 */
6453 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6454 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6455 }
6456
6457 /*
6458 * Returns 1 to let vcpu_run() continue the guest execution loop without
6459 * exiting to the userspace. Otherwise, the value will be returned to the
6460 * userspace.
6461 */
6462 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6463 {
6464 int r;
6465 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
6466 vcpu->run->request_interrupt_window;
6467 bool req_immediate_exit = false;
6468
6469 if (vcpu->requests) {
6470 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6471 kvm_mmu_unload(vcpu);
6472 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6473 __kvm_migrate_timers(vcpu);
6474 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6475 kvm_gen_update_masterclock(vcpu->kvm);
6476 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6477 kvm_gen_kvmclock_update(vcpu);
6478 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6479 r = kvm_guest_time_update(vcpu);
6480 if (unlikely(r))
6481 goto out;
6482 }
6483 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6484 kvm_mmu_sync_roots(vcpu);
6485 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6486 kvm_vcpu_flush_tlb(vcpu);
6487 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6488 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6489 r = 0;
6490 goto out;
6491 }
6492 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6493 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6494 r = 0;
6495 goto out;
6496 }
6497 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
6498 vcpu->fpu_active = 0;
6499 kvm_x86_ops->fpu_deactivate(vcpu);
6500 }
6501 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6502 /* Page is swapped out. Do synthetic halt */
6503 vcpu->arch.apf.halted = true;
6504 r = 1;
6505 goto out;
6506 }
6507 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6508 record_steal_time(vcpu);
6509 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6510 process_smi(vcpu);
6511 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6512 process_nmi(vcpu);
6513 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6514 kvm_pmu_handle_event(vcpu);
6515 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6516 kvm_pmu_deliver_pmi(vcpu);
6517 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6518 vcpu_scan_ioapic(vcpu);
6519 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6520 kvm_vcpu_reload_apic_access_page(vcpu);
6521 }
6522
6523 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6524 kvm_apic_accept_events(vcpu);
6525 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6526 r = 1;
6527 goto out;
6528 }
6529
6530 if (inject_pending_event(vcpu, req_int_win) != 0)
6531 req_immediate_exit = true;
6532 /* enable NMI/IRQ window open exits if needed */
6533 else if (vcpu->arch.nmi_pending)
6534 kvm_x86_ops->enable_nmi_window(vcpu);
6535 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6536 kvm_x86_ops->enable_irq_window(vcpu);
6537
6538 if (kvm_lapic_enabled(vcpu)) {
6539 /*
6540 * Update architecture specific hints for APIC
6541 * virtual interrupt delivery.
6542 */
6543 if (kvm_x86_ops->hwapic_irr_update)
6544 kvm_x86_ops->hwapic_irr_update(vcpu,
6545 kvm_lapic_find_highest_irr(vcpu));
6546 update_cr8_intercept(vcpu);
6547 kvm_lapic_sync_to_vapic(vcpu);
6548 }
6549 }
6550
6551 r = kvm_mmu_reload(vcpu);
6552 if (unlikely(r)) {
6553 goto cancel_injection;
6554 }
6555
6556 preempt_disable();
6557
6558 kvm_x86_ops->prepare_guest_switch(vcpu);
6559 if (vcpu->fpu_active)
6560 kvm_load_guest_fpu(vcpu);
6561 kvm_load_guest_xcr0(vcpu);
6562
6563 vcpu->mode = IN_GUEST_MODE;
6564
6565 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6566
6567 /* We should set ->mode before check ->requests,
6568 * see the comment in make_all_cpus_request.
6569 */
6570 smp_mb__after_srcu_read_unlock();
6571
6572 local_irq_disable();
6573
6574 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6575 || need_resched() || signal_pending(current)) {
6576 vcpu->mode = OUTSIDE_GUEST_MODE;
6577 smp_wmb();
6578 local_irq_enable();
6579 preempt_enable();
6580 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6581 r = 1;
6582 goto cancel_injection;
6583 }
6584
6585 if (req_immediate_exit)
6586 smp_send_reschedule(vcpu->cpu);
6587
6588 __kvm_guest_enter();
6589
6590 if (unlikely(vcpu->arch.switch_db_regs)) {
6591 set_debugreg(0, 7);
6592 set_debugreg(vcpu->arch.eff_db[0], 0);
6593 set_debugreg(vcpu->arch.eff_db[1], 1);
6594 set_debugreg(vcpu->arch.eff_db[2], 2);
6595 set_debugreg(vcpu->arch.eff_db[3], 3);
6596 set_debugreg(vcpu->arch.dr6, 6);
6597 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6598 }
6599
6600 trace_kvm_entry(vcpu->vcpu_id);
6601 wait_lapic_expire(vcpu);
6602 kvm_x86_ops->run(vcpu);
6603
6604 /*
6605 * Do this here before restoring debug registers on the host. And
6606 * since we do this before handling the vmexit, a DR access vmexit
6607 * can (a) read the correct value of the debug registers, (b) set
6608 * KVM_DEBUGREG_WONT_EXIT again.
6609 */
6610 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6611 int i;
6612
6613 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6614 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6615 for (i = 0; i < KVM_NR_DB_REGS; i++)
6616 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6617 }
6618
6619 /*
6620 * If the guest has used debug registers, at least dr7
6621 * will be disabled while returning to the host.
6622 * If we don't have active breakpoints in the host, we don't
6623 * care about the messed up debug address registers. But if
6624 * we have some of them active, restore the old state.
6625 */
6626 if (hw_breakpoint_active())
6627 hw_breakpoint_restore();
6628
6629 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6630 native_read_tsc());
6631
6632 vcpu->mode = OUTSIDE_GUEST_MODE;
6633 smp_wmb();
6634
6635 /* Interrupt is enabled by handle_external_intr() */
6636 kvm_x86_ops->handle_external_intr(vcpu);
6637
6638 ++vcpu->stat.exits;
6639
6640 /*
6641 * We must have an instruction between local_irq_enable() and
6642 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6643 * the interrupt shadow. The stat.exits increment will do nicely.
6644 * But we need to prevent reordering, hence this barrier():
6645 */
6646 barrier();
6647
6648 kvm_guest_exit();
6649
6650 preempt_enable();
6651
6652 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6653
6654 /*
6655 * Profile KVM exit RIPs:
6656 */
6657 if (unlikely(prof_on == KVM_PROFILING)) {
6658 unsigned long rip = kvm_rip_read(vcpu);
6659 profile_hit(KVM_PROFILING, (void *)rip);
6660 }
6661
6662 if (unlikely(vcpu->arch.tsc_always_catchup))
6663 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6664
6665 if (vcpu->arch.apic_attention)
6666 kvm_lapic_sync_from_vapic(vcpu);
6667
6668 r = kvm_x86_ops->handle_exit(vcpu);
6669 return r;
6670
6671 cancel_injection:
6672 kvm_x86_ops->cancel_injection(vcpu);
6673 if (unlikely(vcpu->arch.apic_attention))
6674 kvm_lapic_sync_from_vapic(vcpu);
6675 out:
6676 return r;
6677 }
6678
6679 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6680 {
6681 if (!kvm_arch_vcpu_runnable(vcpu)) {
6682 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6683 kvm_vcpu_block(vcpu);
6684 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6685 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6686 return 1;
6687 }
6688
6689 kvm_apic_accept_events(vcpu);
6690 switch(vcpu->arch.mp_state) {
6691 case KVM_MP_STATE_HALTED:
6692 vcpu->arch.pv.pv_unhalted = false;
6693 vcpu->arch.mp_state =
6694 KVM_MP_STATE_RUNNABLE;
6695 case KVM_MP_STATE_RUNNABLE:
6696 vcpu->arch.apf.halted = false;
6697 break;
6698 case KVM_MP_STATE_INIT_RECEIVED:
6699 break;
6700 default:
6701 return -EINTR;
6702 break;
6703 }
6704 return 1;
6705 }
6706
6707 static int vcpu_run(struct kvm_vcpu *vcpu)
6708 {
6709 int r;
6710 struct kvm *kvm = vcpu->kvm;
6711
6712 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6713
6714 for (;;) {
6715 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6716 !vcpu->arch.apf.halted)
6717 r = vcpu_enter_guest(vcpu);
6718 else
6719 r = vcpu_block(kvm, vcpu);
6720 if (r <= 0)
6721 break;
6722
6723 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6724 if (kvm_cpu_has_pending_timer(vcpu))
6725 kvm_inject_pending_timer_irqs(vcpu);
6726
6727 if (dm_request_for_irq_injection(vcpu)) {
6728 r = -EINTR;
6729 vcpu->run->exit_reason = KVM_EXIT_INTR;
6730 ++vcpu->stat.request_irq_exits;
6731 break;
6732 }
6733
6734 kvm_check_async_pf_completion(vcpu);
6735
6736 if (signal_pending(current)) {
6737 r = -EINTR;
6738 vcpu->run->exit_reason = KVM_EXIT_INTR;
6739 ++vcpu->stat.signal_exits;
6740 break;
6741 }
6742 if (need_resched()) {
6743 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6744 cond_resched();
6745 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6746 }
6747 }
6748
6749 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6750
6751 return r;
6752 }
6753
6754 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6755 {
6756 int r;
6757 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6758 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6759 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6760 if (r != EMULATE_DONE)
6761 return 0;
6762 return 1;
6763 }
6764
6765 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6766 {
6767 BUG_ON(!vcpu->arch.pio.count);
6768
6769 return complete_emulated_io(vcpu);
6770 }
6771
6772 /*
6773 * Implements the following, as a state machine:
6774 *
6775 * read:
6776 * for each fragment
6777 * for each mmio piece in the fragment
6778 * write gpa, len
6779 * exit
6780 * copy data
6781 * execute insn
6782 *
6783 * write:
6784 * for each fragment
6785 * for each mmio piece in the fragment
6786 * write gpa, len
6787 * copy data
6788 * exit
6789 */
6790 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6791 {
6792 struct kvm_run *run = vcpu->run;
6793 struct kvm_mmio_fragment *frag;
6794 unsigned len;
6795
6796 BUG_ON(!vcpu->mmio_needed);
6797
6798 /* Complete previous fragment */
6799 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6800 len = min(8u, frag->len);
6801 if (!vcpu->mmio_is_write)
6802 memcpy(frag->data, run->mmio.data, len);
6803
6804 if (frag->len <= 8) {
6805 /* Switch to the next fragment. */
6806 frag++;
6807 vcpu->mmio_cur_fragment++;
6808 } else {
6809 /* Go forward to the next mmio piece. */
6810 frag->data += len;
6811 frag->gpa += len;
6812 frag->len -= len;
6813 }
6814
6815 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6816 vcpu->mmio_needed = 0;
6817
6818 /* FIXME: return into emulator if single-stepping. */
6819 if (vcpu->mmio_is_write)
6820 return 1;
6821 vcpu->mmio_read_completed = 1;
6822 return complete_emulated_io(vcpu);
6823 }
6824
6825 run->exit_reason = KVM_EXIT_MMIO;
6826 run->mmio.phys_addr = frag->gpa;
6827 if (vcpu->mmio_is_write)
6828 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6829 run->mmio.len = min(8u, frag->len);
6830 run->mmio.is_write = vcpu->mmio_is_write;
6831 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6832 return 0;
6833 }
6834
6835
6836 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6837 {
6838 struct fpu *fpu = &current->thread.fpu;
6839 int r;
6840 sigset_t sigsaved;
6841
6842 fpu__activate_curr(fpu);
6843
6844 if (vcpu->sigset_active)
6845 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6846
6847 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6848 kvm_vcpu_block(vcpu);
6849 kvm_apic_accept_events(vcpu);
6850 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6851 r = -EAGAIN;
6852 goto out;
6853 }
6854
6855 /* re-sync apic's tpr */
6856 if (!irqchip_in_kernel(vcpu->kvm)) {
6857 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6858 r = -EINVAL;
6859 goto out;
6860 }
6861 }
6862
6863 if (unlikely(vcpu->arch.complete_userspace_io)) {
6864 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6865 vcpu->arch.complete_userspace_io = NULL;
6866 r = cui(vcpu);
6867 if (r <= 0)
6868 goto out;
6869 } else
6870 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6871
6872 r = vcpu_run(vcpu);
6873
6874 out:
6875 post_kvm_run_save(vcpu);
6876 if (vcpu->sigset_active)
6877 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6878
6879 return r;
6880 }
6881
6882 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6883 {
6884 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6885 /*
6886 * We are here if userspace calls get_regs() in the middle of
6887 * instruction emulation. Registers state needs to be copied
6888 * back from emulation context to vcpu. Userspace shouldn't do
6889 * that usually, but some bad designed PV devices (vmware
6890 * backdoor interface) need this to work
6891 */
6892 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6893 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6894 }
6895 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6896 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6897 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6898 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6899 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6900 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6901 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6902 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6903 #ifdef CONFIG_X86_64
6904 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6905 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6906 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6907 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6908 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6909 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6910 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6911 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6912 #endif
6913
6914 regs->rip = kvm_rip_read(vcpu);
6915 regs->rflags = kvm_get_rflags(vcpu);
6916
6917 return 0;
6918 }
6919
6920 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6921 {
6922 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6923 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6924
6925 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6926 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6927 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6928 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6929 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6930 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6931 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6932 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6933 #ifdef CONFIG_X86_64
6934 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6935 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6936 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6937 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6938 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6939 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6940 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6941 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6942 #endif
6943
6944 kvm_rip_write(vcpu, regs->rip);
6945 kvm_set_rflags(vcpu, regs->rflags);
6946
6947 vcpu->arch.exception.pending = false;
6948
6949 kvm_make_request(KVM_REQ_EVENT, vcpu);
6950
6951 return 0;
6952 }
6953
6954 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6955 {
6956 struct kvm_segment cs;
6957
6958 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6959 *db = cs.db;
6960 *l = cs.l;
6961 }
6962 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6963
6964 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6965 struct kvm_sregs *sregs)
6966 {
6967 struct desc_ptr dt;
6968
6969 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6970 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6971 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6972 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6973 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6974 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6975
6976 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6977 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6978
6979 kvm_x86_ops->get_idt(vcpu, &dt);
6980 sregs->idt.limit = dt.size;
6981 sregs->idt.base = dt.address;
6982 kvm_x86_ops->get_gdt(vcpu, &dt);
6983 sregs->gdt.limit = dt.size;
6984 sregs->gdt.base = dt.address;
6985
6986 sregs->cr0 = kvm_read_cr0(vcpu);
6987 sregs->cr2 = vcpu->arch.cr2;
6988 sregs->cr3 = kvm_read_cr3(vcpu);
6989 sregs->cr4 = kvm_read_cr4(vcpu);
6990 sregs->cr8 = kvm_get_cr8(vcpu);
6991 sregs->efer = vcpu->arch.efer;
6992 sregs->apic_base = kvm_get_apic_base(vcpu);
6993
6994 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6995
6996 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6997 set_bit(vcpu->arch.interrupt.nr,
6998 (unsigned long *)sregs->interrupt_bitmap);
6999
7000 return 0;
7001 }
7002
7003 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7004 struct kvm_mp_state *mp_state)
7005 {
7006 kvm_apic_accept_events(vcpu);
7007 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7008 vcpu->arch.pv.pv_unhalted)
7009 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7010 else
7011 mp_state->mp_state = vcpu->arch.mp_state;
7012
7013 return 0;
7014 }
7015
7016 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7017 struct kvm_mp_state *mp_state)
7018 {
7019 if (!kvm_vcpu_has_lapic(vcpu) &&
7020 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7021 return -EINVAL;
7022
7023 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7024 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7025 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7026 } else
7027 vcpu->arch.mp_state = mp_state->mp_state;
7028 kvm_make_request(KVM_REQ_EVENT, vcpu);
7029 return 0;
7030 }
7031
7032 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7033 int reason, bool has_error_code, u32 error_code)
7034 {
7035 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7036 int ret;
7037
7038 init_emulate_ctxt(vcpu);
7039
7040 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
7041 has_error_code, error_code);
7042
7043 if (ret)
7044 return EMULATE_FAIL;
7045
7046 kvm_rip_write(vcpu, ctxt->eip);
7047 kvm_set_rflags(vcpu, ctxt->eflags);
7048 kvm_make_request(KVM_REQ_EVENT, vcpu);
7049 return EMULATE_DONE;
7050 }
7051 EXPORT_SYMBOL_GPL(kvm_task_switch);
7052
7053 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7054 struct kvm_sregs *sregs)
7055 {
7056 struct msr_data apic_base_msr;
7057 int mmu_reset_needed = 0;
7058 int pending_vec, max_bits, idx;
7059 struct desc_ptr dt;
7060
7061 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7062 return -EINVAL;
7063
7064 dt.size = sregs->idt.limit;
7065 dt.address = sregs->idt.base;
7066 kvm_x86_ops->set_idt(vcpu, &dt);
7067 dt.size = sregs->gdt.limit;
7068 dt.address = sregs->gdt.base;
7069 kvm_x86_ops->set_gdt(vcpu, &dt);
7070
7071 vcpu->arch.cr2 = sregs->cr2;
7072 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
7073 vcpu->arch.cr3 = sregs->cr3;
7074 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7075
7076 kvm_set_cr8(vcpu, sregs->cr8);
7077
7078 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
7079 kvm_x86_ops->set_efer(vcpu, sregs->efer);
7080 apic_base_msr.data = sregs->apic_base;
7081 apic_base_msr.host_initiated = true;
7082 kvm_set_apic_base(vcpu, &apic_base_msr);
7083
7084 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
7085 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
7086 vcpu->arch.cr0 = sregs->cr0;
7087
7088 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
7089 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7090 if (sregs->cr4 & X86_CR4_OSXSAVE)
7091 kvm_update_cpuid(vcpu);
7092
7093 idx = srcu_read_lock(&vcpu->kvm->srcu);
7094 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
7095 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7096 mmu_reset_needed = 1;
7097 }
7098 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7099
7100 if (mmu_reset_needed)
7101 kvm_mmu_reset_context(vcpu);
7102
7103 max_bits = KVM_NR_INTERRUPTS;
7104 pending_vec = find_first_bit(
7105 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7106 if (pending_vec < max_bits) {
7107 kvm_queue_interrupt(vcpu, pending_vec, false);
7108 pr_debug("Set back pending irq %d\n", pending_vec);
7109 }
7110
7111 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7112 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7113 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7114 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7115 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7116 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7117
7118 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7119 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7120
7121 update_cr8_intercept(vcpu);
7122
7123 /* Older userspace won't unhalt the vcpu on reset. */
7124 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
7125 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
7126 !is_protmode(vcpu))
7127 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7128
7129 kvm_make_request(KVM_REQ_EVENT, vcpu);
7130
7131 return 0;
7132 }
7133
7134 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7135 struct kvm_guest_debug *dbg)
7136 {
7137 unsigned long rflags;
7138 int i, r;
7139
7140 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7141 r = -EBUSY;
7142 if (vcpu->arch.exception.pending)
7143 goto out;
7144 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7145 kvm_queue_exception(vcpu, DB_VECTOR);
7146 else
7147 kvm_queue_exception(vcpu, BP_VECTOR);
7148 }
7149
7150 /*
7151 * Read rflags as long as potentially injected trace flags are still
7152 * filtered out.
7153 */
7154 rflags = kvm_get_rflags(vcpu);
7155
7156 vcpu->guest_debug = dbg->control;
7157 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7158 vcpu->guest_debug = 0;
7159
7160 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7161 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7162 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
7163 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
7164 } else {
7165 for (i = 0; i < KVM_NR_DB_REGS; i++)
7166 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
7167 }
7168 kvm_update_dr7(vcpu);
7169
7170 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7171 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7172 get_segment_base(vcpu, VCPU_SREG_CS);
7173
7174 /*
7175 * Trigger an rflags update that will inject or remove the trace
7176 * flags.
7177 */
7178 kvm_set_rflags(vcpu, rflags);
7179
7180 kvm_x86_ops->update_db_bp_intercept(vcpu);
7181
7182 r = 0;
7183
7184 out:
7185
7186 return r;
7187 }
7188
7189 /*
7190 * Translate a guest virtual address to a guest physical address.
7191 */
7192 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7193 struct kvm_translation *tr)
7194 {
7195 unsigned long vaddr = tr->linear_address;
7196 gpa_t gpa;
7197 int idx;
7198
7199 idx = srcu_read_lock(&vcpu->kvm->srcu);
7200 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
7201 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7202 tr->physical_address = gpa;
7203 tr->valid = gpa != UNMAPPED_GVA;
7204 tr->writeable = 1;
7205 tr->usermode = 0;
7206
7207 return 0;
7208 }
7209
7210 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7211 {
7212 struct fxregs_state *fxsave =
7213 &vcpu->arch.guest_fpu.state.fxsave;
7214
7215 memcpy(fpu->fpr, fxsave->st_space, 128);
7216 fpu->fcw = fxsave->cwd;
7217 fpu->fsw = fxsave->swd;
7218 fpu->ftwx = fxsave->twd;
7219 fpu->last_opcode = fxsave->fop;
7220 fpu->last_ip = fxsave->rip;
7221 fpu->last_dp = fxsave->rdp;
7222 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7223
7224 return 0;
7225 }
7226
7227 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7228 {
7229 struct fxregs_state *fxsave =
7230 &vcpu->arch.guest_fpu.state.fxsave;
7231
7232 memcpy(fxsave->st_space, fpu->fpr, 128);
7233 fxsave->cwd = fpu->fcw;
7234 fxsave->swd = fpu->fsw;
7235 fxsave->twd = fpu->ftwx;
7236 fxsave->fop = fpu->last_opcode;
7237 fxsave->rip = fpu->last_ip;
7238 fxsave->rdp = fpu->last_dp;
7239 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7240
7241 return 0;
7242 }
7243
7244 static void fx_init(struct kvm_vcpu *vcpu)
7245 {
7246 fpstate_init(&vcpu->arch.guest_fpu.state);
7247 if (cpu_has_xsaves)
7248 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7249 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7250
7251 /*
7252 * Ensure guest xcr0 is valid for loading
7253 */
7254 vcpu->arch.xcr0 = XSTATE_FP;
7255
7256 vcpu->arch.cr0 |= X86_CR0_ET;
7257 }
7258
7259 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7260 {
7261 if (vcpu->guest_fpu_loaded)
7262 return;
7263
7264 /*
7265 * Restore all possible states in the guest,
7266 * and assume host would use all available bits.
7267 * Guest xcr0 would be loaded later.
7268 */
7269 kvm_put_guest_xcr0(vcpu);
7270 vcpu->guest_fpu_loaded = 1;
7271 __kernel_fpu_begin();
7272 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
7273 trace_kvm_fpu(1);
7274 }
7275
7276 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7277 {
7278 kvm_put_guest_xcr0(vcpu);
7279
7280 if (!vcpu->guest_fpu_loaded) {
7281 vcpu->fpu_counter = 0;
7282 return;
7283 }
7284
7285 vcpu->guest_fpu_loaded = 0;
7286 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7287 __kernel_fpu_end();
7288 ++vcpu->stat.fpu_reload;
7289 /*
7290 * If using eager FPU mode, or if the guest is a frequent user
7291 * of the FPU, just leave the FPU active for next time.
7292 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7293 * the FPU in bursts will revert to loading it on demand.
7294 */
7295 if (!vcpu->arch.eager_fpu) {
7296 if (++vcpu->fpu_counter < 5)
7297 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7298 }
7299 trace_kvm_fpu(0);
7300 }
7301
7302 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7303 {
7304 kvmclock_reset(vcpu);
7305
7306 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7307 kvm_x86_ops->vcpu_free(vcpu);
7308 }
7309
7310 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7311 unsigned int id)
7312 {
7313 struct kvm_vcpu *vcpu;
7314
7315 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7316 printk_once(KERN_WARNING
7317 "kvm: SMP vm created on host with unstable TSC; "
7318 "guest TSC will not be reliable\n");
7319
7320 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7321
7322 return vcpu;
7323 }
7324
7325 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7326 {
7327 int r;
7328
7329 kvm_vcpu_mtrr_init(vcpu);
7330 r = vcpu_load(vcpu);
7331 if (r)
7332 return r;
7333 kvm_vcpu_reset(vcpu, false);
7334 kvm_mmu_setup(vcpu);
7335 vcpu_put(vcpu);
7336 return r;
7337 }
7338
7339 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7340 {
7341 struct msr_data msr;
7342 struct kvm *kvm = vcpu->kvm;
7343
7344 if (vcpu_load(vcpu))
7345 return;
7346 msr.data = 0x0;
7347 msr.index = MSR_IA32_TSC;
7348 msr.host_initiated = true;
7349 kvm_write_tsc(vcpu, &msr);
7350 vcpu_put(vcpu);
7351
7352 if (!kvmclock_periodic_sync)
7353 return;
7354
7355 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7356 KVMCLOCK_SYNC_PERIOD);
7357 }
7358
7359 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7360 {
7361 int r;
7362 vcpu->arch.apf.msr_val = 0;
7363
7364 r = vcpu_load(vcpu);
7365 BUG_ON(r);
7366 kvm_mmu_unload(vcpu);
7367 vcpu_put(vcpu);
7368
7369 kvm_x86_ops->vcpu_free(vcpu);
7370 }
7371
7372 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7373 {
7374 vcpu->arch.hflags = 0;
7375
7376 atomic_set(&vcpu->arch.nmi_queued, 0);
7377 vcpu->arch.nmi_pending = 0;
7378 vcpu->arch.nmi_injected = false;
7379 kvm_clear_interrupt_queue(vcpu);
7380 kvm_clear_exception_queue(vcpu);
7381
7382 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7383 kvm_update_dr0123(vcpu);
7384 vcpu->arch.dr6 = DR6_INIT;
7385 kvm_update_dr6(vcpu);
7386 vcpu->arch.dr7 = DR7_FIXED_1;
7387 kvm_update_dr7(vcpu);
7388
7389 vcpu->arch.cr2 = 0;
7390
7391 kvm_make_request(KVM_REQ_EVENT, vcpu);
7392 vcpu->arch.apf.msr_val = 0;
7393 vcpu->arch.st.msr_val = 0;
7394
7395 kvmclock_reset(vcpu);
7396
7397 kvm_clear_async_pf_completion_queue(vcpu);
7398 kvm_async_pf_hash_reset(vcpu);
7399 vcpu->arch.apf.halted = false;
7400
7401 if (!init_event) {
7402 kvm_pmu_reset(vcpu);
7403 vcpu->arch.smbase = 0x30000;
7404 }
7405
7406 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7407 vcpu->arch.regs_avail = ~0;
7408 vcpu->arch.regs_dirty = ~0;
7409
7410 kvm_x86_ops->vcpu_reset(vcpu, init_event);
7411 }
7412
7413 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7414 {
7415 struct kvm_segment cs;
7416
7417 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7418 cs.selector = vector << 8;
7419 cs.base = vector << 12;
7420 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7421 kvm_rip_write(vcpu, 0);
7422 }
7423
7424 int kvm_arch_hardware_enable(void)
7425 {
7426 struct kvm *kvm;
7427 struct kvm_vcpu *vcpu;
7428 int i;
7429 int ret;
7430 u64 local_tsc;
7431 u64 max_tsc = 0;
7432 bool stable, backwards_tsc = false;
7433
7434 kvm_shared_msr_cpu_online();
7435 ret = kvm_x86_ops->hardware_enable();
7436 if (ret != 0)
7437 return ret;
7438
7439 local_tsc = native_read_tsc();
7440 stable = !check_tsc_unstable();
7441 list_for_each_entry(kvm, &vm_list, vm_list) {
7442 kvm_for_each_vcpu(i, vcpu, kvm) {
7443 if (!stable && vcpu->cpu == smp_processor_id())
7444 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7445 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7446 backwards_tsc = true;
7447 if (vcpu->arch.last_host_tsc > max_tsc)
7448 max_tsc = vcpu->arch.last_host_tsc;
7449 }
7450 }
7451 }
7452
7453 /*
7454 * Sometimes, even reliable TSCs go backwards. This happens on
7455 * platforms that reset TSC during suspend or hibernate actions, but
7456 * maintain synchronization. We must compensate. Fortunately, we can
7457 * detect that condition here, which happens early in CPU bringup,
7458 * before any KVM threads can be running. Unfortunately, we can't
7459 * bring the TSCs fully up to date with real time, as we aren't yet far
7460 * enough into CPU bringup that we know how much real time has actually
7461 * elapsed; our helper function, get_kernel_ns() will be using boot
7462 * variables that haven't been updated yet.
7463 *
7464 * So we simply find the maximum observed TSC above, then record the
7465 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7466 * the adjustment will be applied. Note that we accumulate
7467 * adjustments, in case multiple suspend cycles happen before some VCPU
7468 * gets a chance to run again. In the event that no KVM threads get a
7469 * chance to run, we will miss the entire elapsed period, as we'll have
7470 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7471 * loose cycle time. This isn't too big a deal, since the loss will be
7472 * uniform across all VCPUs (not to mention the scenario is extremely
7473 * unlikely). It is possible that a second hibernate recovery happens
7474 * much faster than a first, causing the observed TSC here to be
7475 * smaller; this would require additional padding adjustment, which is
7476 * why we set last_host_tsc to the local tsc observed here.
7477 *
7478 * N.B. - this code below runs only on platforms with reliable TSC,
7479 * as that is the only way backwards_tsc is set above. Also note
7480 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7481 * have the same delta_cyc adjustment applied if backwards_tsc
7482 * is detected. Note further, this adjustment is only done once,
7483 * as we reset last_host_tsc on all VCPUs to stop this from being
7484 * called multiple times (one for each physical CPU bringup).
7485 *
7486 * Platforms with unreliable TSCs don't have to deal with this, they
7487 * will be compensated by the logic in vcpu_load, which sets the TSC to
7488 * catchup mode. This will catchup all VCPUs to real time, but cannot
7489 * guarantee that they stay in perfect synchronization.
7490 */
7491 if (backwards_tsc) {
7492 u64 delta_cyc = max_tsc - local_tsc;
7493 backwards_tsc_observed = true;
7494 list_for_each_entry(kvm, &vm_list, vm_list) {
7495 kvm_for_each_vcpu(i, vcpu, kvm) {
7496 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7497 vcpu->arch.last_host_tsc = local_tsc;
7498 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7499 }
7500
7501 /*
7502 * We have to disable TSC offset matching.. if you were
7503 * booting a VM while issuing an S4 host suspend....
7504 * you may have some problem. Solving this issue is
7505 * left as an exercise to the reader.
7506 */
7507 kvm->arch.last_tsc_nsec = 0;
7508 kvm->arch.last_tsc_write = 0;
7509 }
7510
7511 }
7512 return 0;
7513 }
7514
7515 void kvm_arch_hardware_disable(void)
7516 {
7517 kvm_x86_ops->hardware_disable();
7518 drop_user_return_notifiers();
7519 }
7520
7521 int kvm_arch_hardware_setup(void)
7522 {
7523 int r;
7524
7525 r = kvm_x86_ops->hardware_setup();
7526 if (r != 0)
7527 return r;
7528
7529 kvm_init_msr_list();
7530 return 0;
7531 }
7532
7533 void kvm_arch_hardware_unsetup(void)
7534 {
7535 kvm_x86_ops->hardware_unsetup();
7536 }
7537
7538 void kvm_arch_check_processor_compat(void *rtn)
7539 {
7540 kvm_x86_ops->check_processor_compatibility(rtn);
7541 }
7542
7543 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7544 {
7545 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7546 }
7547
7548 struct static_key kvm_no_apic_vcpu __read_mostly;
7549
7550 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7551 {
7552 struct page *page;
7553 struct kvm *kvm;
7554 int r;
7555
7556 BUG_ON(vcpu->kvm == NULL);
7557 kvm = vcpu->kvm;
7558
7559 vcpu->arch.pv.pv_unhalted = false;
7560 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7561 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
7562 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7563 else
7564 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7565
7566 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7567 if (!page) {
7568 r = -ENOMEM;
7569 goto fail;
7570 }
7571 vcpu->arch.pio_data = page_address(page);
7572
7573 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7574
7575 r = kvm_mmu_create(vcpu);
7576 if (r < 0)
7577 goto fail_free_pio_data;
7578
7579 if (irqchip_in_kernel(kvm)) {
7580 r = kvm_create_lapic(vcpu);
7581 if (r < 0)
7582 goto fail_mmu_destroy;
7583 } else
7584 static_key_slow_inc(&kvm_no_apic_vcpu);
7585
7586 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7587 GFP_KERNEL);
7588 if (!vcpu->arch.mce_banks) {
7589 r = -ENOMEM;
7590 goto fail_free_lapic;
7591 }
7592 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7593
7594 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7595 r = -ENOMEM;
7596 goto fail_free_mce_banks;
7597 }
7598
7599 fx_init(vcpu);
7600
7601 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7602 vcpu->arch.pv_time_enabled = false;
7603
7604 vcpu->arch.guest_supported_xcr0 = 0;
7605 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7606
7607 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7608
7609 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7610
7611 kvm_async_pf_hash_reset(vcpu);
7612 kvm_pmu_init(vcpu);
7613
7614 return 0;
7615
7616 fail_free_mce_banks:
7617 kfree(vcpu->arch.mce_banks);
7618 fail_free_lapic:
7619 kvm_free_lapic(vcpu);
7620 fail_mmu_destroy:
7621 kvm_mmu_destroy(vcpu);
7622 fail_free_pio_data:
7623 free_page((unsigned long)vcpu->arch.pio_data);
7624 fail:
7625 return r;
7626 }
7627
7628 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7629 {
7630 int idx;
7631
7632 kvm_pmu_destroy(vcpu);
7633 kfree(vcpu->arch.mce_banks);
7634 kvm_free_lapic(vcpu);
7635 idx = srcu_read_lock(&vcpu->kvm->srcu);
7636 kvm_mmu_destroy(vcpu);
7637 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7638 free_page((unsigned long)vcpu->arch.pio_data);
7639 if (!irqchip_in_kernel(vcpu->kvm))
7640 static_key_slow_dec(&kvm_no_apic_vcpu);
7641 }
7642
7643 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7644 {
7645 kvm_x86_ops->sched_in(vcpu, cpu);
7646 }
7647
7648 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7649 {
7650 if (type)
7651 return -EINVAL;
7652
7653 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
7654 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7655 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7656 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7657 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7658
7659 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7660 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7661 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7662 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7663 &kvm->arch.irq_sources_bitmap);
7664
7665 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7666 mutex_init(&kvm->arch.apic_map_lock);
7667 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7668
7669 pvclock_update_vm_gtod_copy(kvm);
7670
7671 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7672 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7673
7674 return 0;
7675 }
7676
7677 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7678 {
7679 int r;
7680 r = vcpu_load(vcpu);
7681 BUG_ON(r);
7682 kvm_mmu_unload(vcpu);
7683 vcpu_put(vcpu);
7684 }
7685
7686 static void kvm_free_vcpus(struct kvm *kvm)
7687 {
7688 unsigned int i;
7689 struct kvm_vcpu *vcpu;
7690
7691 /*
7692 * Unpin any mmu pages first.
7693 */
7694 kvm_for_each_vcpu(i, vcpu, kvm) {
7695 kvm_clear_async_pf_completion_queue(vcpu);
7696 kvm_unload_vcpu_mmu(vcpu);
7697 }
7698 kvm_for_each_vcpu(i, vcpu, kvm)
7699 kvm_arch_vcpu_free(vcpu);
7700
7701 mutex_lock(&kvm->lock);
7702 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7703 kvm->vcpus[i] = NULL;
7704
7705 atomic_set(&kvm->online_vcpus, 0);
7706 mutex_unlock(&kvm->lock);
7707 }
7708
7709 void kvm_arch_sync_events(struct kvm *kvm)
7710 {
7711 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7712 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7713 kvm_free_all_assigned_devices(kvm);
7714 kvm_free_pit(kvm);
7715 }
7716
7717 int __x86_set_memory_region(struct kvm *kvm,
7718 const struct kvm_userspace_memory_region *mem)
7719 {
7720 int i, r;
7721
7722 /* Called with kvm->slots_lock held. */
7723 BUG_ON(mem->slot >= KVM_MEM_SLOTS_NUM);
7724
7725 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
7726 struct kvm_userspace_memory_region m = *mem;
7727
7728 m.slot |= i << 16;
7729 r = __kvm_set_memory_region(kvm, &m);
7730 if (r < 0)
7731 return r;
7732 }
7733
7734 return 0;
7735 }
7736 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7737
7738 int x86_set_memory_region(struct kvm *kvm,
7739 const struct kvm_userspace_memory_region *mem)
7740 {
7741 int r;
7742
7743 mutex_lock(&kvm->slots_lock);
7744 r = __x86_set_memory_region(kvm, mem);
7745 mutex_unlock(&kvm->slots_lock);
7746
7747 return r;
7748 }
7749 EXPORT_SYMBOL_GPL(x86_set_memory_region);
7750
7751 void kvm_arch_destroy_vm(struct kvm *kvm)
7752 {
7753 if (current->mm == kvm->mm) {
7754 /*
7755 * Free memory regions allocated on behalf of userspace,
7756 * unless the the memory map has changed due to process exit
7757 * or fd copying.
7758 */
7759 struct kvm_userspace_memory_region mem;
7760 memset(&mem, 0, sizeof(mem));
7761 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7762 x86_set_memory_region(kvm, &mem);
7763
7764 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7765 x86_set_memory_region(kvm, &mem);
7766
7767 mem.slot = TSS_PRIVATE_MEMSLOT;
7768 x86_set_memory_region(kvm, &mem);
7769 }
7770 kvm_iommu_unmap_guest(kvm);
7771 kfree(kvm->arch.vpic);
7772 kfree(kvm->arch.vioapic);
7773 kvm_free_vcpus(kvm);
7774 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7775 }
7776
7777 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7778 struct kvm_memory_slot *dont)
7779 {
7780 int i;
7781
7782 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7783 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7784 kvfree(free->arch.rmap[i]);
7785 free->arch.rmap[i] = NULL;
7786 }
7787 if (i == 0)
7788 continue;
7789
7790 if (!dont || free->arch.lpage_info[i - 1] !=
7791 dont->arch.lpage_info[i - 1]) {
7792 kvfree(free->arch.lpage_info[i - 1]);
7793 free->arch.lpage_info[i - 1] = NULL;
7794 }
7795 }
7796 }
7797
7798 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7799 unsigned long npages)
7800 {
7801 int i;
7802
7803 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7804 unsigned long ugfn;
7805 int lpages;
7806 int level = i + 1;
7807
7808 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7809 slot->base_gfn, level) + 1;
7810
7811 slot->arch.rmap[i] =
7812 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7813 if (!slot->arch.rmap[i])
7814 goto out_free;
7815 if (i == 0)
7816 continue;
7817
7818 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7819 sizeof(*slot->arch.lpage_info[i - 1]));
7820 if (!slot->arch.lpage_info[i - 1])
7821 goto out_free;
7822
7823 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7824 slot->arch.lpage_info[i - 1][0].write_count = 1;
7825 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7826 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
7827 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7828 /*
7829 * If the gfn and userspace address are not aligned wrt each
7830 * other, or if explicitly asked to, disable large page
7831 * support for this slot
7832 */
7833 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7834 !kvm_largepages_enabled()) {
7835 unsigned long j;
7836
7837 for (j = 0; j < lpages; ++j)
7838 slot->arch.lpage_info[i - 1][j].write_count = 1;
7839 }
7840 }
7841
7842 return 0;
7843
7844 out_free:
7845 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7846 kvfree(slot->arch.rmap[i]);
7847 slot->arch.rmap[i] = NULL;
7848 if (i == 0)
7849 continue;
7850
7851 kvfree(slot->arch.lpage_info[i - 1]);
7852 slot->arch.lpage_info[i - 1] = NULL;
7853 }
7854 return -ENOMEM;
7855 }
7856
7857 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
7858 {
7859 /*
7860 * memslots->generation has been incremented.
7861 * mmio generation may have reached its maximum value.
7862 */
7863 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
7864 }
7865
7866 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7867 struct kvm_memory_slot *memslot,
7868 const struct kvm_userspace_memory_region *mem,
7869 enum kvm_mr_change change)
7870 {
7871 /*
7872 * Only private memory slots need to be mapped here since
7873 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
7874 */
7875 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7876 unsigned long userspace_addr;
7877
7878 /*
7879 * MAP_SHARED to prevent internal slot pages from being moved
7880 * by fork()/COW.
7881 */
7882 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7883 PROT_READ | PROT_WRITE,
7884 MAP_SHARED | MAP_ANONYMOUS, 0);
7885
7886 if (IS_ERR((void *)userspace_addr))
7887 return PTR_ERR((void *)userspace_addr);
7888
7889 memslot->userspace_addr = userspace_addr;
7890 }
7891
7892 return 0;
7893 }
7894
7895 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7896 struct kvm_memory_slot *new)
7897 {
7898 /* Still write protect RO slot */
7899 if (new->flags & KVM_MEM_READONLY) {
7900 kvm_mmu_slot_remove_write_access(kvm, new);
7901 return;
7902 }
7903
7904 /*
7905 * Call kvm_x86_ops dirty logging hooks when they are valid.
7906 *
7907 * kvm_x86_ops->slot_disable_log_dirty is called when:
7908 *
7909 * - KVM_MR_CREATE with dirty logging is disabled
7910 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7911 *
7912 * The reason is, in case of PML, we need to set D-bit for any slots
7913 * with dirty logging disabled in order to eliminate unnecessary GPA
7914 * logging in PML buffer (and potential PML buffer full VMEXT). This
7915 * guarantees leaving PML enabled during guest's lifetime won't have
7916 * any additonal overhead from PML when guest is running with dirty
7917 * logging disabled for memory slots.
7918 *
7919 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7920 * to dirty logging mode.
7921 *
7922 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7923 *
7924 * In case of write protect:
7925 *
7926 * Write protect all pages for dirty logging.
7927 *
7928 * All the sptes including the large sptes which point to this
7929 * slot are set to readonly. We can not create any new large
7930 * spte on this slot until the end of the logging.
7931 *
7932 * See the comments in fast_page_fault().
7933 */
7934 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7935 if (kvm_x86_ops->slot_enable_log_dirty)
7936 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7937 else
7938 kvm_mmu_slot_remove_write_access(kvm, new);
7939 } else {
7940 if (kvm_x86_ops->slot_disable_log_dirty)
7941 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7942 }
7943 }
7944
7945 void kvm_arch_commit_memory_region(struct kvm *kvm,
7946 const struct kvm_userspace_memory_region *mem,
7947 const struct kvm_memory_slot *old,
7948 const struct kvm_memory_slot *new,
7949 enum kvm_mr_change change)
7950 {
7951 int nr_mmu_pages = 0;
7952
7953 if (change == KVM_MR_DELETE && old->id >= KVM_USER_MEM_SLOTS) {
7954 int ret;
7955
7956 ret = vm_munmap(old->userspace_addr,
7957 old->npages * PAGE_SIZE);
7958 if (ret < 0)
7959 printk(KERN_WARNING
7960 "kvm_vm_ioctl_set_memory_region: "
7961 "failed to munmap memory\n");
7962 }
7963
7964 if (!kvm->arch.n_requested_mmu_pages)
7965 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7966
7967 if (nr_mmu_pages)
7968 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
7969
7970 /*
7971 * Dirty logging tracks sptes in 4k granularity, meaning that large
7972 * sptes have to be split. If live migration is successful, the guest
7973 * in the source machine will be destroyed and large sptes will be
7974 * created in the destination. However, if the guest continues to run
7975 * in the source machine (for example if live migration fails), small
7976 * sptes will remain around and cause bad performance.
7977 *
7978 * Scan sptes if dirty logging has been stopped, dropping those
7979 * which can be collapsed into a single large-page spte. Later
7980 * page faults will create the large-page sptes.
7981 */
7982 if ((change != KVM_MR_DELETE) &&
7983 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7984 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7985 kvm_mmu_zap_collapsible_sptes(kvm, new);
7986
7987 /*
7988 * Set up write protection and/or dirty logging for the new slot.
7989 *
7990 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7991 * been zapped so no dirty logging staff is needed for old slot. For
7992 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7993 * new and it's also covered when dealing with the new slot.
7994 *
7995 * FIXME: const-ify all uses of struct kvm_memory_slot.
7996 */
7997 if (change != KVM_MR_DELETE)
7998 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
7999 }
8000
8001 void kvm_arch_flush_shadow_all(struct kvm *kvm)
8002 {
8003 kvm_mmu_invalidate_zap_all_pages(kvm);
8004 }
8005
8006 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8007 struct kvm_memory_slot *slot)
8008 {
8009 kvm_mmu_invalidate_zap_all_pages(kvm);
8010 }
8011
8012 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8013 {
8014 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8015 kvm_x86_ops->check_nested_events(vcpu, false);
8016
8017 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8018 !vcpu->arch.apf.halted)
8019 || !list_empty_careful(&vcpu->async_pf.done)
8020 || kvm_apic_has_events(vcpu)
8021 || vcpu->arch.pv.pv_unhalted
8022 || atomic_read(&vcpu->arch.nmi_queued) ||
8023 (kvm_arch_interrupt_allowed(vcpu) &&
8024 kvm_cpu_has_interrupt(vcpu));
8025 }
8026
8027 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
8028 {
8029 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
8030 }
8031
8032 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8033 {
8034 return kvm_x86_ops->interrupt_allowed(vcpu);
8035 }
8036
8037 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
8038 {
8039 if (is_64_bit_mode(vcpu))
8040 return kvm_rip_read(vcpu);
8041 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8042 kvm_rip_read(vcpu));
8043 }
8044 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
8045
8046 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8047 {
8048 return kvm_get_linear_rip(vcpu) == linear_rip;
8049 }
8050 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8051
8052 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8053 {
8054 unsigned long rflags;
8055
8056 rflags = kvm_x86_ops->get_rflags(vcpu);
8057 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8058 rflags &= ~X86_EFLAGS_TF;
8059 return rflags;
8060 }
8061 EXPORT_SYMBOL_GPL(kvm_get_rflags);
8062
8063 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8064 {
8065 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
8066 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
8067 rflags |= X86_EFLAGS_TF;
8068 kvm_x86_ops->set_rflags(vcpu, rflags);
8069 }
8070
8071 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8072 {
8073 __kvm_set_rflags(vcpu, rflags);
8074 kvm_make_request(KVM_REQ_EVENT, vcpu);
8075 }
8076 EXPORT_SYMBOL_GPL(kvm_set_rflags);
8077
8078 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8079 {
8080 int r;
8081
8082 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
8083 work->wakeup_all)
8084 return;
8085
8086 r = kvm_mmu_reload(vcpu);
8087 if (unlikely(r))
8088 return;
8089
8090 if (!vcpu->arch.mmu.direct_map &&
8091 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8092 return;
8093
8094 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8095 }
8096
8097 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8098 {
8099 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8100 }
8101
8102 static inline u32 kvm_async_pf_next_probe(u32 key)
8103 {
8104 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8105 }
8106
8107 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8108 {
8109 u32 key = kvm_async_pf_hash_fn(gfn);
8110
8111 while (vcpu->arch.apf.gfns[key] != ~0)
8112 key = kvm_async_pf_next_probe(key);
8113
8114 vcpu->arch.apf.gfns[key] = gfn;
8115 }
8116
8117 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8118 {
8119 int i;
8120 u32 key = kvm_async_pf_hash_fn(gfn);
8121
8122 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
8123 (vcpu->arch.apf.gfns[key] != gfn &&
8124 vcpu->arch.apf.gfns[key] != ~0); i++)
8125 key = kvm_async_pf_next_probe(key);
8126
8127 return key;
8128 }
8129
8130 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8131 {
8132 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8133 }
8134
8135 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8136 {
8137 u32 i, j, k;
8138
8139 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8140 while (true) {
8141 vcpu->arch.apf.gfns[i] = ~0;
8142 do {
8143 j = kvm_async_pf_next_probe(j);
8144 if (vcpu->arch.apf.gfns[j] == ~0)
8145 return;
8146 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8147 /*
8148 * k lies cyclically in ]i,j]
8149 * | i.k.j |
8150 * |....j i.k.| or |.k..j i...|
8151 */
8152 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8153 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8154 i = j;
8155 }
8156 }
8157
8158 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8159 {
8160
8161 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8162 sizeof(val));
8163 }
8164
8165 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8166 struct kvm_async_pf *work)
8167 {
8168 struct x86_exception fault;
8169
8170 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
8171 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
8172
8173 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
8174 (vcpu->arch.apf.send_user_only &&
8175 kvm_x86_ops->get_cpl(vcpu) == 0))
8176 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8177 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
8178 fault.vector = PF_VECTOR;
8179 fault.error_code_valid = true;
8180 fault.error_code = 0;
8181 fault.nested_page_fault = false;
8182 fault.address = work->arch.token;
8183 kvm_inject_page_fault(vcpu, &fault);
8184 }
8185 }
8186
8187 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8188 struct kvm_async_pf *work)
8189 {
8190 struct x86_exception fault;
8191
8192 trace_kvm_async_pf_ready(work->arch.token, work->gva);
8193 if (work->wakeup_all)
8194 work->arch.token = ~0; /* broadcast wakeup */
8195 else
8196 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8197
8198 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8199 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8200 fault.vector = PF_VECTOR;
8201 fault.error_code_valid = true;
8202 fault.error_code = 0;
8203 fault.nested_page_fault = false;
8204 fault.address = work->arch.token;
8205 kvm_inject_page_fault(vcpu, &fault);
8206 }
8207 vcpu->arch.apf.halted = false;
8208 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8209 }
8210
8211 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8212 {
8213 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8214 return true;
8215 else
8216 return !kvm_event_needs_reinjection(vcpu) &&
8217 kvm_x86_ops->interrupt_allowed(vcpu);
8218 }
8219
8220 void kvm_arch_start_assignment(struct kvm *kvm)
8221 {
8222 atomic_inc(&kvm->arch.assigned_device_count);
8223 }
8224 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8225
8226 void kvm_arch_end_assignment(struct kvm *kvm)
8227 {
8228 atomic_dec(&kvm->arch.assigned_device_count);
8229 }
8230 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8231
8232 bool kvm_arch_has_assigned_device(struct kvm *kvm)
8233 {
8234 return atomic_read(&kvm->arch.assigned_device_count);
8235 }
8236 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8237
8238 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8239 {
8240 atomic_inc(&kvm->arch.noncoherent_dma_count);
8241 }
8242 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8243
8244 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8245 {
8246 atomic_dec(&kvm->arch.noncoherent_dma_count);
8247 }
8248 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8249
8250 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8251 {
8252 return atomic_read(&kvm->arch.noncoherent_dma_count);
8253 }
8254 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8255
8256 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8257 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8258 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8259 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8260 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
8261 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
8262 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
8263 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
8264 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
8265 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
8266 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
8267 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
8268 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
8269 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
8270 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
Linux with added FPC-III support