arch/xtensa/boot/dts/xtfpga.dtsi

   1 / {
   2         compatible = "cdns,xtensa-xtfpga";
   3         #address-cells = <1>;
   4         #size-cells = <1>;
   5         interrupt-parent = <&pic>;
   6
   7         chosen {
   8                 bootargs = "earlycon=uart8250,mmio32,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
   9         };
  10
  11         memory@0 {
  12                 device_type = "memory";
  13                 reg = <0x00000000 0x06000000>;
  14         };
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19                 cpu@0 {
  20                         compatible = "cdns,xtensa-cpu";
  21                         reg = <0>;
  22                         /* Filled in by platform_setup from FPGA register
  23                          * clock-frequency = <100000000>;
  24                          */
  25                 };
  26         };
  27
  28         pic: pic {
  29                 compatible = "cdns,xtensa-pic";
  30                 /* one cell: internal irq number,
  31                  * two cells: second cell == 0: internal irq number
  32                  *            second cell == 1: external irq number
  33                  */
  34                 #interrupt-cells = <2>;
  35                 interrupt-controller;
  36         };
  37
  38         clocks {
  39                 osc: main-oscillator {
  40                         #clock-cells = <0>;
  41                         compatible = "fixed-clock";
  42                 };
  43
  44                 clk54: clk54 {
  45                         #clock-cells = <0>;
  46                         compatible = "fixed-clock";
  47                         clock-frequency = <54000000>;
  48                 };
  49         };
  50
  51         soc {
  52                 #address-cells = <1>;
  53                 #size-cells = <1>;
  54                 compatible = "simple-bus";
  55                 ranges = <0x00000000 0xf0000000 0x10000000>;
  56
  57                 serial0: serial@0d050020 {
  58                         device_type = "serial";
  59                         compatible = "ns16550a";
  60                         no-loopback-test;
  61                         reg = <0x0d050020 0x20>;
  62                         reg-shift = <2>;
  63                         interrupts = <0 1>; /* external irq 0 */
  64                         clocks = <&osc>;
  65                 };
  66
  67                 enet0: ethoc@0d030000 {
  68                         compatible = "opencores,ethoc";
  69                         reg = <0x0d030000 0x4000 0x0d800000 0x4000>;
  70                         interrupts = <1 1>; /* external irq 1 */
  71                         local-mac-address = [00 50 c2 13 6f 00];
  72                         clocks = <&osc>;
  73                 };
  74
  75                 i2s0: xtfpga-i2s@0d080000 {
  76                         #sound-dai-cells = <0>;
  77                         compatible = "cdns,xtfpga-i2s";
  78                         reg = <0x0d080000 0x40>;
  79                         interrupts = <2 1>; /* external irq 2 */
  80                         clocks = <&cdce706 4>;
  81                 };
  82
  83                 i2c0: i2c-master@0d090000 {
  84                         compatible = "opencores,i2c-ocores";
  85                         #address-cells = <1>;
  86                         #size-cells = <0>;
  87                         reg = <0x0d090000 0x20>;
  88                         reg-shift = <2>;
  89                         reg-io-width = <1>;
  90                         interrupts = <4 1>;
  91                         clocks = <&osc>;
  92
  93                         cdce706: clock-synth@69 {
  94                                 compatible = "ti,cdce706";
  95                                 #clock-cells = <1>;
  96                                 reg = <0x69>;
  97                                 clocks = <&clk54>;
  98                                 clock-names = "clk_in0";
  99                         };
 100                 };
 101
 102                 spi0: spi-master@0d0a0000 {
 103                         compatible = "cdns,xtfpga-spi";
 104                         #address-cells = <1>;
 105                         #size-cells = <0>;
 106                         reg = <0x0d0a0000 0xc>;
 107
 108                         tlv320aic23: sound-codec@0 {
 109                                 #sound-dai-cells = <0>;
 110                                 compatible = "tlv320aic23";
 111                                 reg = <0>;
 112                                 spi-max-frequency = <12500000>;
 113                         };
 114                 };
 115         };
 116
 117         sound {
 118                 compatible = "simple-audio-card";
 119                 simple-audio-card,format = "i2s";
 120                 simple-audio-card,mclk-fs = <256>;
 121
 122                 simple-audio-card,cpu {
 123                         sound-dai = <&i2s0>;
 124                 };
 125
 126                 simple-audio-card,codec {
 127                         sound-dai = <&tlv320aic23>;
 128                         simple-audio-card,bitclock-master = <0>;
 129                         simple-audio-card,frame-master = <0>;
 130                         clocks = <&cdce706 4>;
 131                 };
 132         };
 133 };