drivers/bus/uniphier-system-bus.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   4  */
   5
   6 #include <linux/io.h>
   7 #include <linux/log2.h>
   8 #include <linux/module.h>
   9 #include <linux/of.h>
  10 #include <linux/of_address.h>
  11 #include <linux/of_platform.h>
  12 #include <linux/platform_device.h>
  13
  14 /* System Bus Controller registers */
  15 #define UNIPHIER_SBC_BASE       0x100   /* base address of bank0 space */
  16 #define    UNIPHIER_SBC_BASE_BE         BIT(0)  /* bank_enable */
  17 #define UNIPHIER_SBC_CTRL0      0x200   /* timing parameter 0 of bank0 */
  18 #define UNIPHIER_SBC_CTRL1      0x204   /* timing parameter 1 of bank0 */
  19 #define UNIPHIER_SBC_CTRL2      0x208   /* timing parameter 2 of bank0 */
  20 #define UNIPHIER_SBC_CTRL3      0x20c   /* timing parameter 3 of bank0 */
  21 #define UNIPHIER_SBC_CTRL4      0x300   /* timing parameter 4 of bank0 */
  22
  23 #define UNIPHIER_SBC_STRIDE     0x10    /* register stride to next bank */
  24 #define UNIPHIER_SBC_NR_BANKS   8       /* number of banks (chip select) */
  25 #define UNIPHIER_SBC_BASE_DUMMY 0xffffffff      /* data to squash bank 0, 1 */
  26
  27 struct uniphier_system_bus_bank {
  28         u32 base;
  29         u32 end;
  30 };
  31
  32 struct uniphier_system_bus_priv {
  33         struct device *dev;
  34         void __iomem *membase;
  35         struct uniphier_system_bus_bank bank[UNIPHIER_SBC_NR_BANKS];
  36 };
  37
  38 static int uniphier_system_bus_add_bank(struct uniphier_system_bus_priv *priv,
  39                                         int bank, u32 addr, u64 paddr, u32 size)
  40 {
  41         u64 end, mask;
  42
  43         dev_dbg(priv->dev,
  44                 "range found: bank = %d, addr = %08x, paddr = %08llx, size = %08x\n",
  45                 bank, addr, paddr, size);
  46
  47         if (bank >= ARRAY_SIZE(priv->bank)) {
  48                 dev_err(priv->dev, "unsupported bank number %d\n", bank);
  49                 return -EINVAL;
  50         }
  51
  52         if (priv->bank[bank].base || priv->bank[bank].end) {
  53                 dev_err(priv->dev,
  54                         "range for bank %d has already been specified\n", bank);
  55                 return -EINVAL;
  56         }
  57
  58         if (paddr > U32_MAX) {
  59                 dev_err(priv->dev, "base address %llx is too high\n", paddr);
  60                 return -EINVAL;
  61         }
  62
  63         end = paddr + size;
  64
  65         if (addr > paddr) {
  66                 dev_err(priv->dev,
  67                         "base %08x cannot be mapped to %08llx of parent\n",
  68                         addr, paddr);
  69                 return -EINVAL;
  70         }
  71         paddr -= addr;
  72
  73         paddr = round_down(paddr, 0x00020000);
  74         end = round_up(end, 0x00020000);
  75
  76         if (end > U32_MAX) {
  77                 dev_err(priv->dev, "end address %08llx is too high\n", end);
  78                 return -EINVAL;
  79         }
  80         mask = paddr ^ (end - 1);
  81         mask = roundup_pow_of_two(mask);
  82
  83         paddr = round_down(paddr, mask);
  84         end = round_up(end, mask);
  85
  86         priv->bank[bank].base = paddr;
  87         priv->bank[bank].end = end;
  88
  89         dev_dbg(priv->dev, "range added: bank = %d, addr = %08x, end = %08x\n",
  90                 bank, priv->bank[bank].base, priv->bank[bank].end);
  91
  92         return 0;
  93 }
  94
  95 static int uniphier_system_bus_check_overlap(
  96                                 const struct uniphier_system_bus_priv *priv)
  97 {
  98         int i, j;
  99
 100         for (i = 0; i < ARRAY_SIZE(priv->bank); i++) {
 101                 for (j = i + 1; j < ARRAY_SIZE(priv->bank); j++) {
 102                         if (priv->bank[i].end > priv->bank[j].base &&
 103                             priv->bank[i].base < priv->bank[j].end) {
 104                                 dev_err(priv->dev,
 105                                         "region overlap between bank%d and bank%d\n",
 106                                         i, j);
 107                                 return -EINVAL;
 108                         }
 109                 }
 110         }
 111
 112         return 0;
 113 }
 114
 115 static void uniphier_system_bus_check_boot_swap(
 116                                         struct uniphier_system_bus_priv *priv)
 117 {
 118         void __iomem *base_reg = priv->membase + UNIPHIER_SBC_BASE;
 119         int is_swapped;
 120
 121         is_swapped = !(readl(base_reg) & UNIPHIER_SBC_BASE_BE);
 122
 123         dev_dbg(priv->dev, "Boot Swap: %s\n", is_swapped ? "on" : "off");
 124
 125         /*
 126          * If BOOT_SWAP was asserted on power-on-reset, the CS0 and CS1 are
 127          * swapped.  In this case, bank0 and bank1 should be swapped as well.
 128          */
 129         if (is_swapped)
 130                 swap(priv->bank[0], priv->bank[1]);
 131 }
 132
 133 static void uniphier_system_bus_set_reg(
 134                                 const struct uniphier_system_bus_priv *priv)
 135 {
 136         void __iomem *base_reg = priv->membase + UNIPHIER_SBC_BASE;
 137         u32 base, end, mask, val;
 138         int i;
 139
 140         for (i = 0; i < ARRAY_SIZE(priv->bank); i++) {
 141                 base = priv->bank[i].base;
 142                 end = priv->bank[i].end;
 143
 144                 if (base == end) {
 145                         /*
 146                          * If SBC_BASE0 or SBC_BASE1 is set to zero, the access
 147                          * to anywhere in the system bus space is routed to
 148                          * bank 0 (if boot swap if off) or bank 1 (if boot swap
 149                          * if on).  It means that CPUs cannot get access to
 150                          * bank 2 or later.  In other words, bank 0/1 cannot
 151                          * be disabled even if its bank_enable bits is cleared.
 152                          * This seems odd, but it is how this hardware goes.
 153                          * As a workaround, dummy data (0xffffffff) should be
 154                          * set when the bank 0/1 is unused.  As for bank 2 and
 155                          * later, they can be simply disable by clearing the
 156                          * bank_enable bit.
 157                          */
 158                         if (i < 2)
 159                                 val = UNIPHIER_SBC_BASE_DUMMY;
 160                         else
 161                                 val = 0;
 162                 } else {
 163                         mask = base ^ (end - 1);
 164
 165                         val = base & 0xfffe0000;
 166                         val |= (~mask >> 16) & 0xfffe;
 167                         val |= UNIPHIER_SBC_BASE_BE;
 168                 }
 169                 dev_dbg(priv->dev, "SBC_BASE[%d] = 0x%08x\n", i, val);
 170
 171                 writel(val, base_reg + UNIPHIER_SBC_STRIDE * i);
 172         }
 173 }
 174
 175 static int uniphier_system_bus_probe(struct platform_device *pdev)
 176 {
 177         struct device *dev = &pdev->dev;
 178         struct uniphier_system_bus_priv *priv;
 179         struct resource *regs;
 180         const __be32 *ranges;
 181         u32 cells, addr, size;
 182         u64 paddr;
 183         int pna, bank, rlen, rone, ret;
 184
 185         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 186         if (!priv)
 187                 return -ENOMEM;
 188
 189         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 190         priv->membase = devm_ioremap_resource(dev, regs);
 191         if (IS_ERR(priv->membase))
 192                 return PTR_ERR(priv->membase);
 193
 194         priv->dev = dev;
 195
 196         pna = of_n_addr_cells(dev->of_node);
 197
 198         ret = of_property_read_u32(dev->of_node, "#address-cells", &cells);
 199         if (ret) {
 200                 dev_err(dev, "failed to get #address-cells\n");
 201                 return ret;
 202         }
 203         if (cells != 2) {
 204                 dev_err(dev, "#address-cells must be 2\n");
 205                 return -EINVAL;
 206         }
 207
 208         ret = of_property_read_u32(dev->of_node, "#size-cells", &cells);
 209         if (ret) {
 210                 dev_err(dev, "failed to get #size-cells\n");
 211                 return ret;
 212         }
 213         if (cells != 1) {
 214                 dev_err(dev, "#size-cells must be 1\n");
 215                 return -EINVAL;
 216         }
 217
 218         ranges = of_get_property(dev->of_node, "ranges", &rlen);
 219         if (!ranges) {
 220                 dev_err(dev, "failed to get ranges property\n");
 221                 return -ENOENT;
 222         }
 223
 224         rlen /= sizeof(*ranges);
 225         rone = pna + 2;
 226
 227         for (; rlen >= rone; rlen -= rone) {
 228                 bank = be32_to_cpup(ranges++);
 229                 addr = be32_to_cpup(ranges++);
 230                 paddr = of_translate_address(dev->of_node, ranges);
 231                 if (paddr == OF_BAD_ADDR)
 232                         return -EINVAL;
 233                 ranges += pna;
 234                 size = be32_to_cpup(ranges++);
 235
 236                 ret = uniphier_system_bus_add_bank(priv, bank, addr,
 237                                                    paddr, size);
 238                 if (ret)
 239                         return ret;
 240         }
 241
 242         ret = uniphier_system_bus_check_overlap(priv);
 243         if (ret)
 244                 return ret;
 245
 246         uniphier_system_bus_check_boot_swap(priv);
 247
 248         uniphier_system_bus_set_reg(priv);
 249
 250         platform_set_drvdata(pdev, priv);
 251
 252         /* Now, the bus is configured.  Populate platform_devices below it */
 253         return of_platform_default_populate(dev->of_node, NULL, dev);
 254 }
 255
 256 static int __maybe_unused uniphier_system_bus_resume(struct device *dev)
 257 {
 258         uniphier_system_bus_set_reg(dev_get_drvdata(dev));
 259
 260         return 0;
 261 }
 262
 263 static const struct dev_pm_ops uniphier_system_bus_pm_ops = {
 264         SET_SYSTEM_SLEEP_PM_OPS(NULL, uniphier_system_bus_resume)
 265 };
 266
 267 static const struct of_device_id uniphier_system_bus_match[] = {
 268         { .compatible = "socionext,uniphier-system-bus" },
 269         { /* sentinel */ }
 270 };
 271 MODULE_DEVICE_TABLE(of, uniphier_system_bus_match);
 272
 273 static struct platform_driver uniphier_system_bus_driver = {
 274         .probe          = uniphier_system_bus_probe,
 275         .driver = {
 276                 .name   = "uniphier-system-bus",
 277                 .of_match_table = uniphier_system_bus_match,
 278                 .pm = &uniphier_system_bus_pm_ops,
 279         },
 280 };
 281 module_platform_driver(uniphier_system_bus_driver);
 282
 283 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
 284 MODULE_DESCRIPTION("UniPhier System Bus driver");
 285 MODULE_LICENSE("GPL");