drivers/gpio/gpio-ath79.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  Atheros AR71XX/AR724X/AR913X GPIO API support
   4  *
   5  *  Copyright (C) 2015 Alban Bedel <albeu@free.fr>
   6  *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
   7  *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
   8  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   9  */
  10
  11 #include <linux/gpio/driver.h>
  12 #include <linux/platform_data/gpio-ath79.h>
  13 #include <linux/of_device.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/module.h>
  16 #include <linux/irq.h>
  17
  18 #define AR71XX_GPIO_REG_OE              0x00
  19 #define AR71XX_GPIO_REG_IN              0x04
  20 #define AR71XX_GPIO_REG_SET             0x0c
  21 #define AR71XX_GPIO_REG_CLEAR           0x10
  22
  23 #define AR71XX_GPIO_REG_INT_ENABLE      0x14
  24 #define AR71XX_GPIO_REG_INT_TYPE        0x18
  25 #define AR71XX_GPIO_REG_INT_POLARITY    0x1c
  26 #define AR71XX_GPIO_REG_INT_PENDING     0x20
  27 #define AR71XX_GPIO_REG_INT_MASK        0x24
  28
  29 struct ath79_gpio_ctrl {
  30         struct gpio_chip gc;
  31         void __iomem *base;
  32         raw_spinlock_t lock;
  33         unsigned long both_edges;
  34 };
  35
  36 static struct ath79_gpio_ctrl *irq_data_to_ath79_gpio(struct irq_data *data)
  37 {
  38         struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
  39
  40         return container_of(gc, struct ath79_gpio_ctrl, gc);
  41 }
  42
  43 static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg)
  44 {
  45         return readl(ctrl->base + reg);
  46 }
  47
  48 static void ath79_gpio_write(struct ath79_gpio_ctrl *ctrl,
  49                         unsigned reg, u32 val)
  50 {
  51         writel(val, ctrl->base + reg);
  52 }
  53
  54 static bool ath79_gpio_update_bits(
  55         struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits)
  56 {
  57         u32 old_val, new_val;
  58
  59         old_val = ath79_gpio_read(ctrl, reg);
  60         new_val = (old_val & ~mask) | (bits & mask);
  61
  62         if (new_val != old_val)
  63                 ath79_gpio_write(ctrl, reg, new_val);
  64
  65         return new_val != old_val;
  66 }
  67
  68 static void ath79_gpio_irq_unmask(struct irq_data *data)
  69 {
  70         struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
  71         u32 mask = BIT(irqd_to_hwirq(data));
  72         unsigned long flags;
  73
  74         raw_spin_lock_irqsave(&ctrl->lock, flags);
  75         ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
  76         raw_spin_unlock_irqrestore(&ctrl->lock, flags);
  77 }
  78
  79 static void ath79_gpio_irq_mask(struct irq_data *data)
  80 {
  81         struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
  82         u32 mask = BIT(irqd_to_hwirq(data));
  83         unsigned long flags;
  84
  85         raw_spin_lock_irqsave(&ctrl->lock, flags);
  86         ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
  87         raw_spin_unlock_irqrestore(&ctrl->lock, flags);
  88 }
  89
  90 static void ath79_gpio_irq_enable(struct irq_data *data)
  91 {
  92         struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
  93         u32 mask = BIT(irqd_to_hwirq(data));
  94         unsigned long flags;
  95
  96         raw_spin_lock_irqsave(&ctrl->lock, flags);
  97         ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
  98         ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
  99         raw_spin_unlock_irqrestore(&ctrl->lock, flags);
 100 }
 101
 102 static void ath79_gpio_irq_disable(struct irq_data *data)
 103 {
 104         struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
 105         u32 mask = BIT(irqd_to_hwirq(data));
 106         unsigned long flags;
 107
 108         raw_spin_lock_irqsave(&ctrl->lock, flags);
 109         ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
 110         ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
 111         raw_spin_unlock_irqrestore(&ctrl->lock, flags);
 112 }
 113
 114 static int ath79_gpio_irq_set_type(struct irq_data *data,
 115                                 unsigned int flow_type)
 116 {
 117         struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
 118         u32 mask = BIT(irqd_to_hwirq(data));
 119         u32 type = 0, polarity = 0;
 120         unsigned long flags;
 121         bool disabled;
 122
 123         switch (flow_type) {
 124         case IRQ_TYPE_EDGE_RISING:
 125                 polarity |= mask;
 126         case IRQ_TYPE_EDGE_FALLING:
 127         case IRQ_TYPE_EDGE_BOTH:
 128                 break;
 129
 130         case IRQ_TYPE_LEVEL_HIGH:
 131                 polarity |= mask;
 132                 /* fall through */
 133         case IRQ_TYPE_LEVEL_LOW:
 134                 type |= mask;
 135                 break;
 136
 137         default:
 138                 return -EINVAL;
 139         }
 140
 141         raw_spin_lock_irqsave(&ctrl->lock, flags);
 142
 143         if (flow_type == IRQ_TYPE_EDGE_BOTH) {
 144                 ctrl->both_edges |= mask;
 145                 polarity = ~ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
 146         } else {
 147                 ctrl->both_edges &= ~mask;
 148         }
 149
 150         /* As the IRQ configuration can't be loaded atomically we
 151          * have to disable the interrupt while the configuration state
 152          * is invalid.
 153          */
 154         disabled = ath79_gpio_update_bits(
 155                 ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
 156
 157         ath79_gpio_update_bits(
 158                 ctrl, AR71XX_GPIO_REG_INT_TYPE, mask, type);
 159         ath79_gpio_update_bits(
 160                 ctrl, AR71XX_GPIO_REG_INT_POLARITY, mask, polarity);
 161
 162         if (disabled)
 163                 ath79_gpio_update_bits(
 164                         ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
 165
 166         raw_spin_unlock_irqrestore(&ctrl->lock, flags);
 167
 168         return 0;
 169 }
 170
 171 static struct irq_chip ath79_gpio_irqchip = {
 172         .name = "gpio-ath79",
 173         .irq_enable = ath79_gpio_irq_enable,
 174         .irq_disable = ath79_gpio_irq_disable,
 175         .irq_mask = ath79_gpio_irq_mask,
 176         .irq_unmask = ath79_gpio_irq_unmask,
 177         .irq_set_type = ath79_gpio_irq_set_type,
 178 };
 179
 180 static void ath79_gpio_irq_handler(struct irq_desc *desc)
 181 {
 182         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 183         struct irq_chip *irqchip = irq_desc_get_chip(desc);
 184         struct ath79_gpio_ctrl *ctrl =
 185                 container_of(gc, struct ath79_gpio_ctrl, gc);
 186         unsigned long flags, pending;
 187         u32 both_edges, state;
 188         int irq;
 189
 190         chained_irq_enter(irqchip, desc);
 191
 192         raw_spin_lock_irqsave(&ctrl->lock, flags);
 193
 194         pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING);
 195
 196         /* Update the polarity of the both edges irqs */
 197         both_edges = ctrl->both_edges & pending;
 198         if (both_edges) {
 199                 state = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
 200                 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY,
 201                                 both_edges, ~state);
 202         }
 203
 204         raw_spin_unlock_irqrestore(&ctrl->lock, flags);
 205
 206         if (pending) {
 207                 for_each_set_bit(irq, &pending, gc->ngpio)
 208                         generic_handle_irq(
 209                                 irq_linear_revmap(gc->irq.domain, irq));
 210         }
 211
 212         chained_irq_exit(irqchip, desc);
 213 }
 214
 215 static const struct of_device_id ath79_gpio_of_match[] = {
 216         { .compatible = "qca,ar7100-gpio" },
 217         { .compatible = "qca,ar9340-gpio" },
 218         {},
 219 };
 220 MODULE_DEVICE_TABLE(of, ath79_gpio_of_match);
 221
 222 static int ath79_gpio_probe(struct platform_device *pdev)
 223 {
 224         struct ath79_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
 225         struct device *dev = &pdev->dev;
 226         struct device_node *np = dev->of_node;
 227         struct ath79_gpio_ctrl *ctrl;
 228         struct gpio_irq_chip *girq;
 229         struct resource *res;
 230         u32 ath79_gpio_count;
 231         bool oe_inverted;
 232         int err;
 233
 234         ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
 235         if (!ctrl)
 236                 return -ENOMEM;
 237         platform_set_drvdata(pdev, ctrl);
 238
 239         if (np) {
 240                 err = of_property_read_u32(np, "ngpios", &ath79_gpio_count);
 241                 if (err) {
 242                         dev_err(dev, "ngpios property is not valid\n");
 243                         return err;
 244                 }
 245                 oe_inverted = of_device_is_compatible(np, "qca,ar9340-gpio");
 246         } else if (pdata) {
 247                 ath79_gpio_count = pdata->ngpios;
 248                 oe_inverted = pdata->oe_inverted;
 249         } else {
 250                 dev_err(dev, "No DT node or platform data found\n");
 251                 return -EINVAL;
 252         }
 253
 254         if (ath79_gpio_count >= 32) {
 255                 dev_err(dev, "ngpios must be less than 32\n");
 256                 return -EINVAL;
 257         }
 258
 259         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 260         if (!res)
 261                 return -EINVAL;
 262         ctrl->base = devm_ioremap_nocache(dev, res->start, resource_size(res));
 263         if (!ctrl->base)
 264                 return -ENOMEM;
 265
 266         raw_spin_lock_init(&ctrl->lock);
 267         err = bgpio_init(&ctrl->gc, dev, 4,
 268                         ctrl->base + AR71XX_GPIO_REG_IN,
 269                         ctrl->base + AR71XX_GPIO_REG_SET,
 270                         ctrl->base + AR71XX_GPIO_REG_CLEAR,
 271                         oe_inverted ? NULL : ctrl->base + AR71XX_GPIO_REG_OE,
 272                         oe_inverted ? ctrl->base + AR71XX_GPIO_REG_OE : NULL,
 273                         0);
 274         if (err) {
 275                 dev_err(dev, "bgpio_init failed\n");
 276                 return err;
 277         }
 278         /* Use base 0 to stay compatible with legacy platforms */
 279         ctrl->gc.base = 0;
 280
 281         /* Optional interrupt setup */
 282         if (!np || of_property_read_bool(np, "interrupt-controller")) {
 283                 girq = &ctrl->gc.irq;
 284                 girq->chip = &ath79_gpio_irqchip;
 285                 girq->parent_handler = ath79_gpio_irq_handler;
 286                 girq->num_parents = 1;
 287                 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
 288                                              GFP_KERNEL);
 289                 if (!girq->parents)
 290                         return -ENOMEM;
 291                 girq->parents[0] = platform_get_irq(pdev, 0);
 292                 girq->default_type = IRQ_TYPE_NONE;
 293                 girq->handler = handle_simple_irq;
 294         }
 295
 296         err = devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);
 297         if (err) {
 298                 dev_err(dev,
 299                         "cannot add AR71xx GPIO chip, error=%d", err);
 300                 return err;
 301         }
 302         return 0;
 303 }
 304
 305 static struct platform_driver ath79_gpio_driver = {
 306         .driver = {
 307                 .name = "ath79-gpio",
 308                 .of_match_table = ath79_gpio_of_match,
 309         },
 310         .probe = ath79_gpio_probe,
 311 };
 312
 313 module_platform_driver(ath79_gpio_driver);
 314
 315 MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X GPIO API support");
 316 MODULE_LICENSE("GPL v2");