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spi: sprd: adi: Remove redundant address bits setting
[linux/fpc-iii.git] / drivers / gpio / gpio-lynxpoint.c
blob31b4a091ab60aeded67e06607020006e0d49092d
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * GPIO controller driver for Intel Lynxpoint PCH chipset>
4 * Copyright (c) 2012, Intel Corporation.
5 *
6 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
7 */
8
9 #include <linux/acpi.h>
10 #include <linux/bitops.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/slab.h>
19 #include <linux/types.h>
20
21 /* LynxPoint chipset has support for 94 gpio pins */
22
23 #define LP_NUM_GPIO 94
24
25 /* Bitmapped register offsets */
26 #define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */
27 #define LP_GC 0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */
28 #define LP_INT_STAT 0x80
29 #define LP_INT_ENABLE 0x90
30
31 /* Each pin has two 32 bit config registers, starting at 0x100 */
32 #define LP_CONFIG1 0x100
33 #define LP_CONFIG2 0x104
34
35 /* LP_CONFIG1 reg bits */
36 #define OUT_LVL_BIT BIT(31)
37 #define IN_LVL_BIT BIT(30)
38 #define TRIG_SEL_BIT BIT(4) /* 0: Edge, 1: Level */
39 #define INT_INV_BIT BIT(3) /* Invert interrupt triggering */
40 #define DIR_BIT BIT(2) /* 0: Output, 1: Input */
41 #define USE_SEL_BIT BIT(0) /* 0: Native, 1: GPIO */
42
43 /* LP_CONFIG2 reg bits */
44 #define GPINDIS_BIT BIT(2) /* disable input sensing */
45 #define GPIWP_BIT (BIT(0) | BIT(1)) /* weak pull options */
46
47 struct lp_gpio {
48 struct gpio_chip chip;
49 struct platform_device *pdev;
50 spinlock_t lock;
51 unsigned long reg_base;
52 };
53
54 /*
55 * Lynxpoint gpios are controlled through both bitmapped registers and
56 * per gpio specific registers. The bitmapped registers are in chunks of
57 * 3 x 32bit registers to cover all 94 gpios
58 *
59 * per gpio specific registers consist of two 32bit registers per gpio
60 * (LP_CONFIG1 and LP_CONFIG2), with 94 gpios there's a total of
61 * 188 config registers.
62 *
63 * A simplified view of the register layout look like this:
64 *
65 * LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers)
66 * LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63
67 * LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94
68 * ...
69 * LP_INT_ENABLE[31:0] ...
70 * LP_INT_ENABLE[63:31] ...
71 * LP_INT_ENABLE[94:64] ...
72 * LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers)
73 * LP0_CONFIG2 (gpio 0) config2 reg for gpio 0
74 * LP1_CONFIG1 (gpio 1) config1 reg for gpio 1
75 * LP1_CONFIG2 (gpio 1) config2 reg for gpio 1
76 * LP2_CONFIG1 (gpio 2) ...
77 * LP2_CONFIG2 (gpio 2) ...
78 * ...
79 * LP94_CONFIG1 (gpio 94) ...
80 * LP94_CONFIG2 (gpio 94) ...
81 */
82
83 static unsigned long lp_gpio_reg(struct gpio_chip *chip, unsigned offset,
84 int reg)
85 {
86 struct lp_gpio *lg = gpiochip_get_data(chip);
87 int reg_offset;
88
89 if (reg == LP_CONFIG1 || reg == LP_CONFIG2)
90 /* per gpio specific config registers */
91 reg_offset = offset * 8;
92 else
93 /* bitmapped registers */
94 reg_offset = (offset / 32) * 4;
95
96 return lg->reg_base + reg + reg_offset;
97 }
98
99 static int lp_gpio_request(struct gpio_chip *chip, unsigned offset)
100 {
101 struct lp_gpio *lg = gpiochip_get_data(chip);
102 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
103 unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2);
104 unsigned long acpi_use = lp_gpio_reg(chip, offset, LP_ACPI_OWNED);
105
106 pm_runtime_get(&lg->pdev->dev); /* should we put if failed */
107
108 /* Fail if BIOS reserved pin for ACPI use */
109 if (!(inl(acpi_use) & BIT(offset % 32))) {
110 dev_err(&lg->pdev->dev, "gpio %d reserved for ACPI\n", offset);
111 return -EBUSY;
112 }
113 /* Fail if pin is in alternate function mode (not GPIO mode) */
114 if (!(inl(reg) & USE_SEL_BIT))
115 return -ENODEV;
116
117 /* enable input sensing */
118 outl(inl(conf2) & ~GPINDIS_BIT, conf2);
119
120
121 return 0;
122 }
123
124 static void lp_gpio_free(struct gpio_chip *chip, unsigned offset)
125 {
126 struct lp_gpio *lg = gpiochip_get_data(chip);
127 unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2);
128
129 /* disable input sensing */
130 outl(inl(conf2) | GPINDIS_BIT, conf2);
131
132 pm_runtime_put(&lg->pdev->dev);
133 }
134
135 static int lp_irq_type(struct irq_data *d, unsigned type)
136 {
137 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
138 struct lp_gpio *lg = gpiochip_get_data(gc);
139 u32 hwirq = irqd_to_hwirq(d);
140 unsigned long flags;
141 u32 value;
142 unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1);
143
144 if (hwirq >= lg->chip.ngpio)
145 return -EINVAL;
146
147 spin_lock_irqsave(&lg->lock, flags);
148 value = inl(reg);
149
150 /* set both TRIG_SEL and INV bits to 0 for rising edge */
151 if (type & IRQ_TYPE_EDGE_RISING)
152 value &= ~(TRIG_SEL_BIT | INT_INV_BIT);
153
154 /* TRIG_SEL bit 0, INV bit 1 for falling edge */
155 if (type & IRQ_TYPE_EDGE_FALLING)
156 value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT;
157
158 /* TRIG_SEL bit 1, INV bit 0 for level low */
159 if (type & IRQ_TYPE_LEVEL_LOW)
160 value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT;
161
162 /* TRIG_SEL bit 1, INV bit 1 for level high */
163 if (type & IRQ_TYPE_LEVEL_HIGH)
164 value |= TRIG_SEL_BIT | INT_INV_BIT;
165
166 outl(value, reg);
167 spin_unlock_irqrestore(&lg->lock, flags);
168
169 return 0;
170 }
171
172 static int lp_gpio_get(struct gpio_chip *chip, unsigned offset)
173 {
174 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
175 return !!(inl(reg) & IN_LVL_BIT);
176 }
177
178 static void lp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
179 {
180 struct lp_gpio *lg = gpiochip_get_data(chip);
181 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
182 unsigned long flags;
183
184 spin_lock_irqsave(&lg->lock, flags);
185
186 if (value)
187 outl(inl(reg) | OUT_LVL_BIT, reg);
188 else
189 outl(inl(reg) & ~OUT_LVL_BIT, reg);
190
191 spin_unlock_irqrestore(&lg->lock, flags);
192 }
193
194 static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
195 {
196 struct lp_gpio *lg = gpiochip_get_data(chip);
197 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
198 unsigned long flags;
199
200 spin_lock_irqsave(&lg->lock, flags);
201 outl(inl(reg) | DIR_BIT, reg);
202 spin_unlock_irqrestore(&lg->lock, flags);
203
204 return 0;
205 }
206
207 static int lp_gpio_direction_output(struct gpio_chip *chip,
208 unsigned offset, int value)
209 {
210 struct lp_gpio *lg = gpiochip_get_data(chip);
211 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
212 unsigned long flags;
213
214 lp_gpio_set(chip, offset, value);
215
216 spin_lock_irqsave(&lg->lock, flags);
217 outl(inl(reg) & ~DIR_BIT, reg);
218 spin_unlock_irqrestore(&lg->lock, flags);
219
220 return 0;
221 }
222
223 static void lp_gpio_irq_handler(struct irq_desc *desc)
224 {
225 struct irq_data *data = irq_desc_get_irq_data(desc);
226 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
227 struct lp_gpio *lg = gpiochip_get_data(gc);
228 struct irq_chip *chip = irq_data_get_irq_chip(data);
229 unsigned long reg, ena, pending;
230 u32 base, pin;
231
232 /* check from GPIO controller which pin triggered the interrupt */
233 for (base = 0; base < lg->chip.ngpio; base += 32) {
234 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
235 ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
236
237 /* Only interrupts that are enabled */
238 pending = inl(reg) & inl(ena);
239
240 for_each_set_bit(pin, &pending, 32) {
241 unsigned irq;
242
243 /* Clear before handling so we don't lose an edge */
244 outl(BIT(pin), reg);
245
246 irq = irq_find_mapping(lg->chip.irq.domain, base + pin);
247 generic_handle_irq(irq);
248 }
249 }
250 chip->irq_eoi(data);
251 }
252
253 static void lp_irq_unmask(struct irq_data *d)
254 {
255 }
256
257 static void lp_irq_mask(struct irq_data *d)
258 {
259 }
260
261 static void lp_irq_enable(struct irq_data *d)
262 {
263 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
264 struct lp_gpio *lg = gpiochip_get_data(gc);
265 u32 hwirq = irqd_to_hwirq(d);
266 unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
267 unsigned long flags;
268
269 spin_lock_irqsave(&lg->lock, flags);
270 outl(inl(reg) | BIT(hwirq % 32), reg);
271 spin_unlock_irqrestore(&lg->lock, flags);
272 }
273
274 static void lp_irq_disable(struct irq_data *d)
275 {
276 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
277 struct lp_gpio *lg = gpiochip_get_data(gc);
278 u32 hwirq = irqd_to_hwirq(d);
279 unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
280 unsigned long flags;
281
282 spin_lock_irqsave(&lg->lock, flags);
283 outl(inl(reg) & ~BIT(hwirq % 32), reg);
284 spin_unlock_irqrestore(&lg->lock, flags);
285 }
286
287 static struct irq_chip lp_irqchip = {
288 .name = "LP-GPIO",
289 .irq_mask = lp_irq_mask,
290 .irq_unmask = lp_irq_unmask,
291 .irq_enable = lp_irq_enable,
292 .irq_disable = lp_irq_disable,
293 .irq_set_type = lp_irq_type,
294 .flags = IRQCHIP_SKIP_SET_WAKE,
295 };
296
297 static void lp_gpio_irq_init_hw(struct lp_gpio *lg)
298 {
299 unsigned long reg;
300 unsigned base;
301
302 for (base = 0; base < lg->chip.ngpio; base += 32) {
303 /* disable gpio pin interrupts */
304 reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
305 outl(0, reg);
306 /* Clear interrupt status register */
307 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
308 outl(0xffffffff, reg);
309 }
310 }
311
312 static int lp_gpio_probe(struct platform_device *pdev)
313 {
314 struct lp_gpio *lg;
315 struct gpio_chip *gc;
316 struct resource *io_rc, *irq_rc;
317 struct device *dev = &pdev->dev;
318 unsigned long reg_len;
319 int ret = -ENODEV;
320
321 lg = devm_kzalloc(dev, sizeof(struct lp_gpio), GFP_KERNEL);
322 if (!lg)
323 return -ENOMEM;
324
325 lg->pdev = pdev;
326 platform_set_drvdata(pdev, lg);
327
328 io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0);
329 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
330
331 if (!io_rc) {
332 dev_err(dev, "missing IO resources\n");
333 return -EINVAL;
334 }
335
336 lg->reg_base = io_rc->start;
337 reg_len = resource_size(io_rc);
338
339 if (!devm_request_region(dev, lg->reg_base, reg_len, "lp-gpio")) {
340 dev_err(dev, "failed requesting IO region 0x%x\n",
341 (unsigned int)lg->reg_base);
342 return -EBUSY;
343 }
344
345 spin_lock_init(&lg->lock);
346
347 gc = &lg->chip;
348 gc->label = dev_name(dev);
349 gc->owner = THIS_MODULE;
350 gc->request = lp_gpio_request;
351 gc->free = lp_gpio_free;
352 gc->direction_input = lp_gpio_direction_input;
353 gc->direction_output = lp_gpio_direction_output;
354 gc->get = lp_gpio_get;
355 gc->set = lp_gpio_set;
356 gc->base = -1;
357 gc->ngpio = LP_NUM_GPIO;
358 gc->can_sleep = false;
359 gc->parent = dev;
360
361 ret = devm_gpiochip_add_data(dev, gc, lg);
362 if (ret) {
363 dev_err(dev, "failed adding lp-gpio chip\n");
364 return ret;
365 }
366
367 /* set up interrupts */
368 if (irq_rc && irq_rc->start) {
369 lp_gpio_irq_init_hw(lg);
370 ret = gpiochip_irqchip_add(gc, &lp_irqchip, 0,
371 handle_simple_irq, IRQ_TYPE_NONE);
372 if (ret) {
373 dev_err(dev, "failed to add irqchip\n");
374 return ret;
375 }
376
377 gpiochip_set_chained_irqchip(gc, &lp_irqchip,
378 (unsigned)irq_rc->start,
379 lp_gpio_irq_handler);
380 }
381
382 pm_runtime_enable(dev);
383
384 return 0;
385 }
386
387 static int lp_gpio_runtime_suspend(struct device *dev)
388 {
389 return 0;
390 }
391
392 static int lp_gpio_runtime_resume(struct device *dev)
393 {
394 return 0;
395 }
396
397 static int lp_gpio_resume(struct device *dev)
398 {
399 struct lp_gpio *lg = dev_get_drvdata(dev);
400 unsigned long reg;
401 int i;
402
403 /* on some hardware suspend clears input sensing, re-enable it here */
404 for (i = 0; i < lg->chip.ngpio; i++) {
405 if (gpiochip_is_requested(&lg->chip, i) != NULL) {
406 reg = lp_gpio_reg(&lg->chip, i, LP_CONFIG2);
407 outl(inl(reg) & ~GPINDIS_BIT, reg);
408 }
409 }
410 return 0;
411 }
412
413 static const struct dev_pm_ops lp_gpio_pm_ops = {
414 .runtime_suspend = lp_gpio_runtime_suspend,
415 .runtime_resume = lp_gpio_runtime_resume,
416 .resume = lp_gpio_resume,
417 };
418
419 static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = {
420 { "INT33C7", 0 },
421 { "INT3437", 0 },
422 { }
423 };
424 MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match);
425
426 static int lp_gpio_remove(struct platform_device *pdev)
427 {
428 pm_runtime_disable(&pdev->dev);
429 return 0;
430 }
431
432 static struct platform_driver lp_gpio_driver = {
433 .probe = lp_gpio_probe,
434 .remove = lp_gpio_remove,
435 .driver = {
436 .name = "lp_gpio",
437 .pm = &lp_gpio_pm_ops,
438 .acpi_match_table = ACPI_PTR(lynxpoint_gpio_acpi_match),
439 },
440 };
441
442 static int __init lp_gpio_init(void)
443 {
444 return platform_driver_register(&lp_gpio_driver);
445 }
446
447 static void __exit lp_gpio_exit(void)
448 {
449 platform_driver_unregister(&lp_gpio_driver);
450 }
451
452 subsys_initcall(lp_gpio_init);
453 module_exit(lp_gpio_exit);
454
455 MODULE_AUTHOR("Mathias Nyman (Intel)");
456 MODULE_DESCRIPTION("GPIO interface for Intel Lynxpoint");
457 MODULE_LICENSE("GPL v2");
458 MODULE_ALIAS("platform:lp_gpio");
Linux with added FPC-III support