1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale vf610 GPIO support through PORT and GPIO
5 * Copyright (c) 2014 Toradex AG.
7 * Author: Stefan Agner <stefan@agner.ch>.
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/err.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
16 #include <linux/ioport.h>
17 #include <linux/irq.h>
18 #include <linux/platform_device.h>
20 #include <linux/of_device.h>
21 #include <linux/of_irq.h>
23 #define VF610_GPIO_PER_PORT 32
25 struct fsl_gpio_soc_data
{
26 /* SoCs has a Port Data Direction Register (PDDR) */
30 struct vf610_gpio_port
{
34 void __iomem
*gpio_base
;
35 const struct fsl_gpio_soc_data
*sdata
;
36 u8 irqc
[VF610_GPIO_PER_PORT
];
42 #define GPIO_PDOR 0x00
43 #define GPIO_PSOR 0x04
44 #define GPIO_PCOR 0x08
45 #define GPIO_PTOR 0x0c
46 #define GPIO_PDIR 0x10
47 #define GPIO_PDDR 0x14
49 #define PORT_PCR(n) ((n) * 0x4)
50 #define PORT_PCR_IRQC_OFFSET 16
52 #define PORT_ISFR 0xa0
53 #define PORT_DFER 0xc0
54 #define PORT_DFCR 0xc4
55 #define PORT_DFWR 0xc8
57 #define PORT_INT_OFF 0x0
58 #define PORT_INT_LOGIC_ZERO 0x8
59 #define PORT_INT_RISING_EDGE 0x9
60 #define PORT_INT_FALLING_EDGE 0xa
61 #define PORT_INT_EITHER_EDGE 0xb
62 #define PORT_INT_LOGIC_ONE 0xc
64 static const struct fsl_gpio_soc_data imx_data
= {
68 static const struct of_device_id vf610_gpio_dt_ids
[] = {
69 { .compatible
= "fsl,vf610-gpio", .data
= NULL
, },
70 { .compatible
= "fsl,imx7ulp-gpio", .data
= &imx_data
, },
74 static inline void vf610_gpio_writel(u32 val
, void __iomem
*reg
)
76 writel_relaxed(val
, reg
);
79 static inline u32
vf610_gpio_readl(void __iomem
*reg
)
81 return readl_relaxed(reg
);
84 static int vf610_gpio_get(struct gpio_chip
*gc
, unsigned int gpio
)
86 struct vf610_gpio_port
*port
= gpiochip_get_data(gc
);
87 unsigned long mask
= BIT(gpio
);
88 unsigned long offset
= GPIO_PDIR
;
90 if (port
->sdata
&& port
->sdata
->have_paddr
) {
91 mask
&= vf610_gpio_readl(port
->gpio_base
+ GPIO_PDDR
);
96 return !!(vf610_gpio_readl(port
->gpio_base
+ offset
) & BIT(gpio
));
99 static void vf610_gpio_set(struct gpio_chip
*gc
, unsigned int gpio
, int val
)
101 struct vf610_gpio_port
*port
= gpiochip_get_data(gc
);
102 unsigned long mask
= BIT(gpio
);
103 unsigned long offset
= val
? GPIO_PSOR
: GPIO_PCOR
;
105 vf610_gpio_writel(mask
, port
->gpio_base
+ offset
);
108 static int vf610_gpio_direction_input(struct gpio_chip
*chip
, unsigned gpio
)
110 struct vf610_gpio_port
*port
= gpiochip_get_data(chip
);
111 unsigned long mask
= BIT(gpio
);
114 if (port
->sdata
&& port
->sdata
->have_paddr
) {
115 val
= vf610_gpio_readl(port
->gpio_base
+ GPIO_PDDR
);
117 vf610_gpio_writel(val
, port
->gpio_base
+ GPIO_PDDR
);
120 return pinctrl_gpio_direction_input(chip
->base
+ gpio
);
123 static int vf610_gpio_direction_output(struct gpio_chip
*chip
, unsigned gpio
,
126 struct vf610_gpio_port
*port
= gpiochip_get_data(chip
);
127 unsigned long mask
= BIT(gpio
);
129 if (port
->sdata
&& port
->sdata
->have_paddr
)
130 vf610_gpio_writel(mask
, port
->gpio_base
+ GPIO_PDDR
);
132 vf610_gpio_set(chip
, gpio
, value
);
134 return pinctrl_gpio_direction_output(chip
->base
+ gpio
);
137 static void vf610_gpio_irq_handler(struct irq_desc
*desc
)
139 struct vf610_gpio_port
*port
=
140 gpiochip_get_data(irq_desc_get_handler_data(desc
));
141 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
143 unsigned long irq_isfr
;
145 chained_irq_enter(chip
, desc
);
147 irq_isfr
= vf610_gpio_readl(port
->base
+ PORT_ISFR
);
149 for_each_set_bit(pin
, &irq_isfr
, VF610_GPIO_PER_PORT
) {
150 vf610_gpio_writel(BIT(pin
), port
->base
+ PORT_ISFR
);
152 generic_handle_irq(irq_find_mapping(port
->gc
.irq
.domain
, pin
));
155 chained_irq_exit(chip
, desc
);
158 static void vf610_gpio_irq_ack(struct irq_data
*d
)
160 struct vf610_gpio_port
*port
=
161 gpiochip_get_data(irq_data_get_irq_chip_data(d
));
164 vf610_gpio_writel(BIT(gpio
), port
->base
+ PORT_ISFR
);
167 static int vf610_gpio_irq_set_type(struct irq_data
*d
, u32 type
)
169 struct vf610_gpio_port
*port
=
170 gpiochip_get_data(irq_data_get_irq_chip_data(d
));
174 case IRQ_TYPE_EDGE_RISING
:
175 irqc
= PORT_INT_RISING_EDGE
;
177 case IRQ_TYPE_EDGE_FALLING
:
178 irqc
= PORT_INT_FALLING_EDGE
;
180 case IRQ_TYPE_EDGE_BOTH
:
181 irqc
= PORT_INT_EITHER_EDGE
;
183 case IRQ_TYPE_LEVEL_LOW
:
184 irqc
= PORT_INT_LOGIC_ZERO
;
186 case IRQ_TYPE_LEVEL_HIGH
:
187 irqc
= PORT_INT_LOGIC_ONE
;
193 port
->irqc
[d
->hwirq
] = irqc
;
195 if (type
& IRQ_TYPE_LEVEL_MASK
)
196 irq_set_handler_locked(d
, handle_level_irq
);
198 irq_set_handler_locked(d
, handle_edge_irq
);
203 static void vf610_gpio_irq_mask(struct irq_data
*d
)
205 struct vf610_gpio_port
*port
=
206 gpiochip_get_data(irq_data_get_irq_chip_data(d
));
207 void __iomem
*pcr_base
= port
->base
+ PORT_PCR(d
->hwirq
);
209 vf610_gpio_writel(0, pcr_base
);
212 static void vf610_gpio_irq_unmask(struct irq_data
*d
)
214 struct vf610_gpio_port
*port
=
215 gpiochip_get_data(irq_data_get_irq_chip_data(d
));
216 void __iomem
*pcr_base
= port
->base
+ PORT_PCR(d
->hwirq
);
218 vf610_gpio_writel(port
->irqc
[d
->hwirq
] << PORT_PCR_IRQC_OFFSET
,
222 static int vf610_gpio_irq_set_wake(struct irq_data
*d
, u32 enable
)
224 struct vf610_gpio_port
*port
=
225 gpiochip_get_data(irq_data_get_irq_chip_data(d
));
228 enable_irq_wake(port
->irq
);
230 disable_irq_wake(port
->irq
);
235 static void vf610_gpio_disable_clk(void *data
)
237 clk_disable_unprepare(data
);
240 static int vf610_gpio_probe(struct platform_device
*pdev
)
242 struct device
*dev
= &pdev
->dev
;
243 struct device_node
*np
= dev
->of_node
;
244 struct vf610_gpio_port
*port
;
245 struct gpio_chip
*gc
;
250 port
= devm_kzalloc(dev
, sizeof(*port
), GFP_KERNEL
);
254 port
->sdata
= of_device_get_match_data(dev
);
255 port
->base
= devm_platform_ioremap_resource(pdev
, 0);
256 if (IS_ERR(port
->base
))
257 return PTR_ERR(port
->base
);
259 port
->gpio_base
= devm_platform_ioremap_resource(pdev
, 1);
260 if (IS_ERR(port
->gpio_base
))
261 return PTR_ERR(port
->gpio_base
);
263 port
->irq
= platform_get_irq(pdev
, 0);
267 port
->clk_port
= devm_clk_get(dev
, "port");
268 ret
= PTR_ERR_OR_ZERO(port
->clk_port
);
270 ret
= clk_prepare_enable(port
->clk_port
);
273 ret
= devm_add_action_or_reset(dev
, vf610_gpio_disable_clk
,
277 } else if (ret
== -EPROBE_DEFER
) {
279 * Percolate deferrals, for anything else,
280 * just live without the clocking.
285 port
->clk_gpio
= devm_clk_get(dev
, "gpio");
286 ret
= PTR_ERR_OR_ZERO(port
->clk_gpio
);
288 ret
= clk_prepare_enable(port
->clk_gpio
);
291 ret
= devm_add_action_or_reset(dev
, vf610_gpio_disable_clk
,
295 } else if (ret
== -EPROBE_DEFER
) {
302 gc
->label
= "vf610-gpio";
303 gc
->ngpio
= VF610_GPIO_PER_PORT
;
304 gc
->base
= of_alias_get_id(np
, "gpio") * VF610_GPIO_PER_PORT
;
306 gc
->request
= gpiochip_generic_request
;
307 gc
->free
= gpiochip_generic_free
;
308 gc
->direction_input
= vf610_gpio_direction_input
;
309 gc
->get
= vf610_gpio_get
;
310 gc
->direction_output
= vf610_gpio_direction_output
;
311 gc
->set
= vf610_gpio_set
;
314 ic
->name
= "gpio-vf610";
315 ic
->irq_ack
= vf610_gpio_irq_ack
;
316 ic
->irq_mask
= vf610_gpio_irq_mask
;
317 ic
->irq_unmask
= vf610_gpio_irq_unmask
;
318 ic
->irq_set_type
= vf610_gpio_irq_set_type
;
319 ic
->irq_set_wake
= vf610_gpio_irq_set_wake
;
321 ret
= devm_gpiochip_add_data(dev
, gc
, port
);
325 /* Mask all GPIO interrupts */
326 for (i
= 0; i
< gc
->ngpio
; i
++)
327 vf610_gpio_writel(0, port
->base
+ PORT_PCR(i
));
329 /* Clear the interrupt status register for all GPIO's */
330 vf610_gpio_writel(~0, port
->base
+ PORT_ISFR
);
332 ret
= gpiochip_irqchip_add(gc
, ic
, 0, handle_edge_irq
, IRQ_TYPE_NONE
);
334 dev_err(dev
, "failed to add irqchip\n");
337 gpiochip_set_chained_irqchip(gc
, ic
, port
->irq
,
338 vf610_gpio_irq_handler
);
343 static struct platform_driver vf610_gpio_driver
= {
345 .name
= "gpio-vf610",
346 .of_match_table
= vf610_gpio_dt_ids
,
348 .probe
= vf610_gpio_probe
,
351 builtin_platform_driver(vf610_gpio_driver
);