1 /* Copyright (c) 2012, The Linux Foundation. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/types.h>
17 #include <linux/device.h>
19 #include <linux/err.h>
21 #include <linux/miscdevice.h>
22 #include <linux/uaccess.h>
23 #include <linux/slab.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/spinlock.h>
26 #include <linux/clk.h>
28 #include <linux/coresight.h>
29 #include <linux/amba/bus.h>
31 #include "coresight-priv.h"
41 #define TMC_MODE 0x028
42 #define TMC_LBUFLEVEL 0x02c
43 #define TMC_CBUFLEVEL 0x030
44 #define TMC_BUFWM 0x034
45 #define TMC_RRPHI 0x038
46 #define TMC_RWPHI 0x03c
47 #define TMC_AXICTL 0x110
48 #define TMC_DBALO 0x118
49 #define TMC_DBAHI 0x11c
50 #define TMC_FFSR 0x300
51 #define TMC_FFCR 0x304
52 #define TMC_PSCR 0x308
53 #define TMC_ITMISCOP0 0xee0
54 #define TMC_ITTRFLIN 0xee8
55 #define TMC_ITATBDATA0 0xeec
56 #define TMC_ITATBCTR2 0xef0
57 #define TMC_ITATBCTR1 0xef4
58 #define TMC_ITATBCTR0 0xef8
60 /* register description */
62 #define TMC_CTL_CAPT_EN BIT(0)
64 #define TMC_STS_TRIGGERED BIT(1)
65 /* TMC_AXICTL - 0x110 */
66 #define TMC_AXICTL_PROT_CTL_B0 BIT(0)
67 #define TMC_AXICTL_PROT_CTL_B1 BIT(1)
68 #define TMC_AXICTL_SCT_GAT_MODE BIT(7)
69 #define TMC_AXICTL_WR_BURST_LEN 0xF00
70 /* TMC_FFCR - 0x304 */
71 #define TMC_FFCR_EN_FMT BIT(0)
72 #define TMC_FFCR_EN_TI BIT(1)
73 #define TMC_FFCR_FON_FLIN BIT(4)
74 #define TMC_FFCR_FON_TRIG_EVT BIT(5)
75 #define TMC_FFCR_FLUSHMAN BIT(6)
76 #define TMC_FFCR_TRIGON_TRIGIN BIT(8)
77 #define TMC_FFCR_STOP_ON_FLUSH BIT(12)
79 #define TMC_STS_TRIGGERED_BIT 2
80 #define TMC_FFCR_FLUSHMAN_BIT 6
82 enum tmc_config_type
{
89 TMC_MODE_CIRCULAR_BUFFER
,
90 TMC_MODE_SOFTWARE_FIFO
,
91 TMC_MODE_HARDWARE_FIFO
,
94 enum tmc_mem_intf_width
{
95 TMC_MEM_INTF_WIDTH_32BITS
= 0x2,
96 TMC_MEM_INTF_WIDTH_64BITS
= 0x3,
97 TMC_MEM_INTF_WIDTH_128BITS
= 0x4,
98 TMC_MEM_INTF_WIDTH_256BITS
= 0x5,
102 * struct tmc_drvdata - specifics associated to an TMC component
103 * @base: memory mapped base address for this component.
104 * @dev: the device entity associated to this component.
105 * @csdev: component vitals needed by the framework.
106 * @miscdev: specifics to handle "/dev/xyz.tmc" entry.
107 * @clk: the clock this component is associated to.
108 * @spinlock: only one at a time pls.
109 * @read_count: manages preparation of buffer for reading.
110 * @buf: area of memory where trace data get sent.
111 * @paddr: DMA start location in RAM.
112 * @vaddr: virtual representation of @paddr.
114 * @enable: this TMC is being used.
115 * @config_type: TMC variant, must be of type @tmc_config_type.
116 * @trigger_cntr: amount of words to store after a trigger.
121 struct coresight_device
*csdev
;
122 struct miscdevice miscdev
;
132 enum tmc_config_type config_type
;
136 static void tmc_wait_for_ready(struct tmc_drvdata
*drvdata
)
138 /* Ensure formatter, unformatter and hardware fifo are empty */
139 if (coresight_timeout(drvdata
->base
,
140 TMC_STS
, TMC_STS_TRIGGERED_BIT
, 1)) {
141 dev_err(drvdata
->dev
,
142 "timeout observed when probing at offset %#x\n",
147 static void tmc_flush_and_stop(struct tmc_drvdata
*drvdata
)
151 ffcr
= readl_relaxed(drvdata
->base
+ TMC_FFCR
);
152 ffcr
|= TMC_FFCR_STOP_ON_FLUSH
;
153 writel_relaxed(ffcr
, drvdata
->base
+ TMC_FFCR
);
154 ffcr
|= TMC_FFCR_FLUSHMAN
;
155 writel_relaxed(ffcr
, drvdata
->base
+ TMC_FFCR
);
156 /* Ensure flush completes */
157 if (coresight_timeout(drvdata
->base
,
158 TMC_FFCR
, TMC_FFCR_FLUSHMAN_BIT
, 0)) {
159 dev_err(drvdata
->dev
,
160 "timeout observed when probing at offset %#x\n",
164 tmc_wait_for_ready(drvdata
);
167 static void tmc_enable_hw(struct tmc_drvdata
*drvdata
)
169 writel_relaxed(TMC_CTL_CAPT_EN
, drvdata
->base
+ TMC_CTL
);
172 static void tmc_disable_hw(struct tmc_drvdata
*drvdata
)
174 writel_relaxed(0x0, drvdata
->base
+ TMC_CTL
);
177 static void tmc_etb_enable_hw(struct tmc_drvdata
*drvdata
)
179 /* Zero out the memory to help with debug */
180 memset(drvdata
->buf
, 0, drvdata
->size
);
182 CS_UNLOCK(drvdata
->base
);
184 writel_relaxed(TMC_MODE_CIRCULAR_BUFFER
, drvdata
->base
+ TMC_MODE
);
185 writel_relaxed(TMC_FFCR_EN_FMT
| TMC_FFCR_EN_TI
|
186 TMC_FFCR_FON_FLIN
| TMC_FFCR_FON_TRIG_EVT
|
187 TMC_FFCR_TRIGON_TRIGIN
,
188 drvdata
->base
+ TMC_FFCR
);
190 writel_relaxed(drvdata
->trigger_cntr
, drvdata
->base
+ TMC_TRG
);
191 tmc_enable_hw(drvdata
);
193 CS_LOCK(drvdata
->base
);
196 static void tmc_etr_enable_hw(struct tmc_drvdata
*drvdata
)
200 /* Zero out the memory to help with debug */
201 memset(drvdata
->vaddr
, 0, drvdata
->size
);
203 CS_UNLOCK(drvdata
->base
);
205 writel_relaxed(drvdata
->size
/ 4, drvdata
->base
+ TMC_RSZ
);
206 writel_relaxed(TMC_MODE_CIRCULAR_BUFFER
, drvdata
->base
+ TMC_MODE
);
208 axictl
= readl_relaxed(drvdata
->base
+ TMC_AXICTL
);
209 axictl
|= TMC_AXICTL_WR_BURST_LEN
;
210 writel_relaxed(axictl
, drvdata
->base
+ TMC_AXICTL
);
211 axictl
&= ~TMC_AXICTL_SCT_GAT_MODE
;
212 writel_relaxed(axictl
, drvdata
->base
+ TMC_AXICTL
);
214 ~(TMC_AXICTL_PROT_CTL_B0
| TMC_AXICTL_PROT_CTL_B1
)) |
215 TMC_AXICTL_PROT_CTL_B1
;
216 writel_relaxed(axictl
, drvdata
->base
+ TMC_AXICTL
);
218 writel_relaxed(drvdata
->paddr
, drvdata
->base
+ TMC_DBALO
);
219 writel_relaxed(0x0, drvdata
->base
+ TMC_DBAHI
);
220 writel_relaxed(TMC_FFCR_EN_FMT
| TMC_FFCR_EN_TI
|
221 TMC_FFCR_FON_FLIN
| TMC_FFCR_FON_TRIG_EVT
|
222 TMC_FFCR_TRIGON_TRIGIN
,
223 drvdata
->base
+ TMC_FFCR
);
224 writel_relaxed(drvdata
->trigger_cntr
, drvdata
->base
+ TMC_TRG
);
225 tmc_enable_hw(drvdata
);
227 CS_LOCK(drvdata
->base
);
230 static void tmc_etf_enable_hw(struct tmc_drvdata
*drvdata
)
232 CS_UNLOCK(drvdata
->base
);
234 writel_relaxed(TMC_MODE_HARDWARE_FIFO
, drvdata
->base
+ TMC_MODE
);
235 writel_relaxed(TMC_FFCR_EN_FMT
| TMC_FFCR_EN_TI
,
236 drvdata
->base
+ TMC_FFCR
);
237 writel_relaxed(0x0, drvdata
->base
+ TMC_BUFWM
);
238 tmc_enable_hw(drvdata
);
240 CS_LOCK(drvdata
->base
);
243 static int tmc_enable(struct tmc_drvdata
*drvdata
, enum tmc_mode mode
)
248 ret
= clk_prepare_enable(drvdata
->clk
);
252 spin_lock_irqsave(&drvdata
->spinlock
, flags
);
253 if (drvdata
->reading
) {
254 spin_unlock_irqrestore(&drvdata
->spinlock
, flags
);
255 clk_disable_unprepare(drvdata
->clk
);
259 if (drvdata
->config_type
== TMC_CONFIG_TYPE_ETB
) {
260 tmc_etb_enable_hw(drvdata
);
261 } else if (drvdata
->config_type
== TMC_CONFIG_TYPE_ETR
) {
262 tmc_etr_enable_hw(drvdata
);
264 if (mode
== TMC_MODE_CIRCULAR_BUFFER
)
265 tmc_etb_enable_hw(drvdata
);
267 tmc_etf_enable_hw(drvdata
);
269 drvdata
->enable
= true;
270 spin_unlock_irqrestore(&drvdata
->spinlock
, flags
);
272 dev_info(drvdata
->dev
, "TMC enabled\n");
276 static int tmc_enable_sink(struct coresight_device
*csdev
)
278 struct tmc_drvdata
*drvdata
= dev_get_drvdata(csdev
->dev
.parent
);
280 return tmc_enable(drvdata
, TMC_MODE_CIRCULAR_BUFFER
);
283 static int tmc_enable_link(struct coresight_device
*csdev
, int inport
,
286 struct tmc_drvdata
*drvdata
= dev_get_drvdata(csdev
->dev
.parent
);
288 return tmc_enable(drvdata
, TMC_MODE_HARDWARE_FIFO
);
291 static void tmc_etb_dump_hw(struct tmc_drvdata
*drvdata
)
293 enum tmc_mem_intf_width memwidth
;
299 memwidth
= BMVAL(readl_relaxed(drvdata
->base
+ CORESIGHT_DEVID
), 8, 10);
300 if (memwidth
== TMC_MEM_INTF_WIDTH_32BITS
)
302 else if (memwidth
== TMC_MEM_INTF_WIDTH_64BITS
)
304 else if (memwidth
== TMC_MEM_INTF_WIDTH_128BITS
)
311 for (i
= 0; i
< memwords
; i
++) {
312 read_data
= readl_relaxed(drvdata
->base
+ TMC_RRD
);
313 if (read_data
== 0xFFFFFFFF)
315 memcpy(bufp
, &read_data
, 4);
321 static void tmc_etb_disable_hw(struct tmc_drvdata
*drvdata
)
323 CS_UNLOCK(drvdata
->base
);
325 tmc_flush_and_stop(drvdata
);
326 tmc_etb_dump_hw(drvdata
);
327 tmc_disable_hw(drvdata
);
329 CS_LOCK(drvdata
->base
);
332 static void tmc_etr_dump_hw(struct tmc_drvdata
*drvdata
)
336 rwp
= readl_relaxed(drvdata
->base
+ TMC_RWP
);
337 val
= readl_relaxed(drvdata
->base
+ TMC_STS
);
339 /* How much memory do we still have */
341 drvdata
->buf
= drvdata
->vaddr
+ rwp
- drvdata
->paddr
;
343 drvdata
->buf
= drvdata
->vaddr
;
346 static void tmc_etr_disable_hw(struct tmc_drvdata
*drvdata
)
348 CS_UNLOCK(drvdata
->base
);
350 tmc_flush_and_stop(drvdata
);
351 tmc_etr_dump_hw(drvdata
);
352 tmc_disable_hw(drvdata
);
354 CS_LOCK(drvdata
->base
);
357 static void tmc_etf_disable_hw(struct tmc_drvdata
*drvdata
)
359 CS_UNLOCK(drvdata
->base
);
361 tmc_flush_and_stop(drvdata
);
362 tmc_disable_hw(drvdata
);
364 CS_LOCK(drvdata
->base
);
367 static void tmc_disable(struct tmc_drvdata
*drvdata
, enum tmc_mode mode
)
371 spin_lock_irqsave(&drvdata
->spinlock
, flags
);
372 if (drvdata
->reading
)
375 if (drvdata
->config_type
== TMC_CONFIG_TYPE_ETB
) {
376 tmc_etb_disable_hw(drvdata
);
377 } else if (drvdata
->config_type
== TMC_CONFIG_TYPE_ETR
) {
378 tmc_etr_disable_hw(drvdata
);
380 if (mode
== TMC_MODE_CIRCULAR_BUFFER
)
381 tmc_etb_disable_hw(drvdata
);
383 tmc_etf_disable_hw(drvdata
);
386 drvdata
->enable
= false;
387 spin_unlock_irqrestore(&drvdata
->spinlock
, flags
);
389 clk_disable_unprepare(drvdata
->clk
);
391 dev_info(drvdata
->dev
, "TMC disabled\n");
394 static void tmc_disable_sink(struct coresight_device
*csdev
)
396 struct tmc_drvdata
*drvdata
= dev_get_drvdata(csdev
->dev
.parent
);
398 tmc_disable(drvdata
, TMC_MODE_CIRCULAR_BUFFER
);
401 static void tmc_disable_link(struct coresight_device
*csdev
, int inport
,
404 struct tmc_drvdata
*drvdata
= dev_get_drvdata(csdev
->dev
.parent
);
406 tmc_disable(drvdata
, TMC_MODE_HARDWARE_FIFO
);
409 static const struct coresight_ops_sink tmc_sink_ops
= {
410 .enable
= tmc_enable_sink
,
411 .disable
= tmc_disable_sink
,
414 static const struct coresight_ops_link tmc_link_ops
= {
415 .enable
= tmc_enable_link
,
416 .disable
= tmc_disable_link
,
419 static const struct coresight_ops tmc_etb_cs_ops
= {
420 .sink_ops
= &tmc_sink_ops
,
423 static const struct coresight_ops tmc_etr_cs_ops
= {
424 .sink_ops
= &tmc_sink_ops
,
427 static const struct coresight_ops tmc_etf_cs_ops
= {
428 .sink_ops
= &tmc_sink_ops
,
429 .link_ops
= &tmc_link_ops
,
432 static int tmc_read_prepare(struct tmc_drvdata
*drvdata
)
438 spin_lock_irqsave(&drvdata
->spinlock
, flags
);
439 if (!drvdata
->enable
)
442 if (drvdata
->config_type
== TMC_CONFIG_TYPE_ETB
) {
443 tmc_etb_disable_hw(drvdata
);
444 } else if (drvdata
->config_type
== TMC_CONFIG_TYPE_ETR
) {
445 tmc_etr_disable_hw(drvdata
);
447 mode
= readl_relaxed(drvdata
->base
+ TMC_MODE
);
448 if (mode
== TMC_MODE_CIRCULAR_BUFFER
) {
449 tmc_etb_disable_hw(drvdata
);
456 drvdata
->reading
= true;
457 spin_unlock_irqrestore(&drvdata
->spinlock
, flags
);
459 dev_info(drvdata
->dev
, "TMC read start\n");
462 spin_unlock_irqrestore(&drvdata
->spinlock
, flags
);
466 static void tmc_read_unprepare(struct tmc_drvdata
*drvdata
)
471 spin_lock_irqsave(&drvdata
->spinlock
, flags
);
472 if (!drvdata
->enable
)
475 if (drvdata
->config_type
== TMC_CONFIG_TYPE_ETB
) {
476 tmc_etb_enable_hw(drvdata
);
477 } else if (drvdata
->config_type
== TMC_CONFIG_TYPE_ETR
) {
478 tmc_etr_enable_hw(drvdata
);
480 mode
= readl_relaxed(drvdata
->base
+ TMC_MODE
);
481 if (mode
== TMC_MODE_CIRCULAR_BUFFER
)
482 tmc_etb_enable_hw(drvdata
);
485 drvdata
->reading
= false;
486 spin_unlock_irqrestore(&drvdata
->spinlock
, flags
);
488 dev_info(drvdata
->dev
, "TMC read end\n");
491 static int tmc_open(struct inode
*inode
, struct file
*file
)
493 struct tmc_drvdata
*drvdata
= container_of(file
->private_data
,
494 struct tmc_drvdata
, miscdev
);
497 if (drvdata
->read_count
++)
500 ret
= tmc_read_prepare(drvdata
);
504 nonseekable_open(inode
, file
);
506 dev_dbg(drvdata
->dev
, "%s: successfully opened\n", __func__
);
510 static ssize_t
tmc_read(struct file
*file
, char __user
*data
, size_t len
,
513 struct tmc_drvdata
*drvdata
= container_of(file
->private_data
,
514 struct tmc_drvdata
, miscdev
);
515 char *bufp
= drvdata
->buf
+ *ppos
;
517 if (*ppos
+ len
> drvdata
->size
)
518 len
= drvdata
->size
- *ppos
;
520 if (drvdata
->config_type
== TMC_CONFIG_TYPE_ETR
) {
521 if (bufp
== (char *)(drvdata
->vaddr
+ drvdata
->size
))
522 bufp
= drvdata
->vaddr
;
523 else if (bufp
> (char *)(drvdata
->vaddr
+ drvdata
->size
))
524 bufp
-= drvdata
->size
;
525 if ((bufp
+ len
) > (char *)(drvdata
->vaddr
+ drvdata
->size
))
526 len
= (char *)(drvdata
->vaddr
+ drvdata
->size
) - bufp
;
529 if (copy_to_user(data
, bufp
, len
)) {
530 dev_dbg(drvdata
->dev
, "%s: copy_to_user failed\n", __func__
);
536 dev_dbg(drvdata
->dev
, "%s: %d bytes copied, %d bytes left\n",
537 __func__
, len
, (int) (drvdata
->size
- *ppos
));
541 static int tmc_release(struct inode
*inode
, struct file
*file
)
543 struct tmc_drvdata
*drvdata
= container_of(file
->private_data
,
544 struct tmc_drvdata
, miscdev
);
546 if (--drvdata
->read_count
) {
547 if (drvdata
->read_count
< 0) {
548 dev_err(drvdata
->dev
, "mismatched close\n");
549 drvdata
->read_count
= 0;
554 tmc_read_unprepare(drvdata
);
556 dev_dbg(drvdata
->dev
, "%s: released\n", __func__
);
560 static const struct file_operations tmc_fops
= {
561 .owner
= THIS_MODULE
,
564 .release
= tmc_release
,
568 static ssize_t
trigger_cntr_show(struct device
*dev
,
569 struct device_attribute
*attr
, char *buf
)
571 struct tmc_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
572 unsigned long val
= drvdata
->trigger_cntr
;
574 return sprintf(buf
, "%#lx\n", val
);
577 static ssize_t
trigger_cntr_store(struct device
*dev
,
578 struct device_attribute
*attr
,
579 const char *buf
, size_t size
)
583 struct tmc_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
585 ret
= kstrtoul(buf
, 16, &val
);
589 drvdata
->trigger_cntr
= val
;
592 static DEVICE_ATTR_RW(trigger_cntr
);
594 static struct attribute
*coresight_etb_attrs
[] = {
595 &dev_attr_trigger_cntr
.attr
,
598 ATTRIBUTE_GROUPS(coresight_etb
);
600 static struct attribute
*coresight_etr_attrs
[] = {
601 &dev_attr_trigger_cntr
.attr
,
604 ATTRIBUTE_GROUPS(coresight_etr
);
606 static struct attribute
*coresight_etf_attrs
[] = {
607 &dev_attr_trigger_cntr
.attr
,
610 ATTRIBUTE_GROUPS(coresight_etf
);
612 static int tmc_probe(struct amba_device
*adev
, const struct amba_id
*id
)
617 struct device
*dev
= &adev
->dev
;
618 struct coresight_platform_data
*pdata
= NULL
;
619 struct tmc_drvdata
*drvdata
;
620 struct resource
*res
= &adev
->res
;
621 struct coresight_desc
*desc
;
622 struct device_node
*np
= adev
->dev
.of_node
;
625 pdata
= of_get_coresight_platform_data(dev
, np
);
627 return PTR_ERR(pdata
);
628 adev
->dev
.platform_data
= pdata
;
631 drvdata
= devm_kzalloc(dev
, sizeof(*drvdata
), GFP_KERNEL
);
635 drvdata
->dev
= &adev
->dev
;
636 dev_set_drvdata(dev
, drvdata
);
638 /* Validity for the resource is already checked by the AMBA core */
639 base
= devm_ioremap_resource(dev
, res
);
641 return PTR_ERR(base
);
643 drvdata
->base
= base
;
645 spin_lock_init(&drvdata
->spinlock
);
647 drvdata
->clk
= adev
->pclk
;
648 ret
= clk_prepare_enable(drvdata
->clk
);
652 devid
= readl_relaxed(drvdata
->base
+ CORESIGHT_DEVID
);
653 drvdata
->config_type
= BMVAL(devid
, 6, 7);
655 if (drvdata
->config_type
== TMC_CONFIG_TYPE_ETR
) {
657 ret
= of_property_read_u32(np
,
661 drvdata
->size
= SZ_1M
;
663 drvdata
->size
= readl_relaxed(drvdata
->base
+ TMC_RSZ
) * 4;
666 clk_disable_unprepare(drvdata
->clk
);
668 if (drvdata
->config_type
== TMC_CONFIG_TYPE_ETR
) {
669 drvdata
->vaddr
= dma_alloc_coherent(dev
, drvdata
->size
,
670 &drvdata
->paddr
, GFP_KERNEL
);
674 memset(drvdata
->vaddr
, 0, drvdata
->size
);
675 drvdata
->buf
= drvdata
->vaddr
;
677 drvdata
->buf
= devm_kzalloc(dev
, drvdata
->size
, GFP_KERNEL
);
682 desc
= devm_kzalloc(dev
, sizeof(*desc
), GFP_KERNEL
);
685 goto err_devm_kzalloc
;
690 desc
->subtype
.sink_subtype
= CORESIGHT_DEV_SUBTYPE_SINK_BUFFER
;
692 if (drvdata
->config_type
== TMC_CONFIG_TYPE_ETB
) {
693 desc
->type
= CORESIGHT_DEV_TYPE_SINK
;
694 desc
->ops
= &tmc_etb_cs_ops
;
695 desc
->groups
= coresight_etb_groups
;
696 } else if (drvdata
->config_type
== TMC_CONFIG_TYPE_ETR
) {
697 desc
->type
= CORESIGHT_DEV_TYPE_SINK
;
698 desc
->ops
= &tmc_etr_cs_ops
;
699 desc
->groups
= coresight_etr_groups
;
701 desc
->type
= CORESIGHT_DEV_TYPE_LINKSINK
;
702 desc
->subtype
.link_subtype
= CORESIGHT_DEV_SUBTYPE_LINK_FIFO
;
703 desc
->ops
= &tmc_etf_cs_ops
;
704 desc
->groups
= coresight_etf_groups
;
707 drvdata
->csdev
= coresight_register(desc
);
708 if (IS_ERR(drvdata
->csdev
)) {
709 ret
= PTR_ERR(drvdata
->csdev
);
710 goto err_devm_kzalloc
;
713 drvdata
->miscdev
.name
= pdata
->name
;
714 drvdata
->miscdev
.minor
= MISC_DYNAMIC_MINOR
;
715 drvdata
->miscdev
.fops
= &tmc_fops
;
716 ret
= misc_register(&drvdata
->miscdev
);
718 goto err_misc_register
;
720 dev_info(dev
, "TMC initialized\n");
724 coresight_unregister(drvdata
->csdev
);
726 if (drvdata
->config_type
== TMC_CONFIG_TYPE_ETR
)
727 dma_free_coherent(dev
, drvdata
->size
,
728 &drvdata
->paddr
, GFP_KERNEL
);
732 static int tmc_remove(struct amba_device
*adev
)
734 struct tmc_drvdata
*drvdata
= amba_get_drvdata(adev
);
736 misc_deregister(&drvdata
->miscdev
);
737 coresight_unregister(drvdata
->csdev
);
738 if (drvdata
->config_type
== TMC_CONFIG_TYPE_ETR
)
739 dma_free_coherent(drvdata
->dev
, drvdata
->size
,
740 &drvdata
->paddr
, GFP_KERNEL
);
745 static struct amba_id tmc_ids
[] = {
753 static struct amba_driver tmc_driver
= {
755 .name
= "coresight-tmc",
756 .owner
= THIS_MODULE
,
759 .remove
= tmc_remove
,
763 static int __init
tmc_init(void)
765 return amba_driver_register(&tmc_driver
);
767 module_init(tmc_init
);
769 static void __exit
tmc_exit(void)
771 amba_driver_unregister(&tmc_driver
);
773 module_exit(tmc_exit
);
775 MODULE_LICENSE("GPL v2");
776 MODULE_DESCRIPTION("CoreSight Trace Memory Controller driver");