arch/powerpc/include/asm/pci-bridge.h

   1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H
   2 #define _ASM_POWERPC_PCI_BRIDGE_H
   3 #ifdef __KERNEL__
   4 /*
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version
   8  * 2 of the License, or (at your option) any later version.
   9  */
  10 #include <linux/pci.h>
  11 #include <linux/list.h>
  12 #include <linux/ioport.h>
  13 #include <asm-generic/pci-bridge.h>
  14
  15 struct device_node;
  16
  17 /*
  18  * Structure of a PCI controller (host bridge)
  19  */
  20 struct pci_controller {
  21         struct pci_bus *bus;
  22         char is_dynamic;
  23 #ifdef CONFIG_PPC64
  24         int node;
  25 #endif
  26         struct device_node *dn;
  27         struct list_head list_node;
  28         struct device *parent;
  29
  30         int first_busno;
  31         int last_busno;
  32         int self_busno;
  33
  34         void __iomem *io_base_virt;
  35 #ifdef CONFIG_PPC64
  36         void *io_base_alloc;
  37 #endif
  38         resource_size_t io_base_phys;
  39         resource_size_t pci_io_size;
  40
  41         /* Some machines (PReP) have a non 1:1 mapping of
  42          * the PCI memory space in the CPU bus space
  43          */
  44         resource_size_t pci_mem_offset;
  45
  46         /* Some machines have a special region to forward the ISA
  47          * "memory" cycles such as VGA memory regions. Left to 0
  48          * if unsupported
  49          */
  50         resource_size_t isa_mem_phys;
  51         resource_size_t isa_mem_size;
  52
  53         struct pci_ops *ops;
  54         unsigned int __iomem *cfg_addr;
  55         void __iomem *cfg_data;
  56
  57         /*
  58          * Used for variants of PCI indirect handling and possible quirks:
  59          *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
  60          *  EXT_REG - provides access to PCI-e extended registers
  61          *  SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
  62          *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
  63          *   to determine which bus number to match on when generating type0
  64          *   config cycles
  65          *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
  66          *   hanging if we don't have link and try to do config cycles to
  67          *   anything but the PHB.  Only allow talking to the PHB if this is
  68          *   set.
  69          *  BIG_ENDIAN - cfg_addr is a big endian register
  70          *  BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
  71          *   the PLB4.  Effectively disable MRM commands by setting this.
  72          */
  73 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE          0x00000001
  74 #define PPC_INDIRECT_TYPE_EXT_REG               0x00000002
  75 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS  0x00000004
  76 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK          0x00000008
  77 #define PPC_INDIRECT_TYPE_BIG_ENDIAN            0x00000010
  78 #define PPC_INDIRECT_TYPE_BROKEN_MRM            0x00000020
  79         u32 indirect_type;
  80         /* Currently, we limit ourselves to 1 IO range and 3 mem
  81          * ranges since the common pci_bus structure can't handle more
  82          */
  83         struct resource io_resource;
  84         struct resource mem_resources[3];
  85         int global_number;              /* PCI domain number */
  86
  87         resource_size_t dma_window_base_cur;
  88         resource_size_t dma_window_size;
  89
  90 #ifdef CONFIG_PPC64
  91         unsigned long buid;
  92
  93         void *private_data;
  94 #endif  /* CONFIG_PPC64 */
  95 };
  96
  97 /* These are used for config access before all the PCI probing
  98    has been done. */
  99 extern int early_read_config_byte(struct pci_controller *hose, int bus,
 100                         int dev_fn, int where, u8 *val);
 101 extern int early_read_config_word(struct pci_controller *hose, int bus,
 102                         int dev_fn, int where, u16 *val);
 103 extern int early_read_config_dword(struct pci_controller *hose, int bus,
 104                         int dev_fn, int where, u32 *val);
 105 extern int early_write_config_byte(struct pci_controller *hose, int bus,
 106                         int dev_fn, int where, u8 val);
 107 extern int early_write_config_word(struct pci_controller *hose, int bus,
 108                         int dev_fn, int where, u16 val);
 109 extern int early_write_config_dword(struct pci_controller *hose, int bus,
 110                         int dev_fn, int where, u32 val);
 111
 112 extern int early_find_capability(struct pci_controller *hose, int bus,
 113                                  int dev_fn, int cap);
 114
 115 extern void setup_indirect_pci(struct pci_controller* hose,
 116                                resource_size_t cfg_addr,
 117                                resource_size_t cfg_data, u32 flags);
 118
 119 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
 120 {
 121         return bus->sysdata;
 122 }
 123
 124 #ifndef CONFIG_PPC64
 125
 126 extern int pci_device_from_OF_node(struct device_node *node,
 127                                    u8 *bus, u8 *devfn);
 128 extern void pci_create_OF_bus_map(void);
 129
 130 static inline int isa_vaddr_is_ioport(void __iomem *address)
 131 {
 132         /* No specific ISA handling on ppc32 at this stage, it
 133          * all goes through PCI
 134          */
 135         return 0;
 136 }
 137
 138 #else   /* CONFIG_PPC64 */
 139
 140 /*
 141  * PCI stuff, for nodes representing PCI devices, pointed to
 142  * by device_node->data.
 143  */
 144 struct iommu_table;
 145
 146 struct pci_dn {
 147         int     busno;                  /* pci bus number */
 148         int     devfn;                  /* pci device and function number */
 149
 150         struct  pci_controller *phb;    /* for pci devices */
 151         struct  iommu_table *iommu_table;       /* for phb's or bridges */
 152         struct  device_node *node;      /* back-pointer to the device_node */
 153
 154         int     pci_ext_config_space;   /* for pci devices */
 155
 156 #ifdef CONFIG_EEH
 157         struct  pci_dev *pcidev;        /* back-pointer to the pci device */
 158         int     class_code;             /* pci device class */
 159         int     eeh_mode;               /* See eeh.h for possible EEH_MODEs */
 160         int     eeh_config_addr;
 161         int     eeh_pe_config_addr; /* new-style partition endpoint address */
 162         int     eeh_check_count;        /* # times driver ignored error */
 163         int     eeh_freeze_count;       /* # times this device froze up. */
 164         int     eeh_false_positives;    /* # times this device reported #ff's */
 165         u32     config_space[16];       /* saved PCI config space */
 166 #endif
 167 };
 168
 169 /* Get the pointer to a device_node's pci_dn */
 170 #define PCI_DN(dn)      ((struct pci_dn *) (dn)->data)
 171
 172 extern void * update_dn_pci_info(struct device_node *dn, void *data);
 173
 174 static inline int pci_device_from_OF_node(struct device_node *np,
 175                                           u8 *bus, u8 *devfn)
 176 {
 177         if (!PCI_DN(np))
 178                 return -ENODEV;
 179         *bus = PCI_DN(np)->busno;
 180         *devfn = PCI_DN(np)->devfn;
 181         return 0;
 182 }
 183
 184 /** Find the bus corresponding to the indicated device node */
 185 extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
 186
 187 /** Remove all of the PCI devices under this bus */
 188 extern void pcibios_remove_pci_devices(struct pci_bus *bus);
 189
 190 /** Discover new pci devices under this bus, and add them */
 191 extern void pcibios_add_pci_devices(struct pci_bus *bus);
 192
 193
 194 extern void isa_bridge_find_early(struct pci_controller *hose);
 195
 196 static inline int isa_vaddr_is_ioport(void __iomem *address)
 197 {
 198         /* Check if address hits the reserved legacy IO range */
 199         unsigned long ea = (unsigned long)address;
 200         return ea >= ISA_IO_BASE && ea < ISA_IO_END;
 201 }
 202
 203 extern int pcibios_unmap_io_space(struct pci_bus *bus);
 204 extern int pcibios_map_io_space(struct pci_bus *bus);
 205
 206 #ifdef CONFIG_NUMA
 207 #define PHB_SET_NODE(PHB, NODE)         ((PHB)->node = (NODE))
 208 #else
 209 #define PHB_SET_NODE(PHB, NODE)         ((PHB)->node = -1)
 210 #endif
 211
 212 #endif  /* CONFIG_PPC64 */
 213
 214 /* Get the PCI host controller for an OF device */
 215 extern struct pci_controller *pci_find_hose_for_OF_device(
 216                         struct device_node* node);
 217
 218 /* Fill up host controller resources from the OF node */
 219 extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
 220                         struct device_node *dev, int primary);
 221
 222 /* Allocate & free a PCI host bridge structure */
 223 extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
 224 extern void pcibios_free_controller(struct pci_controller *phb);
 225 extern void pcibios_setup_phb_resources(struct pci_controller *hose);
 226
 227 #ifdef CONFIG_PCI
 228 extern int pcibios_vaddr_is_ioport(void __iomem *address);
 229 #else
 230 static inline int pcibios_vaddr_is_ioport(void __iomem *address)
 231 {
 232         return 0;
 233 }
 234 #endif  /* CONFIG_PCI */
 235
 236 #endif  /* __KERNEL__ */
 237 #endif  /* _ASM_POWERPC_PCI_BRIDGE_H */